1 //===- IA64RegisterInfo.cpp - IA64 Register Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the IA64 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on IA64.
13 //===----------------------------------------------------------------------===//
16 #include "IA64RegisterInfo.h"
17 #include "IA64InstrBuilder.h"
18 #include "IA64MachineFunctionInfo.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Type.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineLocation.h"
26 #include "llvm/Target/TargetFrameInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/ADT/STLExtras.h"
35 IA64RegisterInfo::IA64RegisterInfo()
36 : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP) {}
38 void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
39 MachineBasicBlock::iterator MI,
40 unsigned SrcReg, int FrameIdx,
41 const TargetRegisterClass *RC) const{
43 if (RC == IA64::FPRegisterClass) {
44 BuildMI(MBB, MI, IA64::STF_SPILL, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
45 } else if (RC == IA64::GRRegisterClass) {
46 BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
48 else if (RC == IA64::PRRegisterClass) {
49 /* we use IA64::r2 as a temporary register for doing this hackery. */
51 BuildMI(MBB, MI, IA64::MOV, 1, IA64::r2).addReg(IA64::r0);
52 // then conditionally add 1:
53 BuildMI(MBB, MI, IA64::CADDIMM22, 3, IA64::r2).addReg(IA64::r2)
54 .addImm(1).addReg(SrcReg);
55 // and then store it to the stack
56 BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(IA64::r2);
58 "sorry, I don't know how to store this sort of reg in the stack\n");
61 void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MI,
63 unsigned DestReg, int FrameIdx,
64 const TargetRegisterClass *RC)const{
66 if (RC == IA64::FPRegisterClass) {
67 BuildMI(MBB, MI, IA64::LDF_FILL, 1, DestReg).addFrameIndex(FrameIdx);
68 } else if (RC == IA64::GRRegisterClass) {
69 BuildMI(MBB, MI, IA64::LD8, 1, DestReg).addFrameIndex(FrameIdx);
70 } else if (RC == IA64::PRRegisterClass) {
71 // first we load a byte from the stack into r2, our 'predicate hackery'
73 BuildMI(MBB, MI, IA64::LD8, 1, IA64::r2).addFrameIndex(FrameIdx);
74 // then we compare it to zero. If it _is_ zero, compare-not-equal to
75 // r0 gives us 0, which is what we want, so that's nice.
76 BuildMI(MBB, MI, IA64::CMPNE, 2, DestReg).addReg(IA64::r2).addReg(IA64::r0);
78 "sorry, I don't know how to load this sort of reg from the stack\n");
81 void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator MI,
83 unsigned DestReg, unsigned SrcReg,
84 const TargetRegisterClass *RC) const {
86 if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
87 // (SrcReg) DestReg = cmp.eq.unc(r0, r0)
88 BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg)
89 .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
90 else // otherwise, MOV works (for both gen. regs and FP regs)
91 BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg);
94 const unsigned* IA64RegisterInfo::getCalleeSaveRegs() const {
95 static const unsigned CalleeSaveRegs[] = {
98 return CalleeSaveRegs;
101 const TargetRegisterClass* const*
102 IA64RegisterInfo::getCalleeSaveRegClasses() const {
103 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
106 return CalleeSaveRegClasses;
109 //===----------------------------------------------------------------------===//
110 // Stack Frame Processing methods
111 //===----------------------------------------------------------------------===//
113 // hasFP - Return true if the specified function should have a dedicated frame
114 // pointer register. This is true if the function has variable sized allocas or
115 // if frame pointer elimination is disabled.
117 static bool hasFP(const MachineFunction &MF) {
118 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
121 void IA64RegisterInfo::
122 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator I) const {
126 // If we have a frame pointer, turn the adjcallstackup instruction into a
127 // 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
129 MachineInstr *Old = I;
130 unsigned Amount = Old->getOperand(0).getImmedValue();
132 // We need to keep the stack aligned properly. To do this, we round the
133 // amount of space needed for the outgoing arguments up to the next
134 // alignment boundary.
135 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
136 Amount = (Amount+Align-1)/Align*Align;
139 if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
140 New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
143 assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
144 New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
148 // Replace the pseudo instruction with a new instruction...
156 void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II)const{
158 MachineInstr &MI = *II;
159 MachineBasicBlock &MBB = *MI.getParent();
160 MachineFunction &MF = *MBB.getParent();
164 while (!MI.getOperand(i).isFrameIndex()) {
166 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
169 int FrameIndex = MI.getOperand(i).getFrameIndex();
171 // choose a base register: ( hasFP? framepointer : stack pointer )
172 unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
173 // Add the base register
174 MI.getOperand(i).ChangeToRegister(BaseRegister, false);
176 // Now add the frame object offset to the offset from r1.
177 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
179 // If we're not using a Frame Pointer that has been set to the value of the
180 // SP before having the stack size subtracted from it, then add the stack size
181 // to Offset to get the correct offset.
182 Offset += MF.getFrameInfo()->getStackSize();
184 // XXX: we use 'r22' as another hack+slash temporary register here :(
185 if (Offset <= 8191 && Offset >= -8192) { // smallish offset
187 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
189 MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
190 .addReg(BaseRegister).addImm(Offset);
194 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
196 nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset);
198 nMI=BuildMI(IA64::ADD, 2, IA64::r22).addReg(BaseRegister)
205 void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
206 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
207 MachineBasicBlock::iterator MBBI = MBB.begin();
208 MachineFrameInfo *MFI = MF.getFrameInfo();
212 // first, we handle the 'alloc' instruction, that should be right up the
213 // top of any function
214 static const unsigned RegsInOrder[96] = { // there are 96 GPRs the
216 IA64::r32, IA64::r33, IA64::r34, IA64::r35,
217 IA64::r36, IA64::r37, IA64::r38, IA64::r39, IA64::r40, IA64::r41,
218 IA64::r42, IA64::r43, IA64::r44, IA64::r45, IA64::r46, IA64::r47,
219 IA64::r48, IA64::r49, IA64::r50, IA64::r51, IA64::r52, IA64::r53,
220 IA64::r54, IA64::r55, IA64::r56, IA64::r57, IA64::r58, IA64::r59,
221 IA64::r60, IA64::r61, IA64::r62, IA64::r63, IA64::r64, IA64::r65,
222 IA64::r66, IA64::r67, IA64::r68, IA64::r69, IA64::r70, IA64::r71,
223 IA64::r72, IA64::r73, IA64::r74, IA64::r75, IA64::r76, IA64::r77,
224 IA64::r78, IA64::r79, IA64::r80, IA64::r81, IA64::r82, IA64::r83,
225 IA64::r84, IA64::r85, IA64::r86, IA64::r87, IA64::r88, IA64::r89,
226 IA64::r90, IA64::r91, IA64::r92, IA64::r93, IA64::r94, IA64::r95,
227 IA64::r96, IA64::r97, IA64::r98, IA64::r99, IA64::r100, IA64::r101,
228 IA64::r102, IA64::r103, IA64::r104, IA64::r105, IA64::r106, IA64::r107,
229 IA64::r108, IA64::r109, IA64::r110, IA64::r111, IA64::r112, IA64::r113,
230 IA64::r114, IA64::r115, IA64::r116, IA64::r117, IA64::r118, IA64::r119,
231 IA64::r120, IA64::r121, IA64::r122, IA64::r123, IA64::r124, IA64::r125,
232 IA64::r126, IA64::r127 };
234 unsigned numStackedGPRsUsed=0;
235 for(int i=0; i<96; i++) {
236 if(MF.isPhysRegUsed(RegsInOrder[i]))
237 numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int)
240 unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
242 // XXX FIXME : this code should be a bit more reliable (in case there _isn't_
243 // a pseudo_alloc in the MBB)
244 unsigned dstRegOfPseudoAlloc;
245 for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
246 assert(MBBI != MBB.end());
247 if(MBBI->getOpcode() == IA64::PSEUDO_ALLOC) {
248 dstRegOfPseudoAlloc=MBBI->getOperand(0).getReg();
253 MI=BuildMI(IA64::ALLOC,5).addReg(dstRegOfPseudoAlloc).addImm(0).\
254 addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
255 MBB.insert(MBBI, MI);
257 // Get the number of bytes to allocate from the FrameInfo
258 unsigned NumBytes = MFI->getStackSize();
260 if (MFI->hasCalls() && !FP) {
261 // We reserve argument space for call sites in the function immediately on
262 // entry to the current function. This eliminates the need for add/sub
263 // brackets around call sites.
264 NumBytes += MFI->getMaxCallFrameSize();
268 NumBytes += 8; // reserve space for the old FP
270 // Do we need to allocate space on the stack?
274 // Add 16 bytes at the bottom of the stack (scratch area)
275 // and round the size to a multiple of the alignment.
276 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
277 unsigned Size = 16 + (FP ? 8 : 0);
278 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
280 // Update frame info to pretend that this is part of the stack...
281 MFI->setStackSize(NumBytes);
283 // adjust stack pointer: r12 -= numbytes
284 if (NumBytes <= 8191) {
285 MI=BuildMI(IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
286 MBB.insert(MBBI, MI);
287 } else { // we use r22 as a scratch register here
288 MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes);
289 // FIXME: MOVLSI32 expects a _u_32imm
290 MBB.insert(MBBI, MI); // first load the decrement into r22
291 MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
292 MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr)
295 // now if we need to, save the old FP and set the new
297 MI = BuildMI(IA64::ST8, 2).addReg(IA64::r12).addReg(IA64::r5);
298 MBB.insert(MBBI, MI);
299 // this must be the last instr in the prolog ? (XXX: why??)
300 MI = BuildMI(IA64::MOV, 1, IA64::r5).addReg(IA64::r12);
301 MBB.insert(MBBI, MI);
306 void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
307 MachineBasicBlock &MBB) const {
308 const MachineFrameInfo *MFI = MF.getFrameInfo();
309 MachineBasicBlock::iterator MBBI = prior(MBB.end());
311 assert(MBBI->getOpcode() == IA64::RET &&
312 "Can only insert epilog into returning blocks");
316 // Get the number of bytes allocated from the FrameInfo...
317 unsigned NumBytes = MFI->getStackSize();
319 //now if we need to, restore the old FP
322 //copy the FP into the SP (discards allocas)
323 MI=BuildMI(IA64::MOV, 1, IA64::r12).addReg(IA64::r5);
324 MBB.insert(MBBI, MI);
326 MI=BuildMI(IA64::LD8, 1, IA64::r5).addReg(IA64::r5);
327 MBB.insert(MBBI, MI);
332 if (NumBytes <= 8191) {
333 MI=BuildMI(IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).addImm(NumBytes);
334 MBB.insert(MBBI, MI);
336 MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes);
337 MBB.insert(MBBI, MI);
338 MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
339 MBB.insert(MBBI, MI);
345 unsigned IA64RegisterInfo::getRARegister() const {
346 assert(0 && "What is the return address register");
350 unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const {
351 return hasFP(MF) ? IA64::r5 : IA64::r12;
354 #include "IA64GenRegisterInfo.inc"