1 //===-- MBlazeISelLowering.cpp - MBlaze DAG Lowering Implementation -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that MBlaze uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mblaze-lower"
16 #include "MBlazeISelLowering.h"
17 #include "MBlazeMachineFunction.h"
18 #include "MBlazeTargetMachine.h"
19 #include "MBlazeTargetObjectFile.h"
20 #include "MBlazeSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
38 const char *MBlazeTargetLowering::getTargetNodeName(unsigned Opcode) const {
40 case MBlazeISD::JmpLink : return "MBlazeISD::JmpLink";
41 case MBlazeISD::GPRel : return "MBlazeISD::GPRel";
42 case MBlazeISD::Wrap : return "MBlazeISD::Wrap";
43 case MBlazeISD::ICmp : return "MBlazeISD::ICmp";
44 case MBlazeISD::Ret : return "MBlazeISD::Ret";
45 case MBlazeISD::Select_CC : return "MBlazeISD::Select_CC";
46 default : return NULL;
50 MBlazeTargetLowering::MBlazeTargetLowering(MBlazeTargetMachine &TM)
51 : TargetLowering(TM, new MBlazeTargetObjectFile()) {
52 Subtarget = &TM.getSubtarget<MBlazeSubtarget>();
54 // MBlaze does not have i1 type, so use i32 for
55 // setcc operations results (slt, sgt, ...).
56 setBooleanContents(ZeroOrOneBooleanContent);
58 // Set up the register classes
59 addRegisterClass(MVT::i32, MBlaze::CPURegsRegisterClass);
60 if (Subtarget->hasFPU()) {
61 addRegisterClass(MVT::f32, MBlaze::FGR32RegisterClass);
62 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
65 // Floating point operations which are not supported
66 setOperationAction(ISD::FREM, MVT::f32, Expand);
67 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Expand);
68 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand);
69 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
70 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
71 setOperationAction(ISD::FP_ROUND, MVT::f32, Expand);
72 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
73 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
74 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
75 setOperationAction(ISD::FSIN, MVT::f32, Expand);
76 setOperationAction(ISD::FCOS, MVT::f32, Expand);
77 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
78 setOperationAction(ISD::FPOW, MVT::f32, Expand);
79 setOperationAction(ISD::FLOG, MVT::f32, Expand);
80 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
81 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
82 setOperationAction(ISD::FEXP, MVT::f32, Expand);
84 // Load extented operations for i1 types must be promoted
85 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
86 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
89 // MBlaze has no REM or DIVREM operations.
90 setOperationAction(ISD::UREM, MVT::i32, Expand);
91 setOperationAction(ISD::SREM, MVT::i32, Expand);
92 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
93 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
95 // If the processor doesn't support multiply then expand it
96 if (!Subtarget->hasMul()) {
97 setOperationAction(ISD::MUL, MVT::i32, Expand);
100 // If the processor doesn't support 64-bit multiply then expand
101 if (!Subtarget->hasMul() || !Subtarget->hasMul64()) {
102 setOperationAction(ISD::MULHS, MVT::i32, Expand);
103 setOperationAction(ISD::MULHS, MVT::i64, Expand);
104 setOperationAction(ISD::MULHU, MVT::i32, Expand);
105 setOperationAction(ISD::MULHU, MVT::i64, Expand);
108 // If the processor doesn't support division then expand
109 if (!Subtarget->hasDiv()) {
110 setOperationAction(ISD::UDIV, MVT::i32, Expand);
111 setOperationAction(ISD::SDIV, MVT::i32, Expand);
114 // Expand unsupported conversions
115 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
116 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
119 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
121 // MBlaze doesn't have MUL_LOHI
122 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
123 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
124 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
125 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
127 // Used by legalize types to correctly generate the setcc result.
128 // Without this, every float setcc comes with a AND/OR with the result,
129 // we don't want this, since the fpcmp result goes to a flag register,
130 // which is used implicitly by brcond and select operations.
131 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
132 AddPromotedToType(ISD::SELECT, MVT::i1, MVT::i32);
133 AddPromotedToType(ISD::SELECT_CC, MVT::i1, MVT::i32);
135 // MBlaze Custom Operations
136 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
137 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
138 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
139 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
141 // Variable Argument support
142 setOperationAction(ISD::VASTART, MVT::Other, Custom);
143 setOperationAction(ISD::VAEND, MVT::Other, Expand);
144 setOperationAction(ISD::VAARG, MVT::Other, Expand);
145 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
148 // Operations not directly supported by MBlaze.
149 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
150 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
151 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
152 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
153 setOperationAction(ISD::ROTL, MVT::i32, Expand);
154 setOperationAction(ISD::ROTR, MVT::i32, Expand);
155 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
156 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
157 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
158 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
159 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
160 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
161 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
163 // We don't have line number support yet.
164 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
166 // Use the default for now
167 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
168 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
169 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
171 // MBlaze doesn't have extending float->double load/store
172 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
173 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
175 setStackPointerRegisterToSaveRestore(MBlaze::R1);
176 computeRegisterProperties();
179 MVT::SimpleValueType MBlazeTargetLowering::getSetCCResultType(EVT VT) const {
183 /// getFunctionAlignment - Return the Log2 alignment of this function.
184 unsigned MBlazeTargetLowering::getFunctionAlignment(const Function *) const {
188 SDValue MBlazeTargetLowering::LowerOperation(SDValue Op,
189 SelectionDAG &DAG) const {
190 switch (Op.getOpcode())
192 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
193 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
194 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
195 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
196 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
197 case ISD::VASTART: return LowerVASTART(Op, DAG);
202 //===----------------------------------------------------------------------===//
203 // Lower helper functions
204 //===----------------------------------------------------------------------===//
206 MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
207 MachineBasicBlock *BB) const {
208 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
209 DebugLoc dl = MI->getDebugLoc();
211 switch (MI->getOpcode()) {
212 default: assert(false && "Unexpected instr type to insert");
213 case MBlaze::ShiftRL:
214 case MBlaze::ShiftRA:
215 case MBlaze::ShiftL: {
216 // To "insert" a shift left instruction, we actually have to insert a
217 // simple loop. The incoming instruction knows the destination vreg to
218 // set, the source vreg to operate over and the shift amount.
219 const BasicBlock *LLVM_BB = BB->getBasicBlock();
220 MachineFunction::iterator It = BB;
224 // andi samt, samt, 31
225 // beqid samt, finish
228 // addik samt, samt, -1
233 MachineFunction *F = BB->getParent();
234 MachineRegisterInfo &R = F->getRegInfo();
235 MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB);
236 MachineBasicBlock *finish = F->CreateMachineBasicBlock(LLVM_BB);
238 F->insert(It, finish);
240 // Update machine-CFG edges by transfering adding all successors and
241 // remaining instructions from the current block to the new block which
242 // will contain the Phi node for the select.
243 finish->splice(finish->begin(), BB,
244 llvm::next(MachineBasicBlock::iterator(MI)),
246 finish->transferSuccessorsAndUpdatePHIs(BB);
248 // Add the true and fallthrough blocks as its successors.
249 BB->addSuccessor(loop);
250 BB->addSuccessor(finish);
252 // Next, add the finish block as a successor of the loop block
253 loop->addSuccessor(finish);
254 loop->addSuccessor(loop);
256 unsigned IAMT = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
257 BuildMI(BB, dl, TII->get(MBlaze::ANDI), IAMT)
258 .addReg(MI->getOperand(2).getReg())
261 unsigned IVAL = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
262 BuildMI(BB, dl, TII->get(MBlaze::ADDI), IVAL)
263 .addReg(MI->getOperand(1).getReg())
266 BuildMI(BB, dl, TII->get(MBlaze::BEQID))
270 unsigned DST = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
271 unsigned NDST = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
272 BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
273 .addReg(IVAL).addMBB(BB)
274 .addReg(NDST).addMBB(loop);
276 unsigned SAMT = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
277 unsigned NAMT = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
278 BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT)
279 .addReg(IAMT).addMBB(BB)
280 .addReg(NAMT).addMBB(loop);
282 if (MI->getOpcode() == MBlaze::ShiftL)
283 BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST);
284 else if (MI->getOpcode() == MBlaze::ShiftRA)
285 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
286 else if (MI->getOpcode() == MBlaze::ShiftRL)
287 BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST);
289 llvm_unreachable( "Cannot lower unknown shift instruction" );
291 BuildMI(loop, dl, TII->get(MBlaze::ADDI), NAMT)
295 BuildMI(loop, dl, TII->get(MBlaze::BNEID))
299 BuildMI(*finish, finish->begin(), dl,
300 TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
301 .addReg(IVAL).addMBB(BB)
302 .addReg(NDST).addMBB(loop);
304 // The pseudo instruction is no longer needed so remove it
305 MI->eraseFromParent();
309 case MBlaze::Select_FCC:
310 case MBlaze::Select_CC: {
311 // To "insert" a SELECT_CC instruction, we actually have to insert the
312 // diamond control-flow pattern. The incoming instruction knows the
313 // destination vreg to set, the condition code register to branch on, the
314 // true/false values to select between, and a branch opcode to use.
315 const BasicBlock *LLVM_BB = BB->getBasicBlock();
316 MachineFunction::iterator It = BB;
323 // bNE r1, r0, copy1MBB
324 // fallthrough --> copy0MBB
325 MachineFunction *F = BB->getParent();
326 MachineBasicBlock *flsBB = F->CreateMachineBasicBlock(LLVM_BB);
327 MachineBasicBlock *dneBB = F->CreateMachineBasicBlock(LLVM_BB);
330 switch (MI->getOperand(4).getImm()) {
331 default: llvm_unreachable( "Unknown branch condition" );
332 case MBlazeCC::EQ: Opc = MBlaze::BNEID; break;
333 case MBlazeCC::NE: Opc = MBlaze::BEQID; break;
334 case MBlazeCC::GT: Opc = MBlaze::BLEID; break;
335 case MBlazeCC::LT: Opc = MBlaze::BGEID; break;
336 case MBlazeCC::GE: Opc = MBlaze::BLTID; break;
337 case MBlazeCC::LE: Opc = MBlaze::BGTID; break;
340 F->insert(It, flsBB);
341 F->insert(It, dneBB);
343 // Transfer the remainder of BB and its successor edges to dneBB.
344 dneBB->splice(dneBB->begin(), BB,
345 llvm::next(MachineBasicBlock::iterator(MI)),
347 dneBB->transferSuccessorsAndUpdatePHIs(BB);
349 BB->addSuccessor(flsBB);
350 BB->addSuccessor(dneBB);
351 flsBB->addSuccessor(dneBB);
353 BuildMI(BB, dl, TII->get(Opc))
354 .addReg(MI->getOperand(3).getReg())
358 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
360 //BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
361 // .addReg(MI->getOperand(1).getReg()).addMBB(flsBB)
362 // .addReg(MI->getOperand(2).getReg()).addMBB(BB);
364 BuildMI(*dneBB, dneBB->begin(), dl,
365 TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
366 .addReg(MI->getOperand(2).getReg()).addMBB(flsBB)
367 .addReg(MI->getOperand(1).getReg()).addMBB(BB);
369 MI->eraseFromParent(); // The pseudo instruction is gone now.
375 //===----------------------------------------------------------------------===//
376 // Misc Lower Operation implementation
377 //===----------------------------------------------------------------------===//
380 SDValue MBlazeTargetLowering::LowerSELECT_CC(SDValue Op,
381 SelectionDAG &DAG) const {
382 SDValue LHS = Op.getOperand(0);
383 SDValue RHS = Op.getOperand(1);
384 SDValue TrueVal = Op.getOperand(2);
385 SDValue FalseVal = Op.getOperand(3);
386 DebugLoc dl = Op.getDebugLoc();
390 if (LHS.getValueType() == MVT::i32) {
391 Opc = MBlazeISD::Select_CC;
392 CompareFlag = DAG.getNode(MBlazeISD::ICmp, dl, MVT::i32, LHS, RHS)
395 llvm_unreachable( "Cannot lower select_cc with unknown type" );
398 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
402 SDValue MBlazeTargetLowering::
403 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
404 // FIXME there isn't actually debug info here
405 DebugLoc dl = Op.getDebugLoc();
406 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
407 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
409 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, GA);
412 SDValue MBlazeTargetLowering::
413 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
414 llvm_unreachable("TLS not implemented for MicroBlaze.");
415 return SDValue(); // Not reached
418 SDValue MBlazeTargetLowering::
419 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
422 // FIXME there isn't actually debug info here
423 DebugLoc dl = Op.getDebugLoc();
424 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
425 unsigned char OpFlag = IsPIC ? MBlazeII::MO_GOT : MBlazeII::MO_ABS_HILO;
427 EVT PtrVT = Op.getValueType();
428 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
430 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
431 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, JTI);
435 SDValue MBlazeTargetLowering::
436 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
438 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
439 const Constant *C = N->getConstVal();
440 DebugLoc dl = Op.getDebugLoc();
442 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
443 N->getOffset(), MBlazeII::MO_ABS_HILO);
444 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, CP);
447 SDValue MBlazeTargetLowering::LowerVASTART(SDValue Op,
448 SelectionDAG &DAG) const {
449 MachineFunction &MF = DAG.getMachineFunction();
450 MBlazeFunctionInfo *FuncInfo = MF.getInfo<MBlazeFunctionInfo>();
452 DebugLoc dl = Op.getDebugLoc();
453 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
456 // vastart just stores the address of the VarArgsFrameIndex slot into the
457 // memory location argument.
458 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
459 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), SV, 0,
463 //===----------------------------------------------------------------------===//
464 // Calling Convention Implementation
465 //===----------------------------------------------------------------------===//
467 #include "MBlazeGenCallingConv.inc"
469 static bool CC_MBlaze2(unsigned ValNo, EVT ValVT,
470 EVT LocVT, CCValAssign::LocInfo LocInfo,
471 ISD::ArgFlagsTy ArgFlags, CCState &State) {
472 static const unsigned RegsSize=6;
473 static const unsigned IntRegs[] = {
474 MBlaze::R5, MBlaze::R6, MBlaze::R7,
475 MBlaze::R8, MBlaze::R9, MBlaze::R10
478 static const unsigned FltRegs[] = {
479 MBlaze::F5, MBlaze::F6, MBlaze::F7,
480 MBlaze::F8, MBlaze::F9, MBlaze::F10
485 // Promote i8 and i16
486 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
488 if (ArgFlags.isSExt())
489 LocInfo = CCValAssign::SExt;
490 else if (ArgFlags.isZExt())
491 LocInfo = CCValAssign::ZExt;
493 LocInfo = CCValAssign::AExt;
496 if (ValVT == MVT::i32) {
497 Reg = State.AllocateReg(IntRegs, RegsSize);
499 } else if (ValVT == MVT::f32) {
500 Reg = State.AllocateReg(FltRegs, RegsSize);
505 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
506 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
507 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
509 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
510 State.AllocateStack(SizeInBytes, SizeInBytes);
511 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
514 return false; // CC must always match
517 //===----------------------------------------------------------------------===//
518 // Call Calling Convention Implementation
519 //===----------------------------------------------------------------------===//
521 /// LowerCall - functions arguments are copied from virtual regs to
522 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
523 /// TODO: isVarArg, isTailCall.
524 SDValue MBlazeTargetLowering::
525 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
526 bool isVarArg, bool &isTailCall,
527 const SmallVectorImpl<ISD::OutputArg> &Outs,
528 const SmallVectorImpl<SDValue> &OutVals,
529 const SmallVectorImpl<ISD::InputArg> &Ins,
530 DebugLoc dl, SelectionDAG &DAG,
531 SmallVectorImpl<SDValue> &InVals) const {
532 // MBlaze does not yet support tail call optimization
535 MachineFunction &MF = DAG.getMachineFunction();
536 MachineFrameInfo *MFI = MF.getFrameInfo();
538 // Analyze operands of the call, assigning locations to each operand.
539 SmallVector<CCValAssign, 16> ArgLocs;
540 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
542 CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze2);
544 // Get a count of how many bytes are to be pushed on the stack.
545 unsigned NumBytes = CCInfo.getNextStackOffset();
546 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
548 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
549 SmallVector<SDValue, 8> MemOpChains;
551 // First/LastArgStackLoc contains the first/last
552 // "at stack" argument location.
553 int LastArgStackLoc = 0;
554 unsigned FirstStackArgLoc = 0;
556 // Walk the register/memloc assignments, inserting copies/loads.
557 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
558 CCValAssign &VA = ArgLocs[i];
559 EVT RegVT = VA.getLocVT();
560 SDValue Arg = OutVals[i];
562 // Promote the value if needed.
563 switch (VA.getLocInfo()) {
564 default: llvm_unreachable("Unknown loc info!");
565 case CCValAssign::Full: break;
566 case CCValAssign::SExt:
567 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
569 case CCValAssign::ZExt:
570 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
572 case CCValAssign::AExt:
573 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
577 // Arguments that can be passed on register must be kept at
580 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
582 // Register can't get to this point...
583 assert(VA.isMemLoc());
585 // Create the frame index object for this incoming parameter
586 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
587 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
588 LastArgStackLoc, true);
590 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
592 // emit ISD::STORE whichs stores the
593 // parameter value to a stack Location
594 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
599 // Transform all store nodes into one single node because all store
600 // nodes are independent of each other.
601 if (!MemOpChains.empty())
602 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
603 &MemOpChains[0], MemOpChains.size());
605 // Build a sequence of copy-to-reg nodes chained together with token
606 // chain and flag operands which copy the outgoing args into registers.
607 // The InFlag in necessary since all emited instructions must be
610 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
611 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
612 RegsToPass[i].second, InFlag);
613 InFlag = Chain.getValue(1);
616 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
617 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
618 // node so that legalize doesn't hack it.
619 unsigned char OpFlag = MBlazeII::MO_NO_FLAG;
620 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
621 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
622 getPointerTy(), 0, OpFlag);
623 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
624 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
625 getPointerTy(), OpFlag);
627 // MBlazeJmpLink = #chain, #target_address, #opt_in_flags...
628 // = Chain, Callee, Reg#1, Reg#2, ...
630 // Returns a chain & a flag for retval copy to use.
631 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
632 SmallVector<SDValue, 8> Ops;
633 Ops.push_back(Chain);
634 Ops.push_back(Callee);
636 // Add argument registers to the end of the list so that they are
637 // known live into the call.
638 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
639 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
640 RegsToPass[i].second.getValueType()));
643 if (InFlag.getNode())
644 Ops.push_back(InFlag);
646 Chain = DAG.getNode(MBlazeISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
647 InFlag = Chain.getValue(1);
649 // Create the CALLSEQ_END node.
650 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
651 DAG.getIntPtrConstant(0, true), InFlag);
653 InFlag = Chain.getValue(1);
655 // Handle result values, copying them out of physregs into vregs that we
657 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
658 Ins, dl, DAG, InVals);
661 /// LowerCallResult - Lower the result values of a call into the
662 /// appropriate copies out of appropriate physical registers.
663 SDValue MBlazeTargetLowering::
664 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv,
665 bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins,
666 DebugLoc dl, SelectionDAG &DAG,
667 SmallVectorImpl<SDValue> &InVals) const {
668 // Assign locations to each value returned by this call.
669 SmallVector<CCValAssign, 16> RVLocs;
670 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
671 RVLocs, *DAG.getContext());
673 CCInfo.AnalyzeCallResult(Ins, RetCC_MBlaze);
675 // Copy all of the result registers out of their specified physreg.
676 for (unsigned i = 0; i != RVLocs.size(); ++i) {
677 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
678 RVLocs[i].getValVT(), InFlag).getValue(1);
679 InFlag = Chain.getValue(2);
680 InVals.push_back(Chain.getValue(0));
686 //===----------------------------------------------------------------------===//
687 // Formal Arguments Calling Convention Implementation
688 //===----------------------------------------------------------------------===//
690 /// LowerFormalArguments - transform physical registers into
691 /// virtual registers and generate load operations for
692 /// arguments places on the stack.
693 SDValue MBlazeTargetLowering::
694 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
695 const SmallVectorImpl<ISD::InputArg> &Ins,
696 DebugLoc dl, SelectionDAG &DAG,
697 SmallVectorImpl<SDValue> &InVals) const {
698 MachineFunction &MF = DAG.getMachineFunction();
699 MachineFrameInfo *MFI = MF.getFrameInfo();
700 MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
702 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
703 MBlazeFI->setVarArgsFrameIndex(0);
705 // Used with vargs to acumulate store chains.
706 std::vector<SDValue> OutChains;
708 // Keep track of the last register used for arguments
709 unsigned ArgRegEnd = 0;
711 // Assign locations to all of the incoming arguments.
712 SmallVector<CCValAssign, 16> ArgLocs;
713 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
714 ArgLocs, *DAG.getContext());
716 CCInfo.AnalyzeFormalArguments(Ins, CC_MBlaze2);
719 unsigned FirstStackArgLoc = 0;
721 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
722 CCValAssign &VA = ArgLocs[i];
724 // Arguments stored on registers
726 EVT RegVT = VA.getLocVT();
727 ArgRegEnd = VA.getLocReg();
728 TargetRegisterClass *RC = 0;
730 if (RegVT == MVT::i32)
731 RC = MBlaze::CPURegsRegisterClass;
732 else if (RegVT == MVT::f32)
733 RC = MBlaze::FGR32RegisterClass;
735 llvm_unreachable("RegVT not supported by LowerFormalArguments");
737 // Transform the arguments stored on
738 // physical registers into virtual ones
739 unsigned Reg = MF.addLiveIn(ArgRegEnd, RC);
740 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
742 // If this is an 8 or 16-bit value, it has been passed promoted
743 // to 32 bits. Insert an assert[sz]ext to capture this, then
744 // truncate to the right size. If if is a floating point value
745 // then convert to the correct type.
746 if (VA.getLocInfo() != CCValAssign::Full) {
748 if (VA.getLocInfo() == CCValAssign::SExt)
749 Opcode = ISD::AssertSext;
750 else if (VA.getLocInfo() == CCValAssign::ZExt)
751 Opcode = ISD::AssertZext;
753 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
754 DAG.getValueType(VA.getValVT()));
755 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
758 InVals.push_back(ArgValue);
760 } else { // VA.isRegLoc()
763 assert(VA.isMemLoc());
765 // The last argument is not a register
768 // The stack pointer offset is relative to the caller stack frame.
769 // Since the real stack size is unknown here, a negative SPOffset
770 // is used so there's a way to adjust these offsets when the stack
771 // size get known (on EliminateFrameIndex). A dummy SPOffset is
772 // used instead of a direct negative address (which is recorded to
773 // be used on emitPrologue) to avoid mis-calc of the first stack
774 // offset on PEI::calculateFrameObjectOffsets.
775 // Arguments are always 32-bit.
776 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
777 int FI = MFI->CreateFixedObject(ArgSize, 0, true);
778 MBlazeFI->recordLoadArgsFI(FI, -(ArgSize+
779 (FirstStackArgLoc + VA.getLocMemOffset())));
781 // Create load nodes to retrieve arguments from the stack
782 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
783 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0,
788 // To meet ABI, when VARARGS are passed on registers, the registers
789 // must have their values written to the caller stack frame. If the last
790 // argument was placed in the stack, there's no need to save any register.
791 if ((isVarArg) && ArgRegEnd) {
792 if (StackPtr.getNode() == 0)
793 StackPtr = DAG.getRegister(StackReg, getPointerTy());
795 // The last register argument that must be saved is MBlaze::R10
796 TargetRegisterClass *RC = MBlaze::CPURegsRegisterClass;
798 unsigned Begin = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R5);
799 unsigned Start = MBlazeRegisterInfo::getRegisterNumbering(ArgRegEnd+1);
800 unsigned End = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R10);
801 unsigned StackLoc = ArgLocs.size()-1 + (Start - Begin);
803 for (; Start <= End; ++Start, ++StackLoc) {
804 unsigned Reg = MBlazeRegisterInfo::getRegisterFromNumbering(Start);
805 unsigned LiveReg = MF.addLiveIn(Reg, RC);
806 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, LiveReg, MVT::i32);
808 int FI = MFI->CreateFixedObject(4, 0, true);
809 MBlazeFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
810 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
811 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0,
814 // Record the frame index of the first variable argument
815 // which is a value necessary to VASTART.
816 if (!MBlazeFI->getVarArgsFrameIndex())
817 MBlazeFI->setVarArgsFrameIndex(FI);
821 // All stores are grouped in one node to allow the matching between
822 // the size of Ins and InVals. This only happens when on varg functions
823 if (!OutChains.empty()) {
824 OutChains.push_back(Chain);
825 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
826 &OutChains[0], OutChains.size());
832 //===----------------------------------------------------------------------===//
833 // Return Value Calling Convention Implementation
834 //===----------------------------------------------------------------------===//
836 SDValue MBlazeTargetLowering::
837 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
838 const SmallVectorImpl<ISD::OutputArg> &Outs,
839 const SmallVectorImpl<SDValue> &OutVals,
840 DebugLoc dl, SelectionDAG &DAG) const {
841 // CCValAssign - represent the assignment of
842 // the return value to a location
843 SmallVector<CCValAssign, 16> RVLocs;
845 // CCState - Info about the registers and stack slot.
846 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
847 RVLocs, *DAG.getContext());
849 // Analize return values.
850 CCInfo.AnalyzeReturn(Outs, RetCC_MBlaze);
852 // If this is the first return lowered for this function, add
853 // the regs to the liveout set for the function.
854 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
855 for (unsigned i = 0; i != RVLocs.size(); ++i)
856 if (RVLocs[i].isRegLoc())
857 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
862 // Copy the result values into the output registers.
863 for (unsigned i = 0; i != RVLocs.size(); ++i) {
864 CCValAssign &VA = RVLocs[i];
865 assert(VA.isRegLoc() && "Can only return in registers!");
867 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
870 // guarantee that all emitted copies are
871 // stuck together, avoiding something bad
872 Flag = Chain.getValue(1);
875 // Return on MBlaze is always a "rtsd R15, 8"
877 return DAG.getNode(MBlazeISD::Ret, dl, MVT::Other,
878 Chain, DAG.getRegister(MBlaze::R15, MVT::i32), Flag);
880 return DAG.getNode(MBlazeISD::Ret, dl, MVT::Other,
881 Chain, DAG.getRegister(MBlaze::R15, MVT::i32));
884 //===----------------------------------------------------------------------===//
885 // MBlaze Inline Assembly Support
886 //===----------------------------------------------------------------------===//
888 /// getConstraintType - Given a constraint letter, return the type of
889 /// constraint it is for this target.
890 MBlazeTargetLowering::ConstraintType MBlazeTargetLowering::
891 getConstraintType(const std::string &Constraint) const
893 // MBlaze specific constrainy
895 // 'd' : An address register. Equivalent to r.
896 // 'y' : Equivalent to r; retained for
897 // backwards compatibility.
898 // 'f' : Floating Point registers.
899 if (Constraint.size() == 1) {
900 switch (Constraint[0]) {
905 return C_RegisterClass;
909 return TargetLowering::getConstraintType(Constraint);
912 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
913 /// return a list of registers that can be used to satisfy the constraint.
914 /// This should only be used for C_RegisterClass constraints.
915 std::pair<unsigned, const TargetRegisterClass*> MBlazeTargetLowering::
916 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
917 if (Constraint.size() == 1) {
918 switch (Constraint[0]) {
920 return std::make_pair(0U, MBlaze::CPURegsRegisterClass);
923 return std::make_pair(0U, MBlaze::FGR32RegisterClass);
926 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
929 /// Given a register class constraint, like 'r', if this corresponds directly
930 /// to an LLVM register class, return a register of 0 and the register class
932 std::vector<unsigned> MBlazeTargetLowering::
933 getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
934 if (Constraint.size() != 1)
935 return std::vector<unsigned>();
937 switch (Constraint[0]) {
940 // GCC MBlaze Constraint Letters
943 return make_vector<unsigned>(
944 MBlaze::R3, MBlaze::R4, MBlaze::R5, MBlaze::R6,
945 MBlaze::R7, MBlaze::R9, MBlaze::R10, MBlaze::R11,
946 MBlaze::R12, MBlaze::R19, MBlaze::R20, MBlaze::R21,
947 MBlaze::R22, MBlaze::R23, MBlaze::R24, MBlaze::R25,
948 MBlaze::R26, MBlaze::R27, MBlaze::R28, MBlaze::R29,
949 MBlaze::R30, MBlaze::R31, 0);
952 return make_vector<unsigned>(
953 MBlaze::F3, MBlaze::F4, MBlaze::F5, MBlaze::F6,
954 MBlaze::F7, MBlaze::F9, MBlaze::F10, MBlaze::F11,
955 MBlaze::F12, MBlaze::F19, MBlaze::F20, MBlaze::F21,
956 MBlaze::F22, MBlaze::F23, MBlaze::F24, MBlaze::F25,
957 MBlaze::F26, MBlaze::F27, MBlaze::F28, MBlaze::F29,
958 MBlaze::F30, MBlaze::F31, 0);
960 return std::vector<unsigned>();
963 bool MBlazeTargetLowering::
964 isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
965 // The MBlaze target isn't yet aware of offsets.
969 bool MBlazeTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
970 return VT != MVT::f32;