1 //===- MBlazeInstrFPU.td - MBlaze FPU Instruction defs ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // MBlaze profiles and nodes
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MBlaze Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 // Memory Access Instructions
20 //===----------------------------------------------------------------------===//
21 class LoadFM<bits<6> op, string instr_asm, PatFrag OpNode> :
22 TA<op, 0x000, (outs FGR32:$dst), (ins memrr:$addr),
23 !strconcat(instr_asm, " $dst, $addr"),
24 [(set FGR32:$dst, (OpNode xaddr:$addr))], IILoad>;
26 class LoadFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
27 TAI<op, (outs FGR32:$dst), (ins memri:$addr),
28 !strconcat(instr_asm, " $dst, $addr"),
29 [(set FGR32:$dst, (OpNode iaddr:$addr))], IILoad>;
31 class StoreFM<bits<6> op, string instr_asm, PatFrag OpNode> :
32 TA<op, 0x000, (outs), (ins FGR32:$dst, memrr:$addr),
33 !strconcat(instr_asm, " $dst, $addr"),
34 [(OpNode FGR32:$dst, xaddr:$addr)], IIStore>;
36 class StoreFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
37 TAI<op, (outs), (ins FGR32:$dst, memrr:$addr),
38 !strconcat(instr_asm, " $dst, $addr"),
39 [(OpNode FGR32:$dst, iaddr:$addr)], IIStore>;
41 class ArithF<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
42 InstrItinClass itin> :
43 TA<op, flags, (outs FGR32:$dst), (ins FGR32:$b, FGR32:$c),
44 !strconcat(instr_asm, " $dst, $b, $c"),
45 [(set FGR32:$dst, (OpNode FGR32:$b, FGR32:$c))], itin>;
47 class CmpFN<bits<6> op, bits<11> flags, string instr_asm,
48 InstrItinClass itin> :
49 TA<op, flags, (outs CPURegs:$dst), (ins FGR32:$b, FGR32:$c),
50 !strconcat(instr_asm, " $dst, $b, $c"),
53 class ArithFR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
54 InstrItinClass itin> :
55 TA<op, flags, (outs FGR32:$dst), (ins FGR32:$b, FGR32:$c),
56 !strconcat(instr_asm, " $dst, $c, $b"),
57 [(set FGR32:$dst, (OpNode FGR32:$b, FGR32:$c))], itin>;
59 class ArithF2<bits<6> op, bits<11> flags, string instr_asm,
60 InstrItinClass itin> :
61 TF<op, flags, (outs FGR32:$dst), (ins FGR32:$b),
62 !strconcat(instr_asm, " $dst, $b"),
65 class ArithIF<bits<6> op, bits<11> flags, string instr_asm,
66 InstrItinClass itin> :
67 TF<op, flags, (outs FGR32:$dst), (ins CPURegs:$b),
68 !strconcat(instr_asm, " $dst, $b"),
71 class ArithFI<bits<6> op, bits<11> flags, string instr_asm,
72 InstrItinClass itin> :
73 TF<op, flags, (outs CPURegs:$dst), (ins FGR32:$b),
74 !strconcat(instr_asm, " $dst, $b"),
77 class LogicF<bits<6> op, string instr_asm> :
78 TAI<op, (outs FGR32:$dst), (ins FGR32:$b, FGR32:$c),
79 !strconcat(instr_asm, " $dst, $b, $c"),
83 class LogicFI<bits<6> op, string instr_asm> :
84 TAI<op, (outs FGR32:$dst), (ins FGR32:$b, fimm:$c),
85 !strconcat(instr_asm, " $dst, $b, $c"),
89 //===----------------------------------------------------------------------===//
90 // Pseudo instructions
91 //===----------------------------------------------------------------------===//
93 //===----------------------------------------------------------------------===//
94 // FPU Arithmetic Instructions
95 //===----------------------------------------------------------------------===//
96 let Predicates=[HasFPU] in {
97 def FOR : LogicF<0x28, "or ">;
98 def FORI : LogicFI<0x28, "ori ">;
99 def FADD : ArithF<0x16, 0x000, "fadd ", fadd, IIAlu>;
100 def FRSUB : ArithFR<0x16, 0x080, "frsub ", fsub, IIAlu>;
101 def FMUL : ArithF<0x16, 0x100, "fmul ", fmul, IIAlu>;
102 def FDIV : ArithF<0x16, 0x180, "fdiv ", fdiv, IIAlu>;
104 def LWF : LoadFM<0x32, "lw ", load>;
105 def LWFI : LoadFMI<0x32, "lwi ", load>;
107 def SWF : StoreFM<0x32, "sw ", store>;
108 def SWFI : StoreFMI<0x32, "swi ", store>;
111 let Predicates=[HasFPU,HasSqrt] in {
112 def FLT : ArithIF<0x16, 0x280, "flt ", IIAlu>;
113 def FINT : ArithFI<0x16, 0x300, "fint ", IIAlu>;
114 def FSQRT : ArithF2<0x16, 0x300, "fsqrt ", IIAlu>;
117 let isAsCheapAsAMove = 1 in {
118 def FCMP_UN : CmpFN<0x16, 0x200, "fcmp.un", IIAlu>;
119 def FCMP_LT : CmpFN<0x16, 0x210, "fcmp.lt", IIAlu>;
120 def FCMP_EQ : CmpFN<0x16, 0x220, "fcmp.eq", IIAlu>;
121 def FCMP_LE : CmpFN<0x16, 0x230, "fcmp.le", IIAlu>;
122 def FCMP_GT : CmpFN<0x16, 0x240, "fcmp.gt", IIAlu>;
123 def FCMP_NE : CmpFN<0x16, 0x250, "fcmp.ne", IIAlu>;
124 def FCMP_GE : CmpFN<0x16, 0x260, "fcmp.ge", IIAlu>;
128 let usesCustomInserter = 1 in {
129 def Select_FCC : MBlazePseudo<(outs FGR32:$dst),
130 (ins FGR32:$T, FGR32:$F, CPURegs:$CMP, i32imm:$CC),
131 "; SELECT_FCC PSEUDO!",
135 // Floating point conversions
136 let Predicates=[HasFPU] in {
137 def : Pat<(sint_to_fp CPURegs:$V), (FLT CPURegs:$V)>;
138 def : Pat<(fp_to_sint FGR32:$V), (FINT FGR32:$V)>;
139 def : Pat<(fsqrt FGR32:$V), (FSQRT FGR32:$V)>;
143 let Predicates=[HasFPU] in {
144 def : Pat<(setcc FGR32:$L, FGR32:$R, SETEQ),
145 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
146 (FCMP_EQ FGR32:$L, FGR32:$R), 2)>;
147 def : Pat<(setcc FGR32:$L, FGR32:$R, SETNE),
148 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
149 (FCMP_EQ FGR32:$L, FGR32:$R), 1)>;
150 def : Pat<(setcc FGR32:$L, FGR32:$R, SETOEQ),
151 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
152 (FCMP_EQ FGR32:$L, FGR32:$R), 2)>;
153 def : Pat<(setcc FGR32:$L, FGR32:$R, SETONE),
154 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
155 (XOR (FCMP_UN FGR32:$L, FGR32:$R),
156 (FCMP_EQ FGR32:$L, FGR32:$R)), 2)>;
157 def : Pat<(setcc FGR32:$L, FGR32:$R, SETONE),
158 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
159 (OR (FCMP_UN FGR32:$L, FGR32:$R),
160 (FCMP_EQ FGR32:$L, FGR32:$R)), 2)>;
161 def : Pat<(setcc FGR32:$L, FGR32:$R, SETGT),
162 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
163 (FCMP_GT FGR32:$L, FGR32:$R), 2)>;
164 def : Pat<(setcc FGR32:$L, FGR32:$R, SETLT),
165 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
166 (FCMP_LT FGR32:$L, FGR32:$R), 2)>;
167 def : Pat<(setcc FGR32:$L, FGR32:$R, SETGE),
168 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
169 (FCMP_GE FGR32:$L, FGR32:$R), 2)>;
170 def : Pat<(setcc FGR32:$L, FGR32:$R, SETLE),
171 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
172 (FCMP_LE FGR32:$L, FGR32:$R), 2)>;
173 def : Pat<(setcc FGR32:$L, FGR32:$R, SETOGT),
174 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
175 (FCMP_GT FGR32:$L, FGR32:$R), 2)>;
176 def : Pat<(setcc FGR32:$L, FGR32:$R, SETOLT),
177 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
178 (FCMP_LT FGR32:$L, FGR32:$R), 2)>;
179 def : Pat<(setcc FGR32:$L, FGR32:$R, SETOGE),
180 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
181 (FCMP_GE FGR32:$L, FGR32:$R), 2)>;
182 def : Pat<(setcc FGR32:$L, FGR32:$R, SETOLE),
183 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
184 (FCMP_LE FGR32:$L, FGR32:$R), 2)>;
185 def : Pat<(setcc FGR32:$L, FGR32:$R, SETUEQ),
186 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
187 (OR (FCMP_UN FGR32:$L, FGR32:$R),
188 (FCMP_EQ FGR32:$L, FGR32:$R)), 2)>;
189 def : Pat<(setcc FGR32:$L, FGR32:$R, SETUNE),
190 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
191 (FCMP_NE FGR32:$L, FGR32:$R), 2)>;
192 def : Pat<(setcc FGR32:$L, FGR32:$R, SETUGT),
193 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
194 (OR (FCMP_UN FGR32:$L, FGR32:$R),
195 (FCMP_GT FGR32:$L, FGR32:$R)), 2)>;
196 def : Pat<(setcc FGR32:$L, FGR32:$R, SETULT),
197 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
198 (OR (FCMP_UN FGR32:$L, FGR32:$R),
199 (FCMP_LT FGR32:$L, FGR32:$R)), 2)>;
200 def : Pat<(setcc FGR32:$L, FGR32:$R, SETUGE),
201 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
202 (OR (FCMP_UN FGR32:$L, FGR32:$R),
203 (FCMP_GE FGR32:$L, FGR32:$R)), 2)>;
204 def : Pat<(setcc FGR32:$L, FGR32:$R, SETULE),
205 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
206 (OR (FCMP_UN FGR32:$L, FGR32:$R),
207 (FCMP_LE FGR32:$L, FGR32:$R)), 2)>;
208 def : Pat<(setcc FGR32:$L, FGR32:$R, SETO),
209 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
210 (FCMP_UN FGR32:$L, FGR32:$R), 1)>;
211 def : Pat<(setcc FGR32:$L, FGR32:$R, SETUO),
212 (Select_CC (ADDI R0, 1), (ADDI R0, 0),
213 (FCMP_UN FGR32:$L, FGR32:$R), 2)>;
217 def : Pat<(select CPURegs:$C, FGR32:$T, FGR32:$F),
218 (Select_FCC FGR32:$T, FGR32:$F, CPURegs:$C, 2)>;
220 //===----------------------------------------------------------------------===//
221 // Patterns for Floating Point Instructions
222 //===----------------------------------------------------------------------===//
223 def : Pat<(f32 fpimm:$imm), (FORI F0, fpimm:$imm)>;