1 //===- MBlazeInstrFormats.td - MB Instruction defs ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Format specifies the encoding used by the instruction. This is part of the
11 // ad-hoc solution used to emit machine instruction encodings by our machine
13 class Format<bits<6> val> {
17 def FPseudo : Format<0>;
18 def FRRR : Format<1>; // ADD, OR, etc.
19 def FRRI : Format<2>; // ADDI, ORI, etc.
20 def FCRR : Format<3>; // PUTD, WDC, WIC, BEQ, BNE, BGE, etc.
21 def FCRI : Format<4>; // RTID, RTED, RTSD, BEQI, BNEI, BGEI, etc.
22 def FRCR : Format<5>; // BRLD, BRALD, GETD
23 def FRCI : Format<6>; // BRLID, BRALID, MSRCLR, MSRSET
24 def FCCR : Format<7>; // BR, BRA, BRD, etc.
25 def FCCI : Format<8>; // IMM, BRI, BRAI, BRID, etc.
26 def FRRCI : Format<9>; // BSRLI, BSRAI, BSLLI
27 def FRRC : Format<10>; // SEXT8, SEXT16, SRA, SRC, SRL, FLT, FINT, FSQRT
28 def FRCX : Format<11>; // GET
29 def FRCS : Format<12>; // MFS
30 def FCRCS : Format<13>; // MTS
31 def FCRCX : Format<14>; // PUT
32 def FCX : Format<15>; // TPUT
33 def FCR : Format<16>; // TPUTD
34 def FRIR : Format<17>; // RSUBI
35 def FRRRR : Format<18>; // RSUB, FRSUB
36 def FRI : Format<19>; // RSUB, FRSUB
37 def FC : Format<20>; // NOP
38 def FRR : Format<21>; // CLZ
40 //===----------------------------------------------------------------------===//
41 // Describe MBlaze instructions format
43 // CPU INSTRUCTION FORMATS
45 // opcode - operation code.
47 // ra - first src. reg.
48 // rb - second src. reg.
49 // imm16 - 16-bit immediate value.
51 //===----------------------------------------------------------------------===//
53 // Generic MBlaze Format
54 class MBlazeInst<bits<6> op, Format form, dag outs, dag ins, string asmstr,
55 list<dag> pattern, InstrItinClass itin> : Instruction {
56 let Namespace = "MBlaze";
61 bits<6> FormBits = Form.Value;
63 // Top 6 bits are the 'opcode' field
64 let Inst{0-5} = opcode;
66 // If the instruction is marked as a pseudo, set isCodeGenOnly so that the
67 // assembler and disassmbler ignore it.
68 let isCodeGenOnly = !eq(!cast<string>(form), "FPseudo");
70 dag OutOperandList = outs;
71 dag InOperandList = ins;
73 let AsmString = asmstr;
74 let Pattern = pattern;
77 // TSFlags layout should be kept in sync with MBlazeInstrInfo.h.
78 let TSFlags{5-0} = FormBits;
81 //===----------------------------------------------------------------------===//
82 // Pseudo instruction class
83 //===----------------------------------------------------------------------===//
84 class MBlazePseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
85 MBlazeInst<0x0, FPseudo, outs, ins, asmstr, pattern, IIC_Pseudo>;
87 //===----------------------------------------------------------------------===//
88 // Type A instruction class in MBlaze : <|opcode|rd|ra|rb|flags|>
89 //===----------------------------------------------------------------------===//
91 class TA<bits<6> op, bits<11> flags, dag outs, dag ins, string asmstr,
92 list<dag> pattern, InstrItinClass itin> :
93 MBlazeInst<op,FRRR,outs, ins, asmstr, pattern, itin>
100 let Inst{11-15} = ra;
101 let Inst{16-20} = rb;
102 let Inst{21-31} = flags;
105 //===----------------------------------------------------------------------===//
106 // Type B instruction class in MBlaze : <|opcode|rd|ra|immediate|>
107 //===----------------------------------------------------------------------===//
109 class TB<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
110 InstrItinClass itin> :
111 MBlazeInst<op, FRRI, outs, ins, asmstr, pattern, itin>
118 let Inst{11-15} = ra;
119 let Inst{16-31} = imm16;
122 //===----------------------------------------------------------------------===//
123 // Type A instruction class in MBlaze but with the operands reversed
124 // in the LLVM DAG : <|opcode|rd|ra|rb|flags|>
125 //===----------------------------------------------------------------------===//
127 class TAR<bits<6> op, bits<11> flags, dag outs, dag ins, string asmstr,
128 list<dag> pattern, InstrItinClass itin> :
129 TA<op, flags, outs, ins, asmstr, pattern, itin>
142 //===----------------------------------------------------------------------===//
143 // Type B instruction class in MBlaze but with the operands reversed in
144 // the LLVM DAG : <|opcode|rd|ra|immediate|>
145 //===----------------------------------------------------------------------===//
146 class TBR<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
147 InstrItinClass itin> :
148 TB<op, outs, ins, asmstr, pattern, itin> {
160 //===----------------------------------------------------------------------===//
161 // Shift immediate instruction class in MBlaze : <|opcode|rd|ra|immediate|>
162 //===----------------------------------------------------------------------===//
163 class SHT<bits<6> op, bits<2> flags, dag outs, dag ins, string asmstr,
164 list<dag> pattern, InstrItinClass itin> :
165 MBlazeInst<op, FRRI, outs, ins, asmstr, pattern, itin> {
171 let Inst{11-15} = ra;
172 let Inst{16-20} = 0x0;
173 let Inst{21-22} = flags;
174 let Inst{23-26} = 0x0;
175 let Inst{27-31} = imm5;
178 //===----------------------------------------------------------------------===//
179 // Special instruction class in MBlaze : <|opcode|rd|imm14|>
180 //===----------------------------------------------------------------------===//
181 class SPC<bits<6> op, bits<2> flags, dag outs, dag ins, string asmstr,
182 list<dag> pattern, InstrItinClass itin> :
183 MBlazeInst<op, FRI, outs, ins, asmstr, pattern, itin> {
188 let Inst{11-15} = 0x0;
189 let Inst{16-17} = flags;
190 let Inst{18-31} = imm14;
193 //===----------------------------------------------------------------------===//
194 // MSR instruction class in MBlaze : <|opcode|rd|imm15|>
195 //===----------------------------------------------------------------------===//
196 class MSR<bits<6> op, bits<6> flags, dag outs, dag ins, string asmstr,
197 list<dag> pattern, InstrItinClass itin> :
198 MBlazeInst<op, FRI, outs, ins, asmstr, pattern, itin> {
203 let Inst{11-16} = flags;
204 let Inst{17-31} = imm15;
207 //===----------------------------------------------------------------------===//
208 // TCLZ instruction class in MBlaze : <|opcode|rd|imm15|>
209 //===----------------------------------------------------------------------===//
210 class TCLZ<bits<6> op, bits<16> flags, dag outs, dag ins, string asmstr,
211 list<dag> pattern, InstrItinClass itin> :
212 MBlazeInst<op, FRR, outs, ins, asmstr, pattern, itin> {
217 let Inst{11-15} = ra;
218 let Inst{16-31} = flags;
221 //===----------------------------------------------------------------------===//
222 // MBAR instruction class in MBlaze : <|opcode|rd|imm15|>
223 //===----------------------------------------------------------------------===//
224 class MBAR<bits<6> op, bits<26> flags, dag outs, dag ins, string asmstr,
225 list<dag> pattern, InstrItinClass itin> :
226 MBlazeInst<op, FC, outs, ins, asmstr, pattern, itin> {
227 let Inst{6-31} = flags;