1 //===- MBlazeInstrInfo.cpp - MBlaze Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MBlaze implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MBlazeInstrInfo.h"
15 #include "MBlazeTargetMachine.h"
16 #include "MBlazeMachineFunction.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/ErrorHandling.h"
24 #define GET_INSTRINFO_MC_DESC
25 #include "MBlazeGenInstrInfo.inc"
29 MBlazeInstrInfo::MBlazeInstrInfo(MBlazeTargetMachine &tm)
30 : TargetInstrInfoImpl(MBlazeInsts, array_lengthof(MBlazeInsts)),
31 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
33 static bool isZeroImm(const MachineOperand &op) {
34 return op.isImm() && op.getImm() == 0;
37 /// isLoadFromStackSlot - If the specified machine instruction is a direct
38 /// load from a stack slot, return the virtual or physical register number of
39 /// the destination along with the FrameIndex of the loaded stack slot. If
40 /// not, return 0. This predicate must return 0 if the instruction has
41 /// any side effects other than loading from the stack slot.
42 unsigned MBlazeInstrInfo::
43 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const {
44 if (MI->getOpcode() == MBlaze::LWI) {
45 if ((MI->getOperand(1).isFI()) && // is a stack slot
46 (MI->getOperand(2).isImm()) && // the imm is zero
47 (isZeroImm(MI->getOperand(2)))) {
48 FrameIndex = MI->getOperand(1).getIndex();
49 return MI->getOperand(0).getReg();
56 /// isStoreToStackSlot - If the specified machine instruction is a direct
57 /// store to a stack slot, return the virtual or physical register number of
58 /// the source reg along with the FrameIndex of the loaded stack slot. If
59 /// not, return 0. This predicate must return 0 if the instruction has
60 /// any side effects other than storing to the stack slot.
61 unsigned MBlazeInstrInfo::
62 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const {
63 if (MI->getOpcode() == MBlaze::SWI) {
64 if ((MI->getOperand(1).isFI()) && // is a stack slot
65 (MI->getOperand(2).isImm()) && // the imm is zero
66 (isZeroImm(MI->getOperand(2)))) {
67 FrameIndex = MI->getOperand(1).getIndex();
68 return MI->getOperand(0).getReg();
74 /// insertNoop - If data hazard condition is found insert the target nop
76 void MBlazeInstrInfo::
77 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
79 BuildMI(MBB, MI, DL, get(MBlaze::NOP));
82 void MBlazeInstrInfo::
83 copyPhysReg(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator I, DebugLoc DL,
85 unsigned DestReg, unsigned SrcReg,
87 llvm::BuildMI(MBB, I, DL, get(MBlaze::ADDK), DestReg)
88 .addReg(SrcReg, getKillRegState(KillSrc)).addReg(MBlaze::R0);
91 void MBlazeInstrInfo::
92 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
93 unsigned SrcReg, bool isKill, int FI,
94 const TargetRegisterClass *RC,
95 const TargetRegisterInfo *TRI) const {
97 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
98 .addFrameIndex(FI).addImm(0); //.addFrameIndex(FI);
101 void MBlazeInstrInfo::
102 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
103 unsigned DestReg, int FI,
104 const TargetRegisterClass *RC,
105 const TargetRegisterInfo *TRI) const {
107 BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg)
108 .addFrameIndex(FI).addImm(0); //.addFrameIndex(FI);
111 //===----------------------------------------------------------------------===//
113 //===----------------------------------------------------------------------===//
114 bool MBlazeInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
115 MachineBasicBlock *&TBB,
116 MachineBasicBlock *&FBB,
117 SmallVectorImpl<MachineOperand> &Cond,
118 bool AllowModify) const {
119 // If the block has no terminators, it just falls into the block after it.
120 MachineBasicBlock::iterator I = MBB.end();
121 if (I == MBB.begin())
124 while (I->isDebugValue()) {
125 if (I == MBB.begin())
129 if (!isUnpredicatedTerminator(I))
132 // Get the last instruction in the block.
133 MachineInstr *LastInst = I;
135 // If there is only one terminator instruction, process it.
136 unsigned LastOpc = LastInst->getOpcode();
137 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
138 if (MBlaze::isUncondBranchOpcode(LastOpc)) {
139 TBB = LastInst->getOperand(0).getMBB();
142 if (MBlaze::isCondBranchOpcode(LastOpc)) {
143 // Block ends with fall-through condbranch.
144 TBB = LastInst->getOperand(1).getMBB();
145 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
146 Cond.push_back(LastInst->getOperand(0));
149 // Otherwise, don't know what this is.
153 // Get the instruction before it if it's a terminator.
154 MachineInstr *SecondLastInst = I;
156 // If there are three terminators, we don't know what sort of block this is.
157 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
160 // If the block ends with something like BEQID then BRID, handle it.
161 if (MBlaze::isCondBranchOpcode(SecondLastInst->getOpcode()) &&
162 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) {
163 TBB = SecondLastInst->getOperand(1).getMBB();
164 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
165 Cond.push_back(SecondLastInst->getOperand(0));
166 FBB = LastInst->getOperand(0).getMBB();
170 // If the block ends with two unconditional branches, handle it.
171 // The second one is not executed, so remove it.
172 if (MBlaze::isUncondBranchOpcode(SecondLastInst->getOpcode()) &&
173 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) {
174 TBB = SecondLastInst->getOperand(0).getMBB();
177 I->eraseFromParent();
181 // Otherwise, can't handle this.
185 unsigned MBlazeInstrInfo::
186 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
187 MachineBasicBlock *FBB,
188 const SmallVectorImpl<MachineOperand> &Cond,
190 // Shouldn't be a fall through.
191 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
192 assert((Cond.size() == 2 || Cond.size() == 0) &&
193 "MBlaze branch conditions have two components!");
195 unsigned Opc = MBlaze::BRID;
197 Opc = (unsigned)Cond[0].getImm();
200 if (Cond.empty()) // Unconditional branch
201 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
202 else // Conditional branch
203 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
207 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
208 BuildMI(&MBB, DL, get(MBlaze::BRID)).addMBB(FBB);
212 unsigned MBlazeInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
213 MachineBasicBlock::iterator I = MBB.end();
214 if (I == MBB.begin()) return 0;
216 while (I->isDebugValue()) {
217 if (I == MBB.begin())
222 if (!MBlaze::isUncondBranchOpcode(I->getOpcode()) &&
223 !MBlaze::isCondBranchOpcode(I->getOpcode()))
226 // Remove the branch.
227 I->eraseFromParent();
231 if (I == MBB.begin()) return 1;
233 if (!MBlaze::isCondBranchOpcode(I->getOpcode()))
236 // Remove the branch.
237 I->eraseFromParent();
241 bool MBlazeInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
242 assert(Cond.size() == 2 && "Invalid MBlaze branch opcode!");
243 switch (Cond[0].getImm()) {
244 default: return true;
245 case MBlaze::BEQ: Cond[0].setImm(MBlaze::BNE); return false;
246 case MBlaze::BNE: Cond[0].setImm(MBlaze::BEQ); return false;
247 case MBlaze::BGT: Cond[0].setImm(MBlaze::BLE); return false;
248 case MBlaze::BGE: Cond[0].setImm(MBlaze::BLT); return false;
249 case MBlaze::BLT: Cond[0].setImm(MBlaze::BGE); return false;
250 case MBlaze::BLE: Cond[0].setImm(MBlaze::BGT); return false;
251 case MBlaze::BEQI: Cond[0].setImm(MBlaze::BNEI); return false;
252 case MBlaze::BNEI: Cond[0].setImm(MBlaze::BEQI); return false;
253 case MBlaze::BGTI: Cond[0].setImm(MBlaze::BLEI); return false;
254 case MBlaze::BGEI: Cond[0].setImm(MBlaze::BLTI); return false;
255 case MBlaze::BLTI: Cond[0].setImm(MBlaze::BGEI); return false;
256 case MBlaze::BLEI: Cond[0].setImm(MBlaze::BGTI); return false;
257 case MBlaze::BEQD: Cond[0].setImm(MBlaze::BNED); return false;
258 case MBlaze::BNED: Cond[0].setImm(MBlaze::BEQD); return false;
259 case MBlaze::BGTD: Cond[0].setImm(MBlaze::BLED); return false;
260 case MBlaze::BGED: Cond[0].setImm(MBlaze::BLTD); return false;
261 case MBlaze::BLTD: Cond[0].setImm(MBlaze::BGED); return false;
262 case MBlaze::BLED: Cond[0].setImm(MBlaze::BGTD); return false;
263 case MBlaze::BEQID: Cond[0].setImm(MBlaze::BNEID); return false;
264 case MBlaze::BNEID: Cond[0].setImm(MBlaze::BEQID); return false;
265 case MBlaze::BGTID: Cond[0].setImm(MBlaze::BLEID); return false;
266 case MBlaze::BGEID: Cond[0].setImm(MBlaze::BLTID); return false;
267 case MBlaze::BLTID: Cond[0].setImm(MBlaze::BGEID); return false;
268 case MBlaze::BLEID: Cond[0].setImm(MBlaze::BGTID); return false;
272 /// getGlobalBaseReg - Return a virtual register initialized with the
273 /// the global base register value. Output instructions required to
274 /// initialize the register in the function entry block, if necessary.
276 unsigned MBlazeInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
277 MBlazeFunctionInfo *MBlazeFI = MF->getInfo<MBlazeFunctionInfo>();
278 unsigned GlobalBaseReg = MBlazeFI->getGlobalBaseReg();
279 if (GlobalBaseReg != 0)
280 return GlobalBaseReg;
282 // Insert the set of GlobalBaseReg into the first MBB of the function
283 MachineBasicBlock &FirstMBB = MF->front();
284 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
285 MachineRegisterInfo &RegInfo = MF->getRegInfo();
286 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
288 GlobalBaseReg = RegInfo.createVirtualRegister(MBlaze::GPRRegisterClass);
289 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
290 GlobalBaseReg).addReg(MBlaze::R20);
291 RegInfo.addLiveIn(MBlaze::R20);
293 MBlazeFI->setGlobalBaseReg(GlobalBaseReg);
294 return GlobalBaseReg;