1 //===- MBlazeInstrInfo.cpp - MBlaze Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MBlaze implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MBlazeInstrInfo.h"
15 #include "MBlazeTargetMachine.h"
16 #include "MBlazeMachineFunction.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "MBlazeGenInstrInfo.inc"
25 MBlazeInstrInfo::MBlazeInstrInfo(MBlazeTargetMachine &tm)
26 : TargetInstrInfoImpl(MBlazeInsts, array_lengthof(MBlazeInsts)),
27 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
29 static bool isZeroImm(const MachineOperand &op) {
30 return op.isImm() && op.getImm() == 0;
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
35 bool MBlazeInstrInfo::
36 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
37 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
38 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
40 // add $dst, $src, $zero || addu $dst, $zero, $src
41 // or $dst, $src, $zero || or $dst, $zero, $src
42 if ((MI.getOpcode() == MBlaze::ADD) || (MI.getOpcode() == MBlaze::OR)) {
43 if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == MBlaze::R0) {
44 DstReg = MI.getOperand(0).getReg();
45 SrcReg = MI.getOperand(2).getReg();
47 } else if (MI.getOperand(2).isReg() &&
48 MI.getOperand(2).getReg() == MBlaze::R0) {
49 DstReg = MI.getOperand(0).getReg();
50 SrcReg = MI.getOperand(1).getReg();
57 if ((MI.getOpcode() == MBlaze::ADDI) || (MI.getOpcode() == MBlaze::ORI)) {
58 if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
59 DstReg = MI.getOperand(0).getReg();
60 SrcReg = MI.getOperand(1).getReg();
68 /// isLoadFromStackSlot - If the specified machine instruction is a direct
69 /// load from a stack slot, return the virtual or physical register number of
70 /// the destination along with the FrameIndex of the loaded stack slot. If
71 /// not, return 0. This predicate must return 0 if the instruction has
72 /// any side effects other than loading from the stack slot.
73 unsigned MBlazeInstrInfo::
74 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const {
75 if (MI->getOpcode() == MBlaze::LWI) {
76 if ((MI->getOperand(2).isFI()) && // is a stack slot
77 (MI->getOperand(1).isImm()) && // the imm is zero
78 (isZeroImm(MI->getOperand(1)))) {
79 FrameIndex = MI->getOperand(2).getIndex();
80 return MI->getOperand(0).getReg();
87 /// isStoreToStackSlot - If the specified machine instruction is a direct
88 /// store to a stack slot, return the virtual or physical register number of
89 /// the source reg along with the FrameIndex of the loaded stack slot. If
90 /// not, return 0. This predicate must return 0 if the instruction has
91 /// any side effects other than storing to the stack slot.
92 unsigned MBlazeInstrInfo::
93 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const {
94 if (MI->getOpcode() == MBlaze::SWI) {
95 if ((MI->getOperand(2).isFI()) && // is a stack slot
96 (MI->getOperand(1).isImm()) && // the imm is zero
97 (isZeroImm(MI->getOperand(1)))) {
98 FrameIndex = MI->getOperand(2).getIndex();
99 return MI->getOperand(0).getReg();
105 /// insertNoop - If data hazard condition is found insert the target nop
107 void MBlazeInstrInfo::
108 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
110 BuildMI(MBB, MI, DL, get(MBlaze::NOP));
113 bool MBlazeInstrInfo::
114 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
115 unsigned DestReg, unsigned SrcReg,
116 const TargetRegisterClass *DestRC,
117 const TargetRegisterClass *SrcRC) const {
119 llvm::BuildMI(MBB, I, DL, get(MBlaze::ADD), DestReg)
120 .addReg(SrcReg).addReg(MBlaze::R0);
124 void MBlazeInstrInfo::
125 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
126 unsigned SrcReg, bool isKill, int FI,
127 const TargetRegisterClass *RC,
128 const TargetRegisterInfo *TRI) const {
130 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
131 .addImm(0).addFrameIndex(FI);
134 void MBlazeInstrInfo::
135 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
136 unsigned DestReg, int FI,
137 const TargetRegisterClass *RC,
138 const TargetRegisterInfo *TRI) const {
140 BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg)
141 .addImm(0).addFrameIndex(FI);
144 MachineInstr *MBlazeInstrInfo::
145 foldMemoryOperandImpl(MachineFunction &MF,
147 const SmallVectorImpl<unsigned> &Ops, int FI) const {
148 if (Ops.size() != 1) return NULL;
150 MachineInstr *NewMI = NULL;
152 switch (MI->getOpcode()) {
155 if ((MI->getOperand(0).isReg()) &&
156 (MI->getOperand(2).isReg()) &&
157 (MI->getOperand(2).getReg() == MBlaze::R0) &&
158 (MI->getOperand(1).isReg())) {
159 if (Ops[0] == 0) { // COPY -> STORE
160 unsigned SrcReg = MI->getOperand(1).getReg();
161 bool isKill = MI->getOperand(1).isKill();
162 bool isUndef = MI->getOperand(1).isUndef();
163 NewMI = BuildMI(MF, MI->getDebugLoc(), get(MBlaze::SW))
164 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
165 .addImm(0).addFrameIndex(FI);
166 } else { // COPY -> LOAD
167 unsigned DstReg = MI->getOperand(0).getReg();
168 bool isDead = MI->getOperand(0).isDead();
169 bool isUndef = MI->getOperand(0).isUndef();
170 NewMI = BuildMI(MF, MI->getDebugLoc(), get(MBlaze::LW))
171 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
172 getUndefRegState(isUndef))
173 .addImm(0).addFrameIndex(FI);
182 //===----------------------------------------------------------------------===//
184 //===----------------------------------------------------------------------===//
185 unsigned MBlazeInstrInfo::
186 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
187 MachineBasicBlock *FBB,
188 const SmallVectorImpl<MachineOperand> &Cond) const {
189 // Can only insert uncond branches so far.
190 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
191 BuildMI(&MBB, DebugLoc(), get(MBlaze::BRI)).addMBB(TBB);
195 /// getGlobalBaseReg - Return a virtual register initialized with the
196 /// the global base register value. Output instructions required to
197 /// initialize the register in the function entry block, if necessary.
199 unsigned MBlazeInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
200 MBlazeFunctionInfo *MBlazeFI = MF->getInfo<MBlazeFunctionInfo>();
201 unsigned GlobalBaseReg = MBlazeFI->getGlobalBaseReg();
202 if (GlobalBaseReg != 0)
203 return GlobalBaseReg;
205 // Insert the set of GlobalBaseReg into the first MBB of the function
206 MachineBasicBlock &FirstMBB = MF->front();
207 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
208 MachineRegisterInfo &RegInfo = MF->getRegInfo();
209 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
211 GlobalBaseReg = RegInfo.createVirtualRegister(MBlaze::CPURegsRegisterClass);
212 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, MBlaze::R20,
213 MBlaze::CPURegsRegisterClass,
214 MBlaze::CPURegsRegisterClass);
215 assert(Ok && "Couldn't assign to global base register!");
216 Ok = Ok; // Silence warning when assertions are turned off.
217 RegInfo.addLiveIn(MBlaze::R20);
219 MBlazeFI->setGlobalBaseReg(GlobalBaseReg);
220 return GlobalBaseReg;