1 //===-- MBlazeInstrInfo.h - MBlaze Instruction Information ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MBlaze implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MBLAZEINSTRUCTIONINFO_H
15 #define MBLAZEINSTRUCTIONINFO_H
18 #include "MBlazeRegisterInfo.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Target/TargetInstrInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #include "MBlazeGenInstrInfo.inc"
29 // MBlaze Branch Codes
38 // MBlaze Condition Codes
40 // To be used with float branch True
58 // To be used with float branch False
59 // This conditions have the same mnemonic as the
60 // above ones, but are used with a branch False;
78 // Only integer conditions
88 // Turn condition code into conditional branch opcode.
89 inline static unsigned GetCondBranchFromCond(CondCode CC) {
91 default: llvm_unreachable("Unknown condition code");
92 case COND_EQ: return MBlaze::BEQID;
93 case COND_NE: return MBlaze::BNEID;
94 case COND_GT: return MBlaze::BGTID;
95 case COND_GE: return MBlaze::BGEID;
96 case COND_LT: return MBlaze::BLTID;
97 case COND_LE: return MBlaze::BLEID;
101 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
102 /// e.g. turning COND_E to COND_NE.
103 // CondCode GetOppositeBranchCondition(MBlaze::CondCode CC);
105 /// MBlazeCCToString - Map each FP condition code to its string
106 inline static const char *MBlazeFCCToString(MBlaze::CondCode CC) {
108 default: llvm_unreachable("Unknown condition code");
110 case FCOND_T: return "f";
112 case FCOND_OR: return "un";
114 case FCOND_NEQ: return "eq";
116 case FCOND_OGL: return "ueq";
118 case FCOND_UGE: return "olt";
120 case FCOND_OGE: return "ult";
122 case FCOND_UGT: return "ole";
124 case FCOND_OGT: return "ule";
126 case FCOND_ST: return "sf";
128 case FCOND_GLE: return "ngle";
130 case FCOND_SNE: return "seq";
132 case FCOND_GL: return "ngl";
134 case FCOND_NLT: return "lt";
136 case FCOND_GE: return "ge";
138 case FCOND_NLE: return "nle";
140 case FCOND_GT: return "gt";
144 inline static bool isUncondBranchOpcode(int Opc) {
146 default: return false;
155 inline static bool isCondBranchOpcode(int Opc) {
157 default: return false;
158 case MBlaze::BEQI: case MBlaze::BEQID:
159 case MBlaze::BNEI: case MBlaze::BNEID:
160 case MBlaze::BGTI: case MBlaze::BGTID:
161 case MBlaze::BGEI: case MBlaze::BGEID:
162 case MBlaze::BLTI: case MBlaze::BLTID:
163 case MBlaze::BLEI: case MBlaze::BLEID:
169 class MBlazeInstrInfo : public MBlazeGenInstrInfo {
170 MBlazeTargetMachine &TM;
171 const MBlazeRegisterInfo RI;
173 explicit MBlazeInstrInfo(MBlazeTargetMachine &TM);
175 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
176 /// such, whenever a client has an instance of instruction info, it should
177 /// always be able to get register info as well (through this method).
179 virtual const MBlazeRegisterInfo &getRegisterInfo() const { return RI; }
181 /// isLoadFromStackSlot - If the specified machine instruction is a direct
182 /// load from a stack slot, return the virtual or physical register number of
183 /// the destination along with the FrameIndex of the loaded stack slot. If
184 /// not, return 0. This predicate must return 0 if the instruction has
185 /// any side effects other than loading from the stack slot.
186 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
187 int &FrameIndex) const;
189 /// isStoreToStackSlot - If the specified machine instruction is a direct
190 /// store to a stack slot, return the virtual or physical register number of
191 /// the source reg along with the FrameIndex of the loaded stack slot. If
192 /// not, return 0. This predicate must return 0 if the instruction has
193 /// any side effects other than storing to the stack slot.
194 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
195 int &FrameIndex) const;
198 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
199 MachineBasicBlock *&FBB,
200 SmallVectorImpl<MachineOperand> &Cond,
201 bool AllowModify) const;
202 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
203 MachineBasicBlock *FBB,
204 const SmallVectorImpl<MachineOperand> &Cond,
206 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
208 virtual bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
211 virtual void copyPhysReg(MachineBasicBlock &MBB,
212 MachineBasicBlock::iterator I, DebugLoc DL,
213 unsigned DestReg, unsigned SrcReg,
215 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
216 MachineBasicBlock::iterator MBBI,
217 unsigned SrcReg, bool isKill, int FrameIndex,
218 const TargetRegisterClass *RC,
219 const TargetRegisterInfo *TRI) const;
221 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
222 MachineBasicBlock::iterator MBBI,
223 unsigned DestReg, int FrameIndex,
224 const TargetRegisterClass *RC,
225 const TargetRegisterInfo *TRI) const;
227 /// Insert nop instruction when hazard condition is found
228 virtual void insertNoop(MachineBasicBlock &MBB,
229 MachineBasicBlock::iterator MI) const;
231 /// getGlobalBaseReg - Return a virtual register initialized with the
232 /// the global base register value. Output instructions required to
233 /// initialize the register in the function entry block, if necessary.
235 unsigned getGlobalBaseReg(MachineFunction *MF) const;