1 //===- MBlazeInstrInfo.td - MBlaze Instruction defs --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
13 include "MBlazeInstrFormats.td"
15 //===----------------------------------------------------------------------===//
16 // MBlaze type profiles
17 //===----------------------------------------------------------------------===//
19 // def SDTMBlazeSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>]>;
20 def SDT_MBlazeRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
21 def SDT_MBlazeIRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
22 def SDT_MBlazeJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
23 def SDT_MBCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
24 def SDT_MBCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 //===----------------------------------------------------------------------===//
27 // MBlaze specific nodes
28 //===----------------------------------------------------------------------===//
30 def MBlazeRet : SDNode<"MBlazeISD::Ret", SDT_MBlazeRet,
31 [SDNPHasChain, SDNPOptInFlag]>;
32 def MBlazeIRet : SDNode<"MBlazeISD::IRet", SDT_MBlazeIRet,
33 [SDNPHasChain, SDNPOptInFlag]>;
35 def MBlazeJmpLink : SDNode<"MBlazeISD::JmpLink",SDT_MBlazeJmpLink,
36 [SDNPHasChain,SDNPOptInFlag,SDNPOutFlag]>;
38 def MBWrapper : SDNode<"MBlazeISD::Wrap", SDTIntUnaryOp>;
40 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MBCallSeqStart,
41 [SDNPHasChain, SDNPOutFlag]>;
43 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MBCallSeqEnd,
44 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
46 //===----------------------------------------------------------------------===//
47 // MBlaze Instruction Predicate Definitions.
48 //===----------------------------------------------------------------------===//
49 def HasPipe3 : Predicate<"Subtarget.hasPipe3()">;
50 def HasBarrel : Predicate<"Subtarget.hasBarrel()">;
51 def NoBarrel : Predicate<"!Subtarget.hasBarrel()">;
52 def HasDiv : Predicate<"Subtarget.hasDiv()">;
53 def HasMul : Predicate<"Subtarget.hasMul()">;
54 def HasFSL : Predicate<"Subtarget.hasFSL()">;
55 def HasEFSL : Predicate<"Subtarget.hasEFSL()">;
56 def HasMSRSet : Predicate<"Subtarget.hasMSRSet()">;
57 def HasException : Predicate<"Subtarget.hasException()">;
58 def HasPatCmp : Predicate<"Subtarget.hasPatCmp()">;
59 def HasFPU : Predicate<"Subtarget.hasFPU()">;
60 def HasESR : Predicate<"Subtarget.hasESR()">;
61 def HasPVR : Predicate<"Subtarget.hasPVR()">;
62 def HasMul64 : Predicate<"Subtarget.hasMul64()">;
63 def HasSqrt : Predicate<"Subtarget.hasSqrt()">;
64 def HasMMU : Predicate<"Subtarget.hasMMU()">;
66 //===----------------------------------------------------------------------===//
67 // MBlaze Operand, Complex Patterns and Transformations Definitions.
68 //===----------------------------------------------------------------------===//
70 def MBlazeMemAsmOperand : AsmOperandClass {
72 let SuperClasses = [];
75 def MBlazeFslAsmOperand : AsmOperandClass {
77 let SuperClasses = [];
80 // Instruction operand types
81 def brtarget : Operand<OtherVT>;
82 def calltarget : Operand<i32>;
83 def simm16 : Operand<i32>;
84 def uimm5 : Operand<i32>;
85 def uimm14 : Operand<i32>;
86 def uimm15 : Operand<i32>;
87 def fimm : Operand<f32>;
90 def uimm16 : Operand<i32> {
91 let PrintMethod = "printUnsignedImm";
95 def fslimm : Operand<i32> {
96 let PrintMethod = "printFSLImm";
97 let ParserMatchClass = MBlazeFslAsmOperand;
101 def memri : Operand<i32> {
102 let PrintMethod = "printMemOperand";
103 let MIOperandInfo = (ops GPR, simm16);
104 let ParserMatchClass = MBlazeMemAsmOperand;
107 def memrr : Operand<i32> {
108 let PrintMethod = "printMemOperand";
109 let MIOperandInfo = (ops GPR, GPR);
110 let ParserMatchClass = MBlazeMemAsmOperand;
113 // Node immediate fits as 16-bit sign extended on target immediate.
114 def immSExt16 : PatLeaf<(imm), [{
115 return (N->getZExtValue() >> 16) == 0;
118 // Node immediate fits as 16-bit zero extended on target immediate.
119 // The LO16 param means that only the lower 16 bits of the node
120 // immediate are caught.
122 def immZExt16 : PatLeaf<(imm), [{
123 return (N->getZExtValue() >> 16) == 0;
126 // FSL immediate field must fit in 4 bits.
127 def immZExt4 : PatLeaf<(imm), [{
128 return N->getZExtValue() == ((N->getZExtValue()) & 0xf) ;
131 // shamt field must fit in 5 bits.
132 def immZExt5 : PatLeaf<(imm), [{
133 return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
136 // MBlaze Address Mode. SDNode frameindex could possibily be a match
137 // since load and store instructions from stack used it.
138 def iaddr : ComplexPattern<i32, 2, "SelectAddrRegImm", [frameindex], []>;
139 def xaddr : ComplexPattern<i32, 2, "SelectAddrRegReg", [], []>;
141 //===----------------------------------------------------------------------===//
142 // Pseudo instructions
143 //===----------------------------------------------------------------------===//
145 // As stack alignment is always done with addiu, we need a 16-bit immediate
146 let Defs = [R1], Uses = [R1] in {
147 def ADJCALLSTACKDOWN : MBlazePseudo<(outs), (ins simm16:$amt),
148 "#ADJCALLSTACKDOWN $amt",
149 [(callseq_start timm:$amt)]>;
150 def ADJCALLSTACKUP : MBlazePseudo<(outs),
151 (ins uimm16:$amt1, simm16:$amt2),
152 "#ADJCALLSTACKUP $amt1",
153 [(callseq_end timm:$amt1, timm:$amt2)]>;
156 //===----------------------------------------------------------------------===//
157 // Instructions specific format
158 //===----------------------------------------------------------------------===//
160 //===----------------------------------------------------------------------===//
161 // Arithmetic Instructions
162 //===----------------------------------------------------------------------===//
163 class Arith<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
164 InstrItinClass itin> :
165 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
166 !strconcat(instr_asm, " $dst, $b, $c"),
167 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
169 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
170 Operand Od, PatLeaf imm_type> :
171 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
172 !strconcat(instr_asm, " $dst, $b, $c"),
173 [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIAlu>;
175 class ArithI32<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
176 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
177 !strconcat(instr_asm, " $dst, $b, $c"),
180 class ShiftI<bits<6> op, bits<2> flags, string instr_asm, SDNode OpNode,
181 Operand Od, PatLeaf imm_type> :
182 SHT<op, flags, (outs GPR:$dst), (ins GPR:$b, Od:$c),
183 !strconcat(instr_asm, " $dst, $b, $c"),
184 [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIAlu>;
186 class ArithR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
187 InstrItinClass itin> :
188 TAR<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
189 !strconcat(instr_asm, " $dst, $c, $b"),
190 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
192 class ArithRI<bits<6> op, string instr_asm, SDNode OpNode,
193 Operand Od, PatLeaf imm_type> :
194 TBR<op, (outs GPR:$dst), (ins Od:$b, GPR:$c),
195 !strconcat(instr_asm, " $dst, $c, $b"),
196 [(set GPR:$dst, (OpNode imm_type:$b, GPR:$c))], IIAlu>;
198 class ArithN<bits<6> op, bits<11> flags, string instr_asm,
199 InstrItinClass itin> :
200 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
201 !strconcat(instr_asm, " $dst, $b, $c"),
204 class ArithNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
205 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
206 !strconcat(instr_asm, " $dst, $b, $c"),
209 class ArithRN<bits<6> op, bits<11> flags, string instr_asm,
210 InstrItinClass itin> :
211 TAR<op, flags, (outs GPR:$dst), (ins GPR:$c, GPR:$b),
212 !strconcat(instr_asm, " $dst, $b, $c"),
215 class ArithRNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
216 TBR<op, (outs GPR:$dst), (ins Od:$c, GPR:$b),
217 !strconcat(instr_asm, " $dst, $b, $c"),
220 //===----------------------------------------------------------------------===//
221 // Misc Arithmetic Instructions
222 //===----------------------------------------------------------------------===//
224 class Logic<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode> :
225 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
226 !strconcat(instr_asm, " $dst, $b, $c"),
227 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], IIAlu>;
229 class LogicI<bits<6> op, string instr_asm, SDNode OpNode> :
230 TB<op, (outs GPR:$dst), (ins GPR:$b, uimm16:$c),
231 !strconcat(instr_asm, " $dst, $b, $c"),
232 [(set GPR:$dst, (OpNode GPR:$b, immZExt16:$c))],
235 class LogicI32<bits<6> op, string instr_asm> :
236 TB<op, (outs GPR:$dst), (ins GPR:$b, uimm16:$c),
237 !strconcat(instr_asm, " $dst, $b, $c"),
240 class PatCmp<bits<6> op, bits<11> flags, string instr_asm> :
241 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
242 !strconcat(instr_asm, " $dst, $b, $c"),
245 //===----------------------------------------------------------------------===//
246 // Memory Access Instructions
247 //===----------------------------------------------------------------------===//
248 class LoadM<bits<6> op, bits<11> flags, string instr_asm> :
249 TA<op, flags, (outs GPR:$dst), (ins memrr:$addr),
250 !strconcat(instr_asm, " $dst, $addr"),
253 class LoadMI<bits<6> op, string instr_asm, PatFrag OpNode> :
254 TB<op, (outs GPR:$dst), (ins memri:$addr),
255 !strconcat(instr_asm, " $dst, $addr"),
256 [(set (i32 GPR:$dst), (OpNode iaddr:$addr))], IILoad>;
258 class StoreM<bits<6> op, bits<11> flags, string instr_asm> :
259 TA<op, flags, (outs), (ins GPR:$dst, memrr:$addr),
260 !strconcat(instr_asm, " $dst, $addr"),
263 class StoreMI<bits<6> op, string instr_asm, PatFrag OpNode> :
264 TB<op, (outs), (ins GPR:$dst, memri:$addr),
265 !strconcat(instr_asm, " $dst, $addr"),
266 [(OpNode (i32 GPR:$dst), iaddr:$addr)], IIStore>;
268 //===----------------------------------------------------------------------===//
269 // Branch Instructions
270 //===----------------------------------------------------------------------===//
271 class Branch<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
272 TA<op, flags, (outs), (ins GPR:$target),
273 !strconcat(instr_asm, " $target"),
280 class BranchI<bits<6> op, bits<5> br, string instr_asm> :
281 TB<op, (outs), (ins brtarget:$target),
282 !strconcat(instr_asm, " $target"),
289 //===----------------------------------------------------------------------===//
290 // Branch and Link Instructions
291 //===----------------------------------------------------------------------===//
292 class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
293 TA<op, flags, (outs), (ins GPR:$link, GPR:$target),
294 !strconcat(instr_asm, " $link, $target"),
300 class BranchLI<bits<6> op, bits<5> br, string instr_asm> :
301 TB<op, (outs), (ins GPR:$link, calltarget:$target),
302 !strconcat(instr_asm, " $link, $target"),
308 //===----------------------------------------------------------------------===//
309 // Conditional Branch Instructions
310 //===----------------------------------------------------------------------===//
311 class BranchC<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
312 TA<op, flags, (outs),
313 (ins GPR:$a, GPR:$b),
314 !strconcat(instr_asm, " $a, $b"),
320 class BranchCI<bits<6> op, bits<5> br, string instr_asm> :
321 TB<op, (outs), (ins GPR:$a, brtarget:$offset),
322 !strconcat(instr_asm, " $a, $offset"),
328 //===----------------------------------------------------------------------===//
329 // MBlaze arithmetic instructions
330 //===----------------------------------------------------------------------===//
332 let isCommutable = 1, isAsCheapAsAMove = 1 in {
333 def ADD : Arith<0x00, 0x000, "add ", addc, IIAlu>;
334 def ADDC : Arith<0x02, 0x000, "addc ", adde, IIAlu>;
335 def ADDK : Arith<0x04, 0x000, "addk ", add, IIAlu>;
336 def ADDKC : ArithN<0x06, 0x000, "addkc ", IIAlu>;
337 def AND : Logic<0x21, 0x000, "and ", and>;
338 def OR : Logic<0x20, 0x000, "or ", or>;
339 def XOR : Logic<0x22, 0x000, "xor ", xor>;
340 def PCMPBF : PatCmp<0x20, 0x400, "pcmpbf ">;
341 def PCMPEQ : PatCmp<0x22, 0x400, "pcmpeq ">;
342 def PCMPNE : PatCmp<0x23, 0x400, "pcmpne ">;
345 let isAsCheapAsAMove = 1 in {
346 def ANDN : ArithN<0x23, 0x000, "andn ", IIAlu>;
347 def CMP : ArithN<0x05, 0x001, "cmp ", IIAlu>;
348 def CMPU : ArithN<0x05, 0x003, "cmpu ", IIAlu>;
349 def RSUB : ArithR<0x01, 0x000, "rsub ", subc, IIAlu>;
350 def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIAlu>;
351 def RSUBK : ArithR<0x05, 0x000, "rsubk ", sub, IIAlu>;
352 def RSUBKC : ArithRN<0x07, 0x000, "rsubkc ", IIAlu>;
355 let isCommutable = 1, Predicates=[HasMul] in {
356 def MUL : Arith<0x10, 0x000, "mul ", mul, IIAlu>;
359 let isCommutable = 1, Predicates=[HasMul,HasMul64] in {
360 def MULH : Arith<0x10, 0x001, "mulh ", mulhs, IIAlu>;
361 def MULHU : Arith<0x10, 0x003, "mulhu ", mulhu, IIAlu>;
364 let Predicates=[HasMul,HasMul64] in {
365 def MULHSU : ArithN<0x10, 0x002, "mulhsu ", IIAlu>;
368 let Predicates=[HasBarrel] in {
369 def BSRL : Arith<0x11, 0x000, "bsrl ", srl, IIAlu>;
370 def BSRA : Arith<0x11, 0x200, "bsra ", sra, IIAlu>;
371 def BSLL : Arith<0x11, 0x400, "bsll ", shl, IIAlu>;
372 def BSRLI : ShiftI<0x19, 0x0, "bsrli ", srl, uimm5, immZExt5>;
373 def BSRAI : ShiftI<0x19, 0x1, "bsrai ", sra, uimm5, immZExt5>;
374 def BSLLI : ShiftI<0x19, 0x2, "bslli ", shl, uimm5, immZExt5>;
377 let Predicates=[HasDiv] in {
378 def IDIV : ArithR<0x12, 0x000, "idiv ", sdiv, IIAlu>;
379 def IDIVU : ArithR<0x12, 0x002, "idivu ", udiv, IIAlu>;
382 //===----------------------------------------------------------------------===//
383 // MBlaze immediate mode arithmetic instructions
384 //===----------------------------------------------------------------------===//
386 let isAsCheapAsAMove = 1 in {
387 def ADDI : ArithI<0x08, "addi ", addc, simm16, immSExt16>;
388 def ADDIC : ArithI<0x0A, "addic ", adde, simm16, immSExt16>;
389 def ADDIK : ArithI<0x0C, "addik ", add, simm16, immSExt16>;
390 def ADDIKC : ArithNI<0x0E, "addikc ", simm16, immSExt16>;
391 def RSUBI : ArithRI<0x09, "rsubi ", subc, simm16, immSExt16>;
392 def RSUBIC : ArithRI<0x0B, "rsubic ", sube, simm16, immSExt16>;
393 def RSUBIK : ArithRI<0x0D, "rsubik ", sub, simm16, immSExt16>;
394 def RSUBIKC : ArithRNI<0x0F, "rsubikc", simm16, immSExt16>;
395 def ANDNI : ArithNI<0x2B, "andni ", uimm16, immZExt16>;
396 def ANDI : LogicI<0x29, "andi ", and>;
397 def ORI : LogicI<0x28, "ori ", or>;
398 def XORI : LogicI<0x2A, "xori ", xor>;
401 let Predicates=[HasMul] in {
402 def MULI : ArithI<0x18, "muli ", mul, simm16, immSExt16>;
405 //===----------------------------------------------------------------------===//
406 // MBlaze memory access instructions
407 //===----------------------------------------------------------------------===//
409 let canFoldAsLoad = 1, isReMaterializable = 1 in {
410 def LBU : LoadM<0x30, 0x000, "lbu ">;
411 def LBUR : LoadM<0x30, 0x200, "lbur ">;
413 def LHU : LoadM<0x31, 0x000, "lhu ">;
414 def LHUR : LoadM<0x31, 0x200, "lhur ">;
416 def LW : LoadM<0x32, 0x000, "lw ">;
417 def LWR : LoadM<0x32, 0x200, "lwr ">;
418 def LWX : LoadM<0x32, 0x400, "lwx ">;
420 def LBUI : LoadMI<0x38, "lbui ", zextloadi8>;
421 def LHUI : LoadMI<0x39, "lhui ", zextloadi16>;
422 def LWI : LoadMI<0x3A, "lwi ", load>;
425 def SB : StoreM<0x34, 0x000, "sb ">;
426 def SBR : StoreM<0x34, 0x200, "sbr ">;
428 def SH : StoreM<0x35, 0x000, "sh ">;
429 def SHR : StoreM<0x35, 0x200, "shr ">;
431 def SW : StoreM<0x36, 0x000, "sw ">;
432 def SWR : StoreM<0x36, 0x200, "swr ">;
433 def SWX : StoreM<0x36, 0x400, "swx ">;
435 def SBI : StoreMI<0x3C, "sbi ", truncstorei8>;
436 def SHI : StoreMI<0x3D, "shi ", truncstorei16>;
437 def SWI : StoreMI<0x3E, "swi ", store>;
439 //===----------------------------------------------------------------------===//
440 // MBlaze branch instructions
441 //===----------------------------------------------------------------------===//
443 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
444 def BRI : BranchI<0x2E, 0x00, "bri ">;
445 def BRAI : BranchI<0x2E, 0x08, "brai ">;
448 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
449 def BEQI : BranchCI<0x2F, 0x00, "beqi ">;
450 def BNEI : BranchCI<0x2F, 0x01, "bnei ">;
451 def BLTI : BranchCI<0x2F, 0x02, "blti ">;
452 def BLEI : BranchCI<0x2F, 0x03, "blei ">;
453 def BGTI : BranchCI<0x2F, 0x04, "bgti ">;
454 def BGEI : BranchCI<0x2F, 0x05, "bgei ">;
457 let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1,
459 def BR : Branch<0x26, 0x00, 0x000, "br ">;
460 def BRA : Branch<0x26, 0x08, 0x000, "bra ">;
463 let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
464 def BEQ : BranchC<0x27, 0x00, 0x000, "beq ">;
465 def BNE : BranchC<0x27, 0x01, 0x000, "bne ">;
466 def BLT : BranchC<0x27, 0x02, 0x000, "blt ">;
467 def BLE : BranchC<0x27, 0x03, 0x000, "ble ">;
468 def BGT : BranchC<0x27, 0x04, 0x000, "bgt ">;
469 def BGE : BranchC<0x27, 0x05, 0x000, "bge ">;
472 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1,
474 def BRID : BranchI<0x2E, 0x10, "brid ">;
475 def BRAID : BranchI<0x2E, 0x18, "braid ">;
478 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1 in {
479 def BEQID : BranchCI<0x2F, 0x10, "beqid ">;
480 def BNEID : BranchCI<0x2F, 0x11, "bneid ">;
481 def BLTID : BranchCI<0x2F, 0x12, "bltid ">;
482 def BLEID : BranchCI<0x2F, 0x13, "bleid ">;
483 def BGTID : BranchCI<0x2F, 0x14, "bgtid ">;
484 def BGEID : BranchCI<0x2F, 0x15, "bgeid ">;
487 let isBranch = 1, isIndirectBranch = 1, isTerminator = 1,
488 hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1 in {
489 def BRD : Branch<0x26, 0x10, 0x000, "brd ">;
490 def BRAD : Branch<0x26, 0x18, 0x000, "brad ">;
493 let isBranch = 1, isIndirectBranch = 1, isTerminator = 1,
494 hasDelaySlot = 1, hasCtrlDep = 1 in {
495 def BEQD : BranchC<0x27, 0x10, 0x000, "beqd ">;
496 def BNED : BranchC<0x27, 0x11, 0x000, "bned ">;
497 def BLTD : BranchC<0x27, 0x12, 0x000, "bltd ">;
498 def BLED : BranchC<0x27, 0x13, 0x000, "bled ">;
499 def BGTD : BranchC<0x27, 0x14, 0x000, "bgtd ">;
500 def BGED : BranchC<0x27, 0x15, 0x000, "bged ">;
503 let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1,
504 Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
505 Uses = [R1,R5,R6,R7,R8,R9,R10] in {
506 def BRLID : BranchLI<0x2E, 0x14, "brlid ">;
507 def BRALID : BranchLI<0x2E, 0x1C, "bralid ">;
510 let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isIndirectBranch = 1,
512 Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
513 Uses = [R1,R5,R6,R7,R8,R9,R10] in {
514 def BRLD : BranchL<0x26, 0x14, 0x000, "brld ">;
515 def BRALD : BranchL<0x26, 0x1C, 0x000, "brald ">;
518 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
519 hasCtrlDep=1, rd=0x10, Form=FCRI in {
520 def RTSD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
521 "rtsd $target, $imm",
526 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
527 hasCtrlDep=1, rd=0x11, Form=FCRI in {
528 def RTID : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
529 "rtid $target, $imm",
534 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
535 hasCtrlDep=1, rd=0x12, Form=FCRI in {
536 def RTBD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
537 "rtbd $target, $imm",
542 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
543 hasCtrlDep=1, rd=0x14, Form=FCRI in {
544 def RTED : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
545 "rted $target, $imm",
550 //===----------------------------------------------------------------------===//
551 // MBlaze misc instructions
552 //===----------------------------------------------------------------------===//
554 let neverHasSideEffects = 1 in {
555 def NOP : MBlazeInst< 0x20, FC, (outs), (ins), "nop ", [], IIAlu>;
558 let usesCustomInserter = 1 in {
559 def Select_CC : MBlazePseudo<(outs GPR:$dst),
560 (ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC), // F T reversed
561 "; SELECT_CC PSEUDO!",
564 def ShiftL : MBlazePseudo<(outs GPR:$dst),
565 (ins GPR:$L, GPR:$R),
569 def ShiftRA : MBlazePseudo<(outs GPR:$dst),
570 (ins GPR:$L, GPR:$R),
574 def ShiftRL : MBlazePseudo<(outs GPR:$dst),
575 (ins GPR:$L, GPR:$R),
582 def SEXT16 : TA<0x24, 0x061, (outs GPR:$dst), (ins GPR:$src),
583 "sext16 $dst, $src", [], IIAlu>;
584 def SEXT8 : TA<0x24, 0x060, (outs GPR:$dst), (ins GPR:$src),
585 "sext8 $dst, $src", [], IIAlu>;
586 def SRL : TA<0x24, 0x041, (outs GPR:$dst), (ins GPR:$src),
587 "srl $dst, $src", [], IIAlu>;
588 def SRA : TA<0x24, 0x001, (outs GPR:$dst), (ins GPR:$src),
589 "sra $dst, $src", [], IIAlu>;
590 def SRC : TA<0x24, 0x021, (outs GPR:$dst), (ins GPR:$src),
591 "src $dst, $src", [], IIAlu>;
594 let isCodeGenOnly=1 in {
595 def ADDIK32 : ArithI32<0x08, "addik ", simm16, immSExt16>;
596 def ORI32 : LogicI32<0x28, "ori ">;
597 def BRLID32 : BranchLI<0x2E, 0x14, "brlid ">;
600 //===----------------------------------------------------------------------===//
601 // Misc. instructions
602 //===----------------------------------------------------------------------===//
603 def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins uimm14:$rg),
604 "mfs $dst, $rg", [], IIAlu>;
606 def MTS : SPC<0x25, 0x3, (outs), (ins uimm14:$dst, GPR:$rg),
607 "mts $dst, $rg", [], IIAlu>;
609 def MSRSET : MSR<0x25, 0x20, (outs GPR:$dst), (ins uimm15:$set),
610 "msrset $dst, $set", [], IIAlu>;
612 def MSRCLR : MSR<0x25, 0x22, (outs GPR:$dst), (ins uimm15:$clr),
613 "msrclr $dst, $clr", [], IIAlu>;
615 let rd=0x0, Form=FCRR in {
616 def WDC : TA<0x24, 0x64, (outs), (ins GPR:$a, GPR:$b),
617 "wdc $a, $b", [], IIAlu>;
618 def WDCF : TA<0x24, 0x74, (outs), (ins GPR:$a, GPR:$b),
619 "wdc.flush $a, $b", [], IIAlu>;
620 def WDCC : TA<0x24, 0x66, (outs), (ins GPR:$a, GPR:$b),
621 "wdc.clear $a, $b", [], IIAlu>;
622 def WIC : TA<0x24, 0x68, (outs), (ins GPR:$a, GPR:$b),
623 "wic $a, $b", [], IIAlu>;
626 def BRK : BranchL<0x26, 0x0C, 0x000, "brk ">;
627 def BRKI : BranchLI<0x2E, 0x0C, "brki ">;
629 def IMM : MBlazeInst<0x2C, FCCI, (outs), (ins simm16:$imm),
630 "imm $imm", [], IIAlu>;
632 //===----------------------------------------------------------------------===//
633 // Arbitrary patterns that map to one or more instructions
634 //===----------------------------------------------------------------------===//
637 def : Pat<(i32 0), (ADD (i32 R0), (i32 R0))>;
638 def : Pat<(i32 immSExt16:$imm), (ADDIK (i32 R0), imm:$imm)>;
639 def : Pat<(i32 immZExt16:$imm), (ORI (i32 R0), imm:$imm)>;
641 // Arbitrary immediates
642 def : Pat<(i32 imm:$imm), (ADDIK (i32 R0), imm:$imm)>;
644 // In register sign extension
645 def : Pat<(sext_inreg GPR:$src, i16), (SEXT16 GPR:$src)>;
646 def : Pat<(sext_inreg GPR:$src, i8), (SEXT8 GPR:$src)>;
649 def : Pat<(MBlazeJmpLink (i32 tglobaladdr:$dst)),
650 (BRLID (i32 R15), tglobaladdr:$dst)>;
652 def : Pat<(MBlazeJmpLink (i32 texternalsym:$dst)),
653 (BRLID (i32 R15), texternalsym:$dst)>;
655 def : Pat<(MBlazeJmpLink GPR:$dst),
656 (BRALD (i32 R15), GPR:$dst)>;
658 // Shift Instructions
659 def : Pat<(shl GPR:$L, GPR:$R), (ShiftL GPR:$L, GPR:$R)>;
660 def : Pat<(sra GPR:$L, GPR:$R), (ShiftRA GPR:$L, GPR:$R)>;
661 def : Pat<(srl GPR:$L, GPR:$R), (ShiftRL GPR:$L, GPR:$R)>;
664 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ),
665 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
666 (CMP GPR:$R, GPR:$L), 1)>;
667 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETNE),
668 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
669 (CMP GPR:$R, GPR:$L), 2)>;
670 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGT),
671 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
672 (CMP GPR:$R, GPR:$L), 3)>;
673 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLT),
674 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
675 (CMP GPR:$R, GPR:$L), 4)>;
676 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGE),
677 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
678 (CMP GPR:$R, GPR:$L), 5)>;
679 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLE),
680 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
681 (CMP GPR:$R, GPR:$L), 6)>;
682 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT),
683 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
684 (CMPU GPR:$R, GPR:$L), 3)>;
685 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULT),
686 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
687 (CMPU GPR:$R, GPR:$L), 4)>;
688 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE),
689 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
690 (CMPU GPR:$R, GPR:$L), 5)>;
691 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULE),
692 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
693 (CMPU GPR:$R, GPR:$L), 6)>;
696 def : Pat<(select (i32 GPR:$C), (i32 GPR:$T), (i32 GPR:$F)),
697 (Select_CC GPR:$T, GPR:$F, GPR:$C, 2)>;
700 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
701 (i32 GPR:$T), (i32 GPR:$F), SETEQ),
702 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 1)>;
703 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
704 (i32 GPR:$T), (i32 GPR:$F), SETNE),
705 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 2)>;
706 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
707 (i32 GPR:$T), (i32 GPR:$F), SETGT),
708 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 3)>;
709 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
710 (i32 GPR:$T), (i32 GPR:$F), SETLT),
711 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 4)>;
712 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
713 (i32 GPR:$T), (i32 GPR:$F), SETGE),
714 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 5)>;
715 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
716 (i32 GPR:$T), (i32 GPR:$F), SETLE),
717 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 6)>;
718 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
719 (i32 GPR:$T), (i32 GPR:$F), SETUGT),
720 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, GPR:$L), 3)>;
721 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
722 (i32 GPR:$T), (i32 GPR:$F), SETULT),
723 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, GPR:$L), 4)>;
724 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
725 (i32 GPR:$T), (i32 GPR:$F), SETUGE),
726 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, GPR:$L), 5)>;
727 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
728 (i32 GPR:$T), (i32 GPR:$F), SETULE),
729 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, GPR:$L), 6)>;
732 def : Pat<(MBlazeRet GPR:$target), (RTSD GPR:$target, 0x8)>;
733 def : Pat<(MBlazeIRet GPR:$target), (RTID GPR:$target, 0x0)>;
736 def : Pat<(br bb:$T), (BRID bb:$T)>;
737 def : Pat<(brind GPR:$T), (BRAD GPR:$T)>;
739 // BRCOND instructions
740 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ), bb:$T),
741 (BEQID (CMP GPR:$R, GPR:$L), bb:$T)>;
742 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETNE), bb:$T),
743 (BNEID (CMP GPR:$R, GPR:$L), bb:$T)>;
744 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETGT), bb:$T),
745 (BGTID (CMP GPR:$R, GPR:$L), bb:$T)>;
746 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETLT), bb:$T),
747 (BLTID (CMP GPR:$R, GPR:$L), bb:$T)>;
748 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETGE), bb:$T),
749 (BGEID (CMP GPR:$R, GPR:$L), bb:$T)>;
750 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETLE), bb:$T),
751 (BLEID (CMP GPR:$R, GPR:$L), bb:$T)>;
752 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT), bb:$T),
753 (BGTID (CMPU GPR:$R, GPR:$L), bb:$T)>;
754 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETULT), bb:$T),
755 (BLTID (CMPU GPR:$R, GPR:$L), bb:$T)>;
756 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE), bb:$T),
757 (BGEID (CMPU GPR:$R, GPR:$L), bb:$T)>;
758 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETULE), bb:$T),
759 (BLEID (CMPU GPR:$R, GPR:$L), bb:$T)>;
760 def : Pat<(brcond (i32 GPR:$C), bb:$T),
761 (BNEID GPR:$C, bb:$T)>;
763 // Jump tables, global addresses, and constant pools
764 def : Pat<(MBWrapper tglobaladdr:$in), (ORI (i32 R0), tglobaladdr:$in)>;
765 def : Pat<(MBWrapper tjumptable:$in), (ORI (i32 R0), tjumptable:$in)>;
766 def : Pat<(MBWrapper tconstpool:$in), (ORI (i32 R0), tconstpool:$in)>;
769 def : Pat<(and (i32 GPR:$lh), (not (i32 GPR:$rh))),(ANDN GPR:$lh, GPR:$rh)>;
771 // Arithmetic with immediates
772 def : Pat<(add (i32 GPR:$in), imm:$imm),(ADDIK GPR:$in, imm:$imm)>;
773 def : Pat<(or (i32 GPR:$in), imm:$imm),(ORI GPR:$in, imm:$imm)>;
774 def : Pat<(xor (i32 GPR:$in), imm:$imm),(XORI GPR:$in, imm:$imm)>;
776 // Convert any extend loads into zero extend loads
777 def : Pat<(extloadi8 iaddr:$src), (i32 (LBUI iaddr:$src))>;
778 def : Pat<(extloadi16 iaddr:$src), (i32 (LHUI iaddr:$src))>;
779 def : Pat<(extloadi8 xaddr:$src), (i32 (LBU xaddr:$src))>;
780 def : Pat<(extloadi16 xaddr:$src), (i32 (LHU xaddr:$src))>;
782 // 32-bit load and store
783 def : Pat<(store (i32 GPR:$dst), xaddr:$addr), (SW GPR:$dst, xaddr:$addr)>;
784 def : Pat<(load xaddr:$addr), (i32 (LW xaddr:$addr))>;
786 // 16-bit load and store
787 def : Pat<(truncstorei16 (i32 GPR:$dst), xaddr:$addr), (SH GPR:$dst, xaddr:$addr)>;
788 def : Pat<(zextloadi16 xaddr:$addr), (i32 (LHU xaddr:$addr))>;
790 // 8-bit load and store
791 def : Pat<(truncstorei8 (i32 GPR:$dst), xaddr:$addr), (SB GPR:$dst, xaddr:$addr)>;
792 def : Pat<(zextloadi8 xaddr:$addr), (i32 (LBU xaddr:$addr))>;
795 def : Pat<(store (i32 0), iaddr:$dst), (SWI (i32 R0), iaddr:$dst)>;
797 //===----------------------------------------------------------------------===//
798 // Floating Point Support
799 //===----------------------------------------------------------------------===//
800 include "MBlazeInstrFSL.td"
801 include "MBlazeInstrFPU.td"