1 //===- MBlazeInstrInfo.td - MBlaze Instruction defs --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
13 include "MBlazeInstrFormats.td"
15 //===----------------------------------------------------------------------===//
16 // MBlaze type profiles
17 //===----------------------------------------------------------------------===//
19 // def SDTMBlazeSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>]>;
20 def SDT_MBlazeRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
21 def SDT_MBlazeJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
22 def SDT_MBCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
23 def SDT_MBCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
25 //===----------------------------------------------------------------------===//
26 // MBlaze specific nodes
27 //===----------------------------------------------------------------------===//
29 def MBlazeRet : SDNode<"MBlazeISD::Ret", SDT_MBlazeRet,
30 [SDNPHasChain, SDNPOptInFlag]>;
32 def MBlazeJmpLink : SDNode<"MBlazeISD::JmpLink",SDT_MBlazeJmpLink,
33 [SDNPHasChain,SDNPOptInFlag,SDNPOutFlag]>;
35 def MBWrapper : SDNode<"MBlazeISD::Wrap", SDTIntUnaryOp>;
37 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MBCallSeqStart,
38 [SDNPHasChain, SDNPOutFlag]>;
40 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MBCallSeqEnd,
41 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
43 //===----------------------------------------------------------------------===//
44 // MBlaze Instruction Predicate Definitions.
45 //===----------------------------------------------------------------------===//
46 def HasPipe3 : Predicate<"Subtarget.hasPipe3()">;
47 def HasBarrel : Predicate<"Subtarget.hasBarrel()">;
48 def NoBarrel : Predicate<"!Subtarget.hasBarrel()">;
49 def HasDiv : Predicate<"Subtarget.hasDiv()">;
50 def HasMul : Predicate<"Subtarget.hasMul()">;
51 def HasFSL : Predicate<"Subtarget.hasFSL()">;
52 def HasEFSL : Predicate<"Subtarget.hasEFSL()">;
53 def HasMSRSet : Predicate<"Subtarget.hasMSRSet()">;
54 def HasException : Predicate<"Subtarget.hasException()">;
55 def HasPatCmp : Predicate<"Subtarget.hasPatCmp()">;
56 def HasFPU : Predicate<"Subtarget.hasFPU()">;
57 def HasESR : Predicate<"Subtarget.hasESR()">;
58 def HasPVR : Predicate<"Subtarget.hasPVR()">;
59 def HasMul64 : Predicate<"Subtarget.hasMul64()">;
60 def HasSqrt : Predicate<"Subtarget.hasSqrt()">;
61 def HasMMU : Predicate<"Subtarget.hasMMU()">;
63 //===----------------------------------------------------------------------===//
64 // MBlaze Operand, Complex Patterns and Transformations Definitions.
65 //===----------------------------------------------------------------------===//
67 def MBlazeMemAsmOperand : AsmOperandClass {
69 let SuperClasses = [];
72 def MBlazeFslAsmOperand : AsmOperandClass {
74 let SuperClasses = [];
77 // Instruction operand types
78 def brtarget : Operand<OtherVT>;
79 def calltarget : Operand<i32>;
80 def simm16 : Operand<i32>;
81 def uimm5 : Operand<i32>;
82 def fimm : Operand<f32>;
85 def uimm16 : Operand<i32> {
86 let PrintMethod = "printUnsignedImm";
90 def fslimm : Operand<i32> {
91 let PrintMethod = "printFSLImm";
92 let ParserMatchClass = MBlazeFslAsmOperand;
96 def memri : Operand<i32> {
97 let PrintMethod = "printMemOperand";
98 let MIOperandInfo = (ops simm16, GPR);
99 let ParserMatchClass = MBlazeMemAsmOperand;
102 def memrr : Operand<i32> {
103 let PrintMethod = "printMemOperand";
104 let MIOperandInfo = (ops GPR, GPR);
105 let ParserMatchClass = MBlazeMemAsmOperand;
108 // Node immediate fits as 16-bit sign extended on target immediate.
109 def immSExt16 : PatLeaf<(imm), [{
110 return (N->getZExtValue() >> 16) == 0;
113 // Node immediate fits as 16-bit zero extended on target immediate.
114 // The LO16 param means that only the lower 16 bits of the node
115 // immediate are caught.
117 def immZExt16 : PatLeaf<(imm), [{
118 return (N->getZExtValue() >> 16) == 0;
121 // FSL immediate field must fit in 4 bits.
122 def immZExt4 : PatLeaf<(imm), [{
123 return N->getZExtValue() == ((N->getZExtValue()) & 0xf) ;
126 // shamt field must fit in 5 bits.
127 def immZExt5 : PatLeaf<(imm), [{
128 return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
131 // MBlaze Address Mode. SDNode frameindex could possibily be a match
132 // since load and store instructions from stack used it.
133 def iaddr : ComplexPattern<i32, 2, "SelectAddrRegImm", [frameindex], []>;
134 def xaddr : ComplexPattern<i32, 2, "SelectAddrRegReg", [], []>;
136 //===----------------------------------------------------------------------===//
137 // Pseudo instructions
138 //===----------------------------------------------------------------------===//
140 // As stack alignment is always done with addiu, we need a 16-bit immediate
141 let Defs = [R1], Uses = [R1] in {
142 def ADJCALLSTACKDOWN : MBlazePseudo<(outs), (ins simm16:$amt),
143 "#ADJCALLSTACKDOWN $amt",
144 [(callseq_start timm:$amt)]>;
145 def ADJCALLSTACKUP : MBlazePseudo<(outs),
146 (ins uimm16:$amt1, simm16:$amt2),
147 "#ADJCALLSTACKUP $amt1",
148 [(callseq_end timm:$amt1, timm:$amt2)]>;
151 //===----------------------------------------------------------------------===//
152 // Instructions specific format
153 //===----------------------------------------------------------------------===//
155 //===----------------------------------------------------------------------===//
156 // Arithmetic Instructions
157 //===----------------------------------------------------------------------===//
158 class Arith<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
159 InstrItinClass itin> :
160 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
161 !strconcat(instr_asm, " $dst, $b, $c"),
162 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
164 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
165 Operand Od, PatLeaf imm_type> :
166 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
167 !strconcat(instr_asm, " $dst, $b, $c"),
168 [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIAlu>;
170 class ArithR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
171 InstrItinClass itin> :
172 TA<op, flags, (outs GPR:$dst), (ins GPR:$c, GPR:$b),
173 !strconcat(instr_asm, " $dst, $c, $b"),
174 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
176 class ArithRI<bits<6> op, string instr_asm, SDNode OpNode,
177 Operand Od, PatLeaf imm_type> :
178 TBR<op, (outs GPR:$dst), (ins Od:$b, GPR:$c),
179 !strconcat(instr_asm, " $dst, $c, $b"),
180 [(set GPR:$dst, (OpNode imm_type:$b, GPR:$c))], IIAlu>;
182 class ArithN<bits<6> op, bits<11> flags, string instr_asm,
183 InstrItinClass itin> :
184 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
185 !strconcat(instr_asm, " $dst, $b, $c"),
188 class ArithNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
189 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
190 !strconcat(instr_asm, " $dst, $b, $c"),
193 class ArithRN<bits<6> op, bits<11> flags, string instr_asm,
194 InstrItinClass itin> :
195 TA<op, flags, (outs GPR:$dst), (ins GPR:$c, GPR:$b),
196 !strconcat(instr_asm, " $dst, $b, $c"),
199 class ArithRNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
200 TB<op, (outs GPR:$dst), (ins Od:$c, GPR:$b),
201 !strconcat(instr_asm, " $dst, $b, $c"),
204 //===----------------------------------------------------------------------===//
205 // Misc Arithmetic Instructions
206 //===----------------------------------------------------------------------===//
208 class Logic<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode> :
209 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
210 !strconcat(instr_asm, " $dst, $b, $c"),
211 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], IIAlu>;
213 class LogicI<bits<6> op, string instr_asm, SDNode OpNode> :
214 TB<op, (outs GPR:$dst), (ins GPR:$b, uimm16:$c),
215 !strconcat(instr_asm, " $dst, $b, $c"),
216 [(set GPR:$dst, (OpNode GPR:$b, immZExt16:$c))],
219 class PatCmp<bits<6> op, bits<11> flags, string instr_asm> :
220 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
221 !strconcat(instr_asm, " $dst, $b, $c"),
224 //===----------------------------------------------------------------------===//
225 // Memory Access Instructions
226 //===----------------------------------------------------------------------===//
227 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode> :
228 TA<op, 0x000, (outs GPR:$dst), (ins memrr:$addr),
229 !strconcat(instr_asm, " $dst, $addr"),
230 [(set (i32 GPR:$dst), (OpNode xaddr:$addr))], IILoad>;
232 class LoadW<bits<6> op, bits<11> flags, string instr_asm> :
233 TA<op, flags, (outs GPR:$dst), (ins memrr:$addr),
234 !strconcat(instr_asm, " $dst, $addr"),
237 class LoadMI<bits<6> op, string instr_asm, PatFrag OpNode> :
238 TBR<op, (outs GPR:$dst), (ins memri:$addr),
239 !strconcat(instr_asm, " $dst, $addr"),
240 [(set (i32 GPR:$dst), (OpNode iaddr:$addr))], IILoad>;
242 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode> :
243 TA<op, 0x000, (outs), (ins GPR:$dst, memrr:$addr),
244 !strconcat(instr_asm, " $dst, $addr"),
245 [(OpNode (i32 GPR:$dst), xaddr:$addr)], IIStore>;
247 class StoreW<bits<6> op, bits<11> flags, string instr_asm> :
248 TA<op, flags, (outs), (ins GPR:$dst, memrr:$addr),
249 !strconcat(instr_asm, " $dst, $addr"),
252 class StoreMI<bits<6> op, string instr_asm, PatFrag OpNode> :
253 TBR<op, (outs), (ins GPR:$dst, memri:$addr),
254 !strconcat(instr_asm, " $dst, $addr"),
255 [(OpNode (i32 GPR:$dst), iaddr:$addr)], IIStore>;
257 //===----------------------------------------------------------------------===//
258 // Branch Instructions
259 //===----------------------------------------------------------------------===//
260 class Branch<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
261 TA<op, flags, (outs), (ins GPR:$target),
262 !strconcat(instr_asm, " $target"),
269 class BranchI<bits<6> op, bits<5> br, string instr_asm> :
270 TB<op, (outs), (ins brtarget:$target),
271 !strconcat(instr_asm, " $target"),
278 //===----------------------------------------------------------------------===//
279 // Branch and Link Instructions
280 //===----------------------------------------------------------------------===//
281 class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
282 TA<op, flags, (outs), (ins GPR:$link, GPR:$target),
283 !strconcat(instr_asm, " $link, $target"),
289 class BranchLI<bits<6> op, bits<5> br, string instr_asm> :
290 TB<op, (outs), (ins GPR:$link, calltarget:$target),
291 !strconcat(instr_asm, " $link, $target"),
297 //===----------------------------------------------------------------------===//
298 // Conditional Branch Instructions
299 //===----------------------------------------------------------------------===//
300 class BranchC<bits<6> op, bits<5> br, bits<11> flags, string instr_asm,
302 TA<op, flags, (outs),
303 (ins GPR:$a, GPR:$b, brtarget:$offset),
304 !strconcat(instr_asm, " $a, $b, $offset"),
310 class BranchCI<bits<6> op, bits<5> br, string instr_asm, PatFrag cond_op> :
311 TB<op, (outs), (ins GPR:$a, brtarget:$offset),
312 !strconcat(instr_asm, " $a, $offset"),
318 //===----------------------------------------------------------------------===//
319 // MBlaze arithmetic instructions
320 //===----------------------------------------------------------------------===//
322 let isCommutable = 1, isAsCheapAsAMove = 1 in {
323 def ADD : Arith<0x00, 0x000, "add ", add, IIAlu>;
324 def ADDC : Arith<0x02, 0x000, "addc ", adde, IIAlu>;
325 def ADDK : Arith<0x04, 0x000, "addk ", addc, IIAlu>;
326 def ADDKC : ArithN<0x06, 0x000, "addkc ", IIAlu>;
327 def AND : Logic<0x21, 0x000, "and ", and>;
328 def OR : Logic<0x20, 0x000, "or ", or>;
329 def XOR : Logic<0x22, 0x000, "xor ", xor>;
330 def PCMPBF : PatCmp<0x20, 0x400, "pcmpbf ">;
331 def PCMPEQ : PatCmp<0x23, 0x400, "pcmpeq ">;
332 def PCMPNE : PatCmp<0x22, 0x400, "pcmpne ">;
335 let isAsCheapAsAMove = 1 in {
336 def ANDN : ArithN<0x23, 0x000, "andn ", IIAlu>;
337 def CMP : ArithN<0x05, 0x001, "cmp ", IIAlu>;
338 def CMPU : ArithN<0x05, 0x003, "cmpu ", IIAlu>;
339 def RSUB : ArithR<0x01, 0x000, "rsub ", sub, IIAlu>;
340 def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIAlu>;
341 def RSUBK : ArithR<0x05, 0x000, "rsubk ", subc, IIAlu>;
342 def RSUBKC : ArithRN<0x07, 0x000, "rsubkc ", IIAlu>;
345 let isCommutable = 1, Predicates=[HasMul] in {
346 def MUL : Arith<0x10, 0x000, "mul ", mul, IIAlu>;
349 let isCommutable = 1, Predicates=[HasMul,HasMul64] in {
350 def MULH : Arith<0x10, 0x001, "mulh ", mulhs, IIAlu>;
351 def MULHU : Arith<0x10, 0x003, "mulhu ", mulhu, IIAlu>;
354 let Predicates=[HasMul,HasMul64] in {
355 def MULHSU : ArithN<0x10, 0x002, "mulhsu ", IIAlu>;
358 let Predicates=[HasBarrel] in {
359 def BSRL : Arith<0x11, 0x000, "bsrl ", srl, IIAlu>;
360 def BSRA : Arith<0x11, 0x200, "bsra ", sra, IIAlu>;
361 def BSLL : Arith<0x11, 0x400, "bsll ", shl, IIAlu>;
362 def BSRLI : ArithI<0x11, "bsrli ", srl, uimm5, immZExt5>;
363 def BSRAI : ArithI<0x11, "bsrai ", sra, uimm5, immZExt5>;
364 def BSLLI : ArithI<0x11, "bslli ", shl, uimm5, immZExt5>;
367 let Predicates=[HasDiv] in {
368 def IDIV : Arith<0x12, 0x000, "idiv ", sdiv, IIAlu>;
369 def IDIVU : Arith<0x12, 0x002, "idivu ", udiv, IIAlu>;
372 //===----------------------------------------------------------------------===//
373 // MBlaze immediate mode arithmetic instructions
374 //===----------------------------------------------------------------------===//
376 let isAsCheapAsAMove = 1 in {
377 def ADDI : ArithI<0x08, "addi ", add, simm16, immSExt16>;
378 def ADDIC : ArithNI<0x0A, "addic ", simm16, immSExt16>;
379 def ADDIK : ArithNI<0x0C, "addik ", simm16, immSExt16>;
380 def ADDIKC : ArithI<0x0E, "addikc ", addc, simm16, immSExt16>;
381 def RSUBI : ArithRI<0x09, "rsubi ", sub, simm16, immSExt16>;
382 def RSUBIC : ArithRNI<0x0B, "rsubi ", simm16, immSExt16>;
383 def RSUBIK : ArithRNI<0x0E, "rsubic ", simm16, immSExt16>;
384 def RSUBIKC : ArithRI<0x0F, "rsubikc", subc, simm16, immSExt16>;
385 def ANDNI : ArithNI<0x2B, "andni ", uimm16, immZExt16>;
386 def ANDI : LogicI<0x29, "andi ", and>;
387 def ORI : LogicI<0x28, "ori ", or>;
388 def XORI : LogicI<0x2A, "xori ", xor>;
391 let Predicates=[HasMul] in {
392 def MULI : ArithI<0x18, "muli ", mul, simm16, immSExt16>;
395 //===----------------------------------------------------------------------===//
396 // MBlaze memory access instructions
397 //===----------------------------------------------------------------------===//
399 let canFoldAsLoad = 1, isReMaterializable = 1 in {
400 def LBU : LoadM<0x30, "lbu ", zextloadi8>;
401 def LHU : LoadM<0x31, "lhu ", zextloadi16>;
403 def LW : LoadW<0x32, 0x0, "lw ">;
404 def LWR : LoadW<0x32, 0x2, "lwr ">;
405 def LWX : LoadW<0x32, 0x4, "lwx ">;
407 def LBUI : LoadMI<0x38, "lbui ", zextloadi8>;
408 def LHUI : LoadMI<0x39, "lhui ", zextloadi16>;
409 def LWI : LoadMI<0x3A, "lwi ", load>;
412 def SB : StoreM<0x34, "sb ", truncstorei8>;
413 def SH : StoreM<0x35, "sh ", truncstorei16>;
415 def SW : StoreW<0x36, 0x0, "sw ">;
416 def SWR : StoreW<0x36, 0x2, "swr ">;
417 def SWX : StoreW<0x36, 0x4, "swx ">;
419 def SBI : StoreMI<0x3C, "sbi ", truncstorei8>;
420 def SHI : StoreMI<0x3D, "shi ", truncstorei16>;
421 def SWI : StoreMI<0x3E, "swi ", store>;
423 //===----------------------------------------------------------------------===//
424 // MBlaze branch instructions
425 //===----------------------------------------------------------------------===//
427 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
428 def BRI : BranchI<0x2E, 0x00, "bri ">;
429 def BRAI : BranchI<0x2E, 0x08, "brai ">;
432 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
433 def BEQI : BranchCI<0x2F, 0x00, "beqi ", seteq>;
434 def BNEI : BranchCI<0x2F, 0x01, "bnei ", setne>;
435 def BLTI : BranchCI<0x2F, 0x02, "blti ", setlt>;
436 def BLEI : BranchCI<0x2F, 0x03, "blei ", setle>;
437 def BGTI : BranchCI<0x2F, 0x04, "bgti ", setgt>;
438 def BGEI : BranchCI<0x2F, 0x05, "bgei ", setge>;
441 let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1,
443 def BR : Branch<0x26, 0x00, 0x000, "br ">;
444 def BRA : Branch<0x26, 0x08, 0x000, "bra ">;
447 let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
448 def BEQ : BranchC<0x27, 0x00, 0x000, "beq ", seteq>;
449 def BNE : BranchC<0x27, 0x01, 0x000, "bne ", setne>;
450 def BLT : BranchC<0x27, 0x02, 0x000, "blt ", setlt>;
451 def BLE : BranchC<0x27, 0x03, 0x000, "ble ", setle>;
452 def BGT : BranchC<0x27, 0x04, 0x000, "bgt ", setgt>;
453 def BGE : BranchC<0x27, 0x05, 0x000, "bge ", setge>;
456 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1,
458 def BRID : BranchI<0x2E, 0x10, "brid ">;
459 def BRAID : BranchI<0x2E, 0x18, "braid ">;
462 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1 in {
463 def BEQID : BranchCI<0x2F, 0x10, "beqid ", seteq>;
464 def BNEID : BranchCI<0x2F, 0x11, "bneid ", setne>;
465 def BLTID : BranchCI<0x2F, 0x12, "bltid ", setlt>;
466 def BLEID : BranchCI<0x2F, 0x13, "bleid ", setle>;
467 def BGTID : BranchCI<0x2F, 0x14, "bgtid ", setgt>;
468 def BGEID : BranchCI<0x2F, 0x15, "bgeid ", setge>;
471 let isBranch = 1, isIndirectBranch = 1, isTerminator = 1,
472 hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1 in {
473 def BRD : Branch<0x26, 0x10, 0x000, "brd ">;
474 def BRAD : Branch<0x26, 0x18, 0x000, "brad ">;
477 let isBranch = 1, isIndirectBranch = 1, isTerminator = 1,
478 hasDelaySlot = 1, hasCtrlDep = 1 in {
479 def BEQD : BranchC<0x27, 0x10, 0x000, "beqd ", seteq>;
480 def BNED : BranchC<0x27, 0x11, 0x000, "bned ", setne>;
481 def BLTD : BranchC<0x27, 0x12, 0x000, "bltd ", setlt>;
482 def BLED : BranchC<0x27, 0x13, 0x000, "bled ", setle>;
483 def BGTD : BranchC<0x27, 0x14, 0x000, "bgtd ", setgt>;
484 def BGED : BranchC<0x27, 0x15, 0x000, "bged ", setge>;
487 let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1,
488 Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
489 Uses = [R1,R5,R6,R7,R8,R9,R10] in {
490 def BRLID : BranchLI<0x2E, 0x14, "brlid ">;
491 def BRALID : BranchLI<0x2E, 0x1C, "bralid ">;
494 let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isIndirectBranch = 1,
496 Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
497 Uses = [R1,R5,R6,R7,R8,R9,R10] in {
498 def BRLD : BranchL<0x26, 0x14, 0x000, "brld ">;
499 def BRALD : BranchL<0x26, 0x1C, 0x000, "brald ">;
502 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
503 hasCtrlDep=1, rd=0x10, Form=FCRI in {
504 def RTSD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
505 "rtsd $target, $imm",
510 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
511 hasCtrlDep=1, rd=0x11, Form=FCRI in {
512 def RTID : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
513 "rtid $target, $imm",
518 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
519 hasCtrlDep=1, rd=0x12, Form=FCRI in {
520 def RTBD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
521 "rtbd $target, $imm",
526 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
527 hasCtrlDep=1, rd=0x14, Form=FCRI in {
528 def RTED : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
529 "rted $target, $imm",
534 //===----------------------------------------------------------------------===//
535 // MBlaze misc instructions
536 //===----------------------------------------------------------------------===//
538 let neverHasSideEffects = 1 in {
539 def NOP : MBlazeInst< 0x20, FC, (outs), (ins), "nop ", [], IIAlu>;
542 let usesCustomInserter = 1 in {
543 def Select_CC : MBlazePseudo<(outs GPR:$dst),
544 (ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC),
545 "; SELECT_CC PSEUDO!",
548 def ShiftL : MBlazePseudo<(outs GPR:$dst),
549 (ins GPR:$L, GPR:$R),
553 def ShiftRA : MBlazePseudo<(outs GPR:$dst),
554 (ins GPR:$L, GPR:$R),
558 def ShiftRL : MBlazePseudo<(outs GPR:$dst),
559 (ins GPR:$L, GPR:$R),
566 def SEXT16 : TA<0x24, 0x061, (outs GPR:$dst), (ins GPR:$src),
567 "sext16 $dst, $src", [], IIAlu>;
568 def SEXT8 : TA<0x24, 0x060, (outs GPR:$dst), (ins GPR:$src),
569 "sext8 $dst, $src", [], IIAlu>;
570 def SRL : TA<0x24, 0x041, (outs GPR:$dst), (ins GPR:$src),
571 "srl $dst, $src", [], IIAlu>;
572 def SRA : TA<0x24, 0x001, (outs GPR:$dst), (ins GPR:$src),
573 "sra $dst, $src", [], IIAlu>;
574 def SRC : TA<0x24, 0x021, (outs GPR:$dst), (ins GPR:$src),
575 "src $dst, $src", [], IIAlu>;
578 let opcode=0x08, isCodeGenOnly=1 in {
579 def LEA_ADDI : TB<0x08, (outs GPR:$dst), (ins memri:$addr),
580 "addi $dst, ${addr:stackloc}",
581 [(set GPR:$dst, iaddr:$addr)], IIAlu>;
584 //===----------------------------------------------------------------------===//
585 // Misc. instructions
586 //===----------------------------------------------------------------------===//
587 def MFS : MBlazeInst<0x25, FPseudo, (outs), (ins), "mfs", [], IIAlu> {
590 def MTS : MBlazeInst<0x25, FPseudo, (outs), (ins), "mts", [], IIAlu> {
593 def MSRSET : MBlazeInst<0x25, FPseudo, (outs), (ins), "msrset", [], IIAlu> {
596 def MSRCLR : MBlazeInst<0x25, FPseudo, (outs), (ins), "msrclr", [], IIAlu> {
599 let rd=0x0, Form=FCRR in {
600 def WDC : TA<0x24, 0x64, (outs), (ins GPR:$a, GPR:$b),
601 "wdc $a, $b", [], IIAlu>;
602 def WDCF : TA<0x24, 0x74, (outs), (ins GPR:$a, GPR:$b),
603 "wdc.flush $a, $b", [], IIAlu>;
604 def WDCC : TA<0x24, 0x66, (outs), (ins GPR:$a, GPR:$b),
605 "wdc.clear $a, $b", [], IIAlu>;
606 def WIC : TA<0x24, 0x68, (outs), (ins GPR:$a, GPR:$b),
607 "wic $a, $b", [], IIAlu>;
610 def BRK : Branch<0x26, 0x0C, 0x000, "brk ">;
611 def BRKI : BranchI<0x2E, 0x0C, "brki ">;
613 def IMM : MBlazeInst<0x2C, FCCI, (outs), (ins simm16:$imm),
614 "imm $imm", [], IIAlu>;
616 //===----------------------------------------------------------------------===//
617 // Arbitrary patterns that map to one or more instructions
618 //===----------------------------------------------------------------------===//
621 def : Pat<(i32 0), (ADD (i32 R0), (i32 R0))>;
622 def : Pat<(i32 immSExt16:$imm), (ADDI (i32 R0), imm:$imm)>;
623 def : Pat<(i32 immZExt16:$imm), (ORI (i32 R0), imm:$imm)>;
625 // Arbitrary immediates
626 def : Pat<(i32 imm:$imm), (ADDI (i32 R0), imm:$imm)>;
628 // In register sign extension
629 def : Pat<(sext_inreg GPR:$src, i16), (SEXT16 GPR:$src)>;
630 def : Pat<(sext_inreg GPR:$src, i8), (SEXT8 GPR:$src)>;
633 def : Pat<(MBlazeJmpLink (i32 tglobaladdr:$dst)),
634 (BRLID (i32 R15), tglobaladdr:$dst)>;
636 def : Pat<(MBlazeJmpLink (i32 texternalsym:$dst)),
637 (BRLID (i32 R15), texternalsym:$dst)>;
639 def : Pat<(MBlazeJmpLink GPR:$dst),
640 (BRLD (i32 R15), GPR:$dst)>;
642 // Shift Instructions
643 def : Pat<(shl GPR:$L, GPR:$R), (ShiftL GPR:$L, GPR:$R)>;
644 def : Pat<(sra GPR:$L, GPR:$R), (ShiftRA GPR:$L, GPR:$R)>;
645 def : Pat<(srl GPR:$L, GPR:$R), (ShiftRL GPR:$L, GPR:$R)>;
648 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ),
649 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
650 (CMP GPR:$L, GPR:$R), 1)>;
651 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETNE),
652 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
653 (CMP GPR:$L, GPR:$R), 2)>;
654 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGT),
655 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
656 (CMP GPR:$L, GPR:$R), 3)>;
657 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLT),
658 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
659 (CMP GPR:$L, GPR:$R), 4)>;
660 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGE),
661 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
662 (CMP GPR:$L, GPR:$R), 5)>;
663 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLE),
664 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
665 (CMP GPR:$L, GPR:$R), 6)>;
666 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT),
667 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
668 (CMPU GPR:$L, GPR:$R), 3)>;
669 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULT),
670 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
671 (CMPU GPR:$L, GPR:$R), 4)>;
672 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE),
673 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
674 (CMPU GPR:$L, GPR:$R), 5)>;
675 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULE),
676 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
677 (CMPU GPR:$L, GPR:$R), 6)>;
680 def : Pat<(select (i32 GPR:$C), (i32 GPR:$T), (i32 GPR:$F)),
681 (Select_CC GPR:$T, GPR:$F, GPR:$C, 2)>;
684 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
685 (i32 GPR:$T), (i32 GPR:$F), SETEQ),
686 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$L, GPR:$R), 1)>;
687 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
688 (i32 GPR:$T), (i32 GPR:$F), SETNE),
689 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$L, GPR:$R), 2)>;
690 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
691 (i32 GPR:$T), (i32 GPR:$F), SETGT),
692 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$L, GPR:$R), 3)>;
693 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
694 (i32 GPR:$T), (i32 GPR:$F), SETLT),
695 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$L, GPR:$R), 4)>;
696 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
697 (i32 GPR:$T), (i32 GPR:$F), SETGE),
698 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$L, GPR:$R), 5)>;
699 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
700 (i32 GPR:$T), (i32 GPR:$F), SETLE),
701 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$L, GPR:$R), 6)>;
702 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
703 (i32 GPR:$T), (i32 GPR:$F), SETUGT),
704 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$L, GPR:$R), 3)>;
705 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
706 (i32 GPR:$T), (i32 GPR:$F), SETULT),
707 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$L, GPR:$R), 4)>;
708 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
709 (i32 GPR:$T), (i32 GPR:$F), SETUGE),
710 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$L, GPR:$R), 5)>;
711 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
712 (i32 GPR:$T), (i32 GPR:$F), SETULE),
713 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$L, GPR:$R), 6)>;
716 def : Pat<(MBlazeRet GPR:$target), (RTSD GPR:$target, 0x8)>;
719 def : Pat<(br bb:$T), (BRID bb:$T)>;
720 def : Pat<(brind GPR:$T), (BRD GPR:$T)>;
722 // BRCOND instructions
723 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ), bb:$T),
724 (BEQID (CMP GPR:$R, GPR:$L), bb:$T)>;
725 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETNE), bb:$T),
726 (BNEID (CMP GPR:$R, GPR:$L), bb:$T)>;
727 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETGT), bb:$T),
728 (BGTID (CMP GPR:$R, GPR:$L), bb:$T)>;
729 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETLT), bb:$T),
730 (BLTID (CMP GPR:$R, GPR:$L), bb:$T)>;
731 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETGE), bb:$T),
732 (BGEID (CMP GPR:$R, GPR:$L), bb:$T)>;
733 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETLE), bb:$T),
734 (BLEID (CMP GPR:$R, GPR:$L), bb:$T)>;
735 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT), bb:$T),
736 (BGTID (CMPU GPR:$R, GPR:$L), bb:$T)>;
737 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETULT), bb:$T),
738 (BLTID (CMPU GPR:$R, GPR:$L), bb:$T)>;
739 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE), bb:$T),
740 (BGEID (CMPU GPR:$R, GPR:$L), bb:$T)>;
741 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETULE), bb:$T),
742 (BLEID (CMPU GPR:$R, GPR:$L), bb:$T)>;
743 def : Pat<(brcond (i32 GPR:$C), bb:$T),
744 (BNEID GPR:$C, bb:$T)>;
746 // Jump tables, global addresses, and constant pools
747 def : Pat<(MBWrapper tglobaladdr:$in), (ORI (i32 R0), tglobaladdr:$in)>;
748 def : Pat<(MBWrapper tjumptable:$in), (ORI (i32 R0), tjumptable:$in)>;
749 def : Pat<(MBWrapper tconstpool:$in), (ORI (i32 R0), tconstpool:$in)>;
752 def : Pat<(and (i32 GPR:$lh), (not (i32 GPR:$rh))),(ANDN GPR:$lh, GPR:$rh)>;
754 // Arithmetic with immediates
755 def : Pat<(add (i32 GPR:$in), imm:$imm),(ADDI GPR:$in, imm:$imm)>;
756 def : Pat<(or (i32 GPR:$in), imm:$imm),(ORI GPR:$in, imm:$imm)>;
757 def : Pat<(xor (i32 GPR:$in), imm:$imm),(XORI GPR:$in, imm:$imm)>;
759 // Convert any extend loads into zero extend loads
760 def : Pat<(extloadi8 iaddr:$src), (i32 (LBUI iaddr:$src))>;
761 def : Pat<(extloadi16 iaddr:$src), (i32 (LHUI iaddr:$src))>;
762 def : Pat<(extloadi8 xaddr:$src), (i32 (LBU xaddr:$src))>;
763 def : Pat<(extloadi16 xaddr:$src), (i32 (LHU xaddr:$src))>;
765 // 32-bit load and store
766 def : Pat<(store (i32 GPR:$dst), xaddr:$addr), (SW GPR:$dst, xaddr:$addr)>;
767 def : Pat<(load xaddr:$addr), (i32 (LW xaddr:$addr))>;
770 def : Pat<(store (i32 0), iaddr:$dst), (SWI (i32 R0), iaddr:$dst)>;
772 //===----------------------------------------------------------------------===//
773 // Floating Point Support
774 //===----------------------------------------------------------------------===//
775 include "MBlazeInstrFSL.td"
776 include "MBlazeInstrFPU.td"