1 //===- MBlazeInstrInfo.td - MBlaze Instruction defs --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
13 include "MBlazeInstrFormats.td"
15 //===----------------------------------------------------------------------===//
16 // MBlaze type profiles
17 //===----------------------------------------------------------------------===//
19 // def SDTMBlazeSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>]>;
20 def SDT_MBlazeRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
21 def SDT_MBlazeJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
22 def SDT_MBCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
23 def SDT_MBCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
25 //===----------------------------------------------------------------------===//
26 // MBlaze specific nodes
27 //===----------------------------------------------------------------------===//
29 def MBlazeRet : SDNode<"MBlazeISD::Ret", SDT_MBlazeRet,
30 [SDNPHasChain, SDNPOptInFlag]>;
32 def MBlazeJmpLink : SDNode<"MBlazeISD::JmpLink",SDT_MBlazeJmpLink,
33 [SDNPHasChain,SDNPOptInFlag,SDNPOutFlag]>;
35 def MBWrapper : SDNode<"MBlazeISD::Wrap", SDTIntUnaryOp>;
37 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MBCallSeqStart,
38 [SDNPHasChain, SDNPOutFlag]>;
40 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MBCallSeqEnd,
41 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
43 //===----------------------------------------------------------------------===//
44 // MBlaze Instruction Predicate Definitions.
45 //===----------------------------------------------------------------------===//
46 def HasPipe3 : Predicate<"Subtarget.hasPipe3()">;
47 def HasBarrel : Predicate<"Subtarget.hasBarrel()">;
48 def NoBarrel : Predicate<"!Subtarget.hasBarrel()">;
49 def HasDiv : Predicate<"Subtarget.hasDiv()">;
50 def HasMul : Predicate<"Subtarget.hasMul()">;
51 def HasFSL : Predicate<"Subtarget.hasFSL()">;
52 def HasEFSL : Predicate<"Subtarget.hasEFSL()">;
53 def HasMSRSet : Predicate<"Subtarget.hasMSRSet()">;
54 def HasException : Predicate<"Subtarget.hasException()">;
55 def HasPatCmp : Predicate<"Subtarget.hasPatCmp()">;
56 def HasFPU : Predicate<"Subtarget.hasFPU()">;
57 def HasESR : Predicate<"Subtarget.hasESR()">;
58 def HasPVR : Predicate<"Subtarget.hasPVR()">;
59 def HasMul64 : Predicate<"Subtarget.hasMul64()">;
60 def HasSqrt : Predicate<"Subtarget.hasSqrt()">;
61 def HasMMU : Predicate<"Subtarget.hasMMU()">;
63 //===----------------------------------------------------------------------===//
64 // MBlaze Operand, Complex Patterns and Transformations Definitions.
65 //===----------------------------------------------------------------------===//
67 def MBlazeMemAsmOperand : AsmOperandClass {
69 let SuperClasses = [];
72 def MBlazeFslAsmOperand : AsmOperandClass {
74 let SuperClasses = [];
77 // Instruction operand types
78 def brtarget : Operand<OtherVT>;
79 def calltarget : Operand<i32>;
80 def simm16 : Operand<i32>;
81 def uimm5 : Operand<i32>;
82 def uimm14 : Operand<i32>;
83 def uimm15 : Operand<i32>;
84 def fimm : Operand<f32>;
87 def uimm16 : Operand<i32> {
88 let PrintMethod = "printUnsignedImm";
92 def fslimm : Operand<i32> {
93 let PrintMethod = "printFSLImm";
94 let ParserMatchClass = MBlazeFslAsmOperand;
98 def memri : Operand<i32> {
99 let PrintMethod = "printMemOperand";
100 let MIOperandInfo = (ops GPR, simm16);
101 let ParserMatchClass = MBlazeMemAsmOperand;
104 def memrr : Operand<i32> {
105 let PrintMethod = "printMemOperand";
106 let MIOperandInfo = (ops GPR, GPR);
107 let ParserMatchClass = MBlazeMemAsmOperand;
110 // Node immediate fits as 16-bit sign extended on target immediate.
111 def immSExt16 : PatLeaf<(imm), [{
112 return (N->getZExtValue() >> 16) == 0;
115 // Node immediate fits as 16-bit zero extended on target immediate.
116 // The LO16 param means that only the lower 16 bits of the node
117 // immediate are caught.
119 def immZExt16 : PatLeaf<(imm), [{
120 return (N->getZExtValue() >> 16) == 0;
123 // FSL immediate field must fit in 4 bits.
124 def immZExt4 : PatLeaf<(imm), [{
125 return N->getZExtValue() == ((N->getZExtValue()) & 0xf) ;
128 // shamt field must fit in 5 bits.
129 def immZExt5 : PatLeaf<(imm), [{
130 return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
133 // MBlaze Address Mode. SDNode frameindex could possibily be a match
134 // since load and store instructions from stack used it.
135 def iaddr : ComplexPattern<i32, 2, "SelectAddrRegImm", [frameindex], []>;
136 def xaddr : ComplexPattern<i32, 2, "SelectAddrRegReg", [], []>;
138 //===----------------------------------------------------------------------===//
139 // Pseudo instructions
140 //===----------------------------------------------------------------------===//
142 // As stack alignment is always done with addiu, we need a 16-bit immediate
143 let Defs = [R1], Uses = [R1] in {
144 def ADJCALLSTACKDOWN : MBlazePseudo<(outs), (ins simm16:$amt),
145 "#ADJCALLSTACKDOWN $amt",
146 [(callseq_start timm:$amt)]>;
147 def ADJCALLSTACKUP : MBlazePseudo<(outs),
148 (ins uimm16:$amt1, simm16:$amt2),
149 "#ADJCALLSTACKUP $amt1",
150 [(callseq_end timm:$amt1, timm:$amt2)]>;
153 //===----------------------------------------------------------------------===//
154 // Instructions specific format
155 //===----------------------------------------------------------------------===//
157 //===----------------------------------------------------------------------===//
158 // Arithmetic Instructions
159 //===----------------------------------------------------------------------===//
160 class Arith<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
161 InstrItinClass itin> :
162 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
163 !strconcat(instr_asm, " $dst, $b, $c"),
164 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
166 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
167 Operand Od, PatLeaf imm_type> :
168 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
169 !strconcat(instr_asm, " $dst, $b, $c"),
170 [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIAlu>;
172 class ArithI32<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
173 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
174 !strconcat(instr_asm, " $dst, $b, $c"),
177 class ShiftI<bits<6> op, bits<2> flags, string instr_asm, SDNode OpNode,
178 Operand Od, PatLeaf imm_type> :
179 SHT<op, flags, (outs GPR:$dst), (ins GPR:$b, Od:$c),
180 !strconcat(instr_asm, " $dst, $b, $c"),
181 [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIAlu>;
183 class ArithR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
184 InstrItinClass itin> :
185 TAR<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
186 !strconcat(instr_asm, " $dst, $c, $b"),
187 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
189 class ArithRI<bits<6> op, string instr_asm, SDNode OpNode,
190 Operand Od, PatLeaf imm_type> :
191 TBR<op, (outs GPR:$dst), (ins Od:$b, GPR:$c),
192 !strconcat(instr_asm, " $dst, $c, $b"),
193 [(set GPR:$dst, (OpNode imm_type:$b, GPR:$c))], IIAlu>;
195 class ArithN<bits<6> op, bits<11> flags, string instr_asm,
196 InstrItinClass itin> :
197 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
198 !strconcat(instr_asm, " $dst, $b, $c"),
201 class ArithNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
202 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
203 !strconcat(instr_asm, " $dst, $b, $c"),
206 class ArithRN<bits<6> op, bits<11> flags, string instr_asm,
207 InstrItinClass itin> :
208 TAR<op, flags, (outs GPR:$dst), (ins GPR:$c, GPR:$b),
209 !strconcat(instr_asm, " $dst, $b, $c"),
212 class ArithRNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
213 TBR<op, (outs GPR:$dst), (ins Od:$c, GPR:$b),
214 !strconcat(instr_asm, " $dst, $b, $c"),
217 //===----------------------------------------------------------------------===//
218 // Misc Arithmetic Instructions
219 //===----------------------------------------------------------------------===//
221 class Logic<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode> :
222 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
223 !strconcat(instr_asm, " $dst, $b, $c"),
224 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], IIAlu>;
226 class LogicI<bits<6> op, string instr_asm, SDNode OpNode> :
227 TB<op, (outs GPR:$dst), (ins GPR:$b, uimm16:$c),
228 !strconcat(instr_asm, " $dst, $b, $c"),
229 [(set GPR:$dst, (OpNode GPR:$b, immZExt16:$c))],
232 class LogicI32<bits<6> op, string instr_asm> :
233 TB<op, (outs GPR:$dst), (ins GPR:$b, uimm16:$c),
234 !strconcat(instr_asm, " $dst, $b, $c"),
237 class PatCmp<bits<6> op, bits<11> flags, string instr_asm> :
238 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
239 !strconcat(instr_asm, " $dst, $b, $c"),
242 //===----------------------------------------------------------------------===//
243 // Memory Access Instructions
244 //===----------------------------------------------------------------------===//
245 class LoadM<bits<6> op, bits<11> flags, string instr_asm> :
246 TA<op, flags, (outs GPR:$dst), (ins memrr:$addr),
247 !strconcat(instr_asm, " $dst, $addr"),
250 class LoadMI<bits<6> op, string instr_asm, PatFrag OpNode> :
251 TB<op, (outs GPR:$dst), (ins memri:$addr),
252 !strconcat(instr_asm, " $dst, $addr"),
253 [(set (i32 GPR:$dst), (OpNode iaddr:$addr))], IILoad>;
255 class StoreM<bits<6> op, bits<11> flags, string instr_asm> :
256 TA<op, flags, (outs), (ins GPR:$dst, memrr:$addr),
257 !strconcat(instr_asm, " $dst, $addr"),
260 class StoreMI<bits<6> op, string instr_asm, PatFrag OpNode> :
261 TB<op, (outs), (ins GPR:$dst, memri:$addr),
262 !strconcat(instr_asm, " $dst, $addr"),
263 [(OpNode (i32 GPR:$dst), iaddr:$addr)], IIStore>;
265 //===----------------------------------------------------------------------===//
266 // Branch Instructions
267 //===----------------------------------------------------------------------===//
268 class Branch<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
269 TA<op, flags, (outs), (ins GPR:$target),
270 !strconcat(instr_asm, " $target"),
277 class BranchI<bits<6> op, bits<5> br, string instr_asm> :
278 TB<op, (outs), (ins brtarget:$target),
279 !strconcat(instr_asm, " $target"),
286 //===----------------------------------------------------------------------===//
287 // Branch and Link Instructions
288 //===----------------------------------------------------------------------===//
289 class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
290 TA<op, flags, (outs), (ins GPR:$link, GPR:$target),
291 !strconcat(instr_asm, " $link, $target"),
297 class BranchLI<bits<6> op, bits<5> br, string instr_asm> :
298 TB<op, (outs), (ins GPR:$link, calltarget:$target),
299 !strconcat(instr_asm, " $link, $target"),
305 //===----------------------------------------------------------------------===//
306 // Conditional Branch Instructions
307 //===----------------------------------------------------------------------===//
308 class BranchC<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
309 TA<op, flags, (outs),
310 (ins GPR:$a, GPR:$b),
311 !strconcat(instr_asm, " $a, $b"),
317 class BranchCI<bits<6> op, bits<5> br, string instr_asm> :
318 TB<op, (outs), (ins GPR:$a, brtarget:$offset),
319 !strconcat(instr_asm, " $a, $offset"),
325 //===----------------------------------------------------------------------===//
326 // MBlaze arithmetic instructions
327 //===----------------------------------------------------------------------===//
329 let isCommutable = 1, isAsCheapAsAMove = 1 in {
330 def ADD : Arith<0x00, 0x000, "add ", add, IIAlu>;
331 def ADDC : Arith<0x02, 0x000, "addc ", adde, IIAlu>;
332 def ADDK : Arith<0x04, 0x000, "addk ", addc, IIAlu>;
333 def ADDKC : ArithN<0x06, 0x000, "addkc ", IIAlu>;
334 def AND : Logic<0x21, 0x000, "and ", and>;
335 def OR : Logic<0x20, 0x000, "or ", or>;
336 def XOR : Logic<0x22, 0x000, "xor ", xor>;
337 def PCMPBF : PatCmp<0x20, 0x400, "pcmpbf ">;
338 def PCMPEQ : PatCmp<0x22, 0x400, "pcmpeq ">;
339 def PCMPNE : PatCmp<0x23, 0x400, "pcmpne ">;
342 let isAsCheapAsAMove = 1 in {
343 def ANDN : ArithN<0x23, 0x000, "andn ", IIAlu>;
344 def CMP : ArithN<0x05, 0x001, "cmp ", IIAlu>;
345 def CMPU : ArithN<0x05, 0x003, "cmpu ", IIAlu>;
346 def RSUB : ArithR<0x01, 0x000, "rsub ", sub, IIAlu>;
347 def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIAlu>;
348 def RSUBK : ArithR<0x05, 0x000, "rsubk ", subc, IIAlu>;
349 def RSUBKC : ArithRN<0x07, 0x000, "rsubkc ", IIAlu>;
352 let isCommutable = 1, Predicates=[HasMul] in {
353 def MUL : Arith<0x10, 0x000, "mul ", mul, IIAlu>;
356 let isCommutable = 1, Predicates=[HasMul,HasMul64] in {
357 def MULH : Arith<0x10, 0x001, "mulh ", mulhs, IIAlu>;
358 def MULHU : Arith<0x10, 0x003, "mulhu ", mulhu, IIAlu>;
361 let Predicates=[HasMul,HasMul64] in {
362 def MULHSU : ArithN<0x10, 0x002, "mulhsu ", IIAlu>;
365 let Predicates=[HasBarrel] in {
366 def BSRL : Arith<0x11, 0x000, "bsrl ", srl, IIAlu>;
367 def BSRA : Arith<0x11, 0x200, "bsra ", sra, IIAlu>;
368 def BSLL : Arith<0x11, 0x400, "bsll ", shl, IIAlu>;
369 def BSRLI : ShiftI<0x19, 0x0, "bsrli ", srl, uimm5, immZExt5>;
370 def BSRAI : ShiftI<0x19, 0x1, "bsrai ", sra, uimm5, immZExt5>;
371 def BSLLI : ShiftI<0x19, 0x2, "bslli ", shl, uimm5, immZExt5>;
374 let Predicates=[HasDiv] in {
375 def IDIV : ArithR<0x12, 0x000, "idiv ", sdiv, IIAlu>;
376 def IDIVU : ArithR<0x12, 0x002, "idivu ", udiv, IIAlu>;
379 //===----------------------------------------------------------------------===//
380 // MBlaze immediate mode arithmetic instructions
381 //===----------------------------------------------------------------------===//
383 let isAsCheapAsAMove = 1 in {
384 def ADDI : ArithI<0x08, "addi ", add, simm16, immSExt16>;
385 def ADDIC : ArithNI<0x0A, "addic ", simm16, immSExt16>;
386 def ADDIK : ArithNI<0x0C, "addik ", simm16, immSExt16>;
387 def ADDIKC : ArithI<0x0E, "addikc ", addc, simm16, immSExt16>;
388 def RSUBI : ArithRI<0x09, "rsubi ", sub, simm16, immSExt16>;
389 def RSUBIC : ArithRNI<0x0B, "rsubic ", simm16, immSExt16>;
390 def RSUBIK : ArithRNI<0x0D, "rsubik ", simm16, immSExt16>;
391 def RSUBIKC : ArithRI<0x0F, "rsubikc", subc, simm16, immSExt16>;
392 def ANDNI : ArithNI<0x2B, "andni ", uimm16, immZExt16>;
393 def ANDI : LogicI<0x29, "andi ", and>;
394 def ORI : LogicI<0x28, "ori ", or>;
395 def XORI : LogicI<0x2A, "xori ", xor>;
398 let Predicates=[HasMul] in {
399 def MULI : ArithI<0x18, "muli ", mul, simm16, immSExt16>;
402 //===----------------------------------------------------------------------===//
403 // MBlaze memory access instructions
404 //===----------------------------------------------------------------------===//
406 let canFoldAsLoad = 1, isReMaterializable = 1 in {
407 def LBU : LoadM<0x30, 0x000, "lbu ">;
408 def LBUR : LoadM<0x30, 0x200, "lbur ">;
410 def LHU : LoadM<0x31, 0x000, "lhu ">;
411 def LHUR : LoadM<0x31, 0x200, "lhur ">;
413 def LW : LoadM<0x32, 0x000, "lw ">;
414 def LWR : LoadM<0x32, 0x200, "lwr ">;
415 def LWX : LoadM<0x32, 0x400, "lwx ">;
417 def LBUI : LoadMI<0x38, "lbui ", zextloadi8>;
418 def LHUI : LoadMI<0x39, "lhui ", zextloadi16>;
419 def LWI : LoadMI<0x3A, "lwi ", load>;
422 def SB : StoreM<0x34, 0x000, "sb ">;
423 def SBR : StoreM<0x34, 0x200, "sbr ">;
425 def SH : StoreM<0x35, 0x000, "sh ">;
426 def SHR : StoreM<0x35, 0x200, "shr ">;
428 def SW : StoreM<0x36, 0x000, "sw ">;
429 def SWR : StoreM<0x36, 0x200, "swr ">;
430 def SWX : StoreM<0x36, 0x400, "swx ">;
432 def SBI : StoreMI<0x3C, "sbi ", truncstorei8>;
433 def SHI : StoreMI<0x3D, "shi ", truncstorei16>;
434 def SWI : StoreMI<0x3E, "swi ", store>;
436 //===----------------------------------------------------------------------===//
437 // MBlaze branch instructions
438 //===----------------------------------------------------------------------===//
440 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
441 def BRI : BranchI<0x2E, 0x00, "bri ">;
442 def BRAI : BranchI<0x2E, 0x08, "brai ">;
445 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
446 def BEQI : BranchCI<0x2F, 0x00, "beqi ">;
447 def BNEI : BranchCI<0x2F, 0x01, "bnei ">;
448 def BLTI : BranchCI<0x2F, 0x02, "blti ">;
449 def BLEI : BranchCI<0x2F, 0x03, "blei ">;
450 def BGTI : BranchCI<0x2F, 0x04, "bgti ">;
451 def BGEI : BranchCI<0x2F, 0x05, "bgei ">;
454 let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1,
456 def BR : Branch<0x26, 0x00, 0x000, "br ">;
457 def BRA : Branch<0x26, 0x08, 0x000, "bra ">;
460 let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
461 def BEQ : BranchC<0x27, 0x00, 0x000, "beq ">;
462 def BNE : BranchC<0x27, 0x01, 0x000, "bne ">;
463 def BLT : BranchC<0x27, 0x02, 0x000, "blt ">;
464 def BLE : BranchC<0x27, 0x03, 0x000, "ble ">;
465 def BGT : BranchC<0x27, 0x04, 0x000, "bgt ">;
466 def BGE : BranchC<0x27, 0x05, 0x000, "bge ">;
469 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1,
471 def BRID : BranchI<0x2E, 0x10, "brid ">;
472 def BRAID : BranchI<0x2E, 0x18, "braid ">;
475 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1 in {
476 def BEQID : BranchCI<0x2F, 0x10, "beqid ">;
477 def BNEID : BranchCI<0x2F, 0x11, "bneid ">;
478 def BLTID : BranchCI<0x2F, 0x12, "bltid ">;
479 def BLEID : BranchCI<0x2F, 0x13, "bleid ">;
480 def BGTID : BranchCI<0x2F, 0x14, "bgtid ">;
481 def BGEID : BranchCI<0x2F, 0x15, "bgeid ">;
484 let isBranch = 1, isIndirectBranch = 1, isTerminator = 1,
485 hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1 in {
486 def BRD : Branch<0x26, 0x10, 0x000, "brd ">;
487 def BRAD : Branch<0x26, 0x18, 0x000, "brad ">;
490 let isBranch = 1, isIndirectBranch = 1, isTerminator = 1,
491 hasDelaySlot = 1, hasCtrlDep = 1 in {
492 def BEQD : BranchC<0x27, 0x10, 0x000, "beqd ">;
493 def BNED : BranchC<0x27, 0x11, 0x000, "bned ">;
494 def BLTD : BranchC<0x27, 0x12, 0x000, "bltd ">;
495 def BLED : BranchC<0x27, 0x13, 0x000, "bled ">;
496 def BGTD : BranchC<0x27, 0x14, 0x000, "bgtd ">;
497 def BGED : BranchC<0x27, 0x15, 0x000, "bged ">;
500 let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1,
501 Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
502 Uses = [R1,R5,R6,R7,R8,R9,R10] in {
503 def BRLID : BranchLI<0x2E, 0x14, "brlid ">;
504 def BRALID : BranchLI<0x2E, 0x1C, "bralid ">;
507 let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isIndirectBranch = 1,
509 Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
510 Uses = [R1,R5,R6,R7,R8,R9,R10] in {
511 def BRLD : BranchL<0x26, 0x14, 0x000, "brld ">;
512 def BRALD : BranchL<0x26, 0x1C, 0x000, "brald ">;
515 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
516 hasCtrlDep=1, rd=0x10, Form=FCRI in {
517 def RTSD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
518 "rtsd $target, $imm",
523 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
524 hasCtrlDep=1, rd=0x11, Form=FCRI in {
525 def RTID : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
526 "rtid $target, $imm",
531 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
532 hasCtrlDep=1, rd=0x12, Form=FCRI in {
533 def RTBD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
534 "rtbd $target, $imm",
539 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
540 hasCtrlDep=1, rd=0x14, Form=FCRI in {
541 def RTED : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
542 "rted $target, $imm",
547 //===----------------------------------------------------------------------===//
548 // MBlaze misc instructions
549 //===----------------------------------------------------------------------===//
551 let neverHasSideEffects = 1 in {
552 def NOP : MBlazeInst< 0x20, FC, (outs), (ins), "nop ", [], IIAlu>;
555 let usesCustomInserter = 1 in {
556 def Select_CC : MBlazePseudo<(outs GPR:$dst),
557 (ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC), // F T reversed
558 "; SELECT_CC PSEUDO!",
561 def ShiftL : MBlazePseudo<(outs GPR:$dst),
562 (ins GPR:$L, GPR:$R),
566 def ShiftRA : MBlazePseudo<(outs GPR:$dst),
567 (ins GPR:$L, GPR:$R),
571 def ShiftRL : MBlazePseudo<(outs GPR:$dst),
572 (ins GPR:$L, GPR:$R),
579 def SEXT16 : TA<0x24, 0x061, (outs GPR:$dst), (ins GPR:$src),
580 "sext16 $dst, $src", [], IIAlu>;
581 def SEXT8 : TA<0x24, 0x060, (outs GPR:$dst), (ins GPR:$src),
582 "sext8 $dst, $src", [], IIAlu>;
583 def SRL : TA<0x24, 0x041, (outs GPR:$dst), (ins GPR:$src),
584 "srl $dst, $src", [], IIAlu>;
585 def SRA : TA<0x24, 0x001, (outs GPR:$dst), (ins GPR:$src),
586 "sra $dst, $src", [], IIAlu>;
587 def SRC : TA<0x24, 0x021, (outs GPR:$dst), (ins GPR:$src),
588 "src $dst, $src", [], IIAlu>;
591 let isCodeGenOnly=1 in {
592 def ADDI32 : ArithI32<0x08, "addi ", simm16, immSExt16>;
593 def ORI32 : LogicI32<0x28, "ori ">;
594 def BRLID32 : BranchLI<0x2E, 0x14, "brlid ">;
597 //===----------------------------------------------------------------------===//
598 // Misc. instructions
599 //===----------------------------------------------------------------------===//
600 def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins uimm14:$rg),
601 "mfs $dst, $rg", [], IIAlu>;
603 def MTS : SPC<0x25, 0x3, (outs), (ins uimm14:$dst, GPR:$rg),
604 "mts $dst, $rg", [], IIAlu>;
606 def MSRSET : MSR<0x25, 0x20, (outs GPR:$dst), (ins uimm15:$set),
607 "msrset $dst, $set", [], IIAlu>;
609 def MSRCLR : MSR<0x25, 0x22, (outs GPR:$dst), (ins uimm15:$clr),
610 "msrclr $dst, $clr", [], IIAlu>;
612 let rd=0x0, Form=FCRR in {
613 def WDC : TA<0x24, 0x64, (outs), (ins GPR:$a, GPR:$b),
614 "wdc $a, $b", [], IIAlu>;
615 def WDCF : TA<0x24, 0x74, (outs), (ins GPR:$a, GPR:$b),
616 "wdc.flush $a, $b", [], IIAlu>;
617 def WDCC : TA<0x24, 0x66, (outs), (ins GPR:$a, GPR:$b),
618 "wdc.clear $a, $b", [], IIAlu>;
619 def WIC : TA<0x24, 0x68, (outs), (ins GPR:$a, GPR:$b),
620 "wic $a, $b", [], IIAlu>;
623 def BRK : BranchL<0x26, 0x0C, 0x000, "brk ">;
624 def BRKI : BranchLI<0x2E, 0x0C, "brki ">;
626 def IMM : MBlazeInst<0x2C, FCCI, (outs), (ins simm16:$imm),
627 "imm $imm", [], IIAlu>;
629 //===----------------------------------------------------------------------===//
630 // Arbitrary patterns that map to one or more instructions
631 //===----------------------------------------------------------------------===//
634 def : Pat<(i32 0), (ADD (i32 R0), (i32 R0))>;
635 def : Pat<(i32 immSExt16:$imm), (ADDI (i32 R0), imm:$imm)>;
636 def : Pat<(i32 immZExt16:$imm), (ORI (i32 R0), imm:$imm)>;
638 // Arbitrary immediates
639 def : Pat<(i32 imm:$imm), (ADDI (i32 R0), imm:$imm)>;
641 // In register sign extension
642 def : Pat<(sext_inreg GPR:$src, i16), (SEXT16 GPR:$src)>;
643 def : Pat<(sext_inreg GPR:$src, i8), (SEXT8 GPR:$src)>;
646 def : Pat<(MBlazeJmpLink (i32 tglobaladdr:$dst)),
647 (BRLID (i32 R15), tglobaladdr:$dst)>;
649 def : Pat<(MBlazeJmpLink (i32 texternalsym:$dst)),
650 (BRLID (i32 R15), texternalsym:$dst)>;
652 def : Pat<(MBlazeJmpLink GPR:$dst),
653 (BRALD (i32 R15), GPR:$dst)>;
655 // Shift Instructions
656 def : Pat<(shl GPR:$L, GPR:$R), (ShiftL GPR:$L, GPR:$R)>;
657 def : Pat<(sra GPR:$L, GPR:$R), (ShiftRA GPR:$L, GPR:$R)>;
658 def : Pat<(srl GPR:$L, GPR:$R), (ShiftRL GPR:$L, GPR:$R)>;
661 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ),
662 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
663 (CMP GPR:$R, GPR:$L), 1)>;
664 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETNE),
665 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
666 (CMP GPR:$R, GPR:$L), 2)>;
667 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGT),
668 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
669 (CMP GPR:$R, GPR:$L), 3)>;
670 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLT),
671 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
672 (CMP GPR:$R, GPR:$L), 4)>;
673 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGE),
674 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
675 (CMP GPR:$R, GPR:$L), 5)>;
676 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLE),
677 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
678 (CMP GPR:$R, GPR:$L), 6)>;
679 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT),
680 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
681 (CMPU GPR:$R, GPR:$L), 3)>;
682 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULT),
683 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
684 (CMPU GPR:$R, GPR:$L), 4)>;
685 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE),
686 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
687 (CMPU GPR:$R, GPR:$L), 5)>;
688 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULE),
689 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
690 (CMPU GPR:$R, GPR:$L), 6)>;
693 def : Pat<(select (i32 GPR:$C), (i32 GPR:$T), (i32 GPR:$F)),
694 (Select_CC GPR:$T, GPR:$F, GPR:$C, 2)>;
697 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
698 (i32 GPR:$T), (i32 GPR:$F), SETEQ),
699 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 1)>;
700 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
701 (i32 GPR:$T), (i32 GPR:$F), SETNE),
702 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 2)>;
703 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
704 (i32 GPR:$T), (i32 GPR:$F), SETGT),
705 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 3)>;
706 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
707 (i32 GPR:$T), (i32 GPR:$F), SETLT),
708 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 4)>;
709 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
710 (i32 GPR:$T), (i32 GPR:$F), SETGE),
711 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 5)>;
712 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
713 (i32 GPR:$T), (i32 GPR:$F), SETLE),
714 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 6)>;
715 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
716 (i32 GPR:$T), (i32 GPR:$F), SETUGT),
717 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, GPR:$L), 3)>;
718 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
719 (i32 GPR:$T), (i32 GPR:$F), SETULT),
720 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, GPR:$L), 4)>;
721 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
722 (i32 GPR:$T), (i32 GPR:$F), SETUGE),
723 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, GPR:$L), 5)>;
724 def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
725 (i32 GPR:$T), (i32 GPR:$F), SETULE),
726 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, GPR:$L), 6)>;
729 def : Pat<(MBlazeRet GPR:$target), (RTSD GPR:$target, 0x8)>;
732 def : Pat<(br bb:$T), (BRID bb:$T)>;
733 def : Pat<(brind GPR:$T), (BRAD GPR:$T)>;
735 // BRCOND instructions
736 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ), bb:$T),
737 (BEQID (CMP GPR:$R, GPR:$L), bb:$T)>;
738 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETNE), bb:$T),
739 (BNEID (CMP GPR:$R, GPR:$L), bb:$T)>;
740 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETGT), bb:$T),
741 (BGTID (CMP GPR:$R, GPR:$L), bb:$T)>;
742 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETLT), bb:$T),
743 (BLTID (CMP GPR:$R, GPR:$L), bb:$T)>;
744 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETGE), bb:$T),
745 (BGEID (CMP GPR:$R, GPR:$L), bb:$T)>;
746 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETLE), bb:$T),
747 (BLEID (CMP GPR:$R, GPR:$L), bb:$T)>;
748 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT), bb:$T),
749 (BGTID (CMPU GPR:$R, GPR:$L), bb:$T)>;
750 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETULT), bb:$T),
751 (BLTID (CMPU GPR:$R, GPR:$L), bb:$T)>;
752 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE), bb:$T),
753 (BGEID (CMPU GPR:$R, GPR:$L), bb:$T)>;
754 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETULE), bb:$T),
755 (BLEID (CMPU GPR:$R, GPR:$L), bb:$T)>;
756 def : Pat<(brcond (i32 GPR:$C), bb:$T),
757 (BNEID GPR:$C, bb:$T)>;
759 // Jump tables, global addresses, and constant pools
760 def : Pat<(MBWrapper tglobaladdr:$in), (ORI (i32 R0), tglobaladdr:$in)>;
761 def : Pat<(MBWrapper tjumptable:$in), (ORI (i32 R0), tjumptable:$in)>;
762 def : Pat<(MBWrapper tconstpool:$in), (ORI (i32 R0), tconstpool:$in)>;
765 def : Pat<(and (i32 GPR:$lh), (not (i32 GPR:$rh))),(ANDN GPR:$lh, GPR:$rh)>;
767 // Arithmetic with immediates
768 def : Pat<(add (i32 GPR:$in), imm:$imm),(ADDI GPR:$in, imm:$imm)>;
769 def : Pat<(or (i32 GPR:$in), imm:$imm),(ORI GPR:$in, imm:$imm)>;
770 def : Pat<(xor (i32 GPR:$in), imm:$imm),(XORI GPR:$in, imm:$imm)>;
772 // Convert any extend loads into zero extend loads
773 def : Pat<(extloadi8 iaddr:$src), (i32 (LBUI iaddr:$src))>;
774 def : Pat<(extloadi16 iaddr:$src), (i32 (LHUI iaddr:$src))>;
775 def : Pat<(extloadi8 xaddr:$src), (i32 (LBU xaddr:$src))>;
776 def : Pat<(extloadi16 xaddr:$src), (i32 (LHU xaddr:$src))>;
778 // 32-bit load and store
779 def : Pat<(store (i32 GPR:$dst), xaddr:$addr), (SW GPR:$dst, xaddr:$addr)>;
780 def : Pat<(load xaddr:$addr), (i32 (LW xaddr:$addr))>;
782 // 16-bit load and store
783 def : Pat<(truncstorei16 (i32 GPR:$dst), xaddr:$addr), (SH GPR:$dst, xaddr:$addr)>;
784 def : Pat<(zextloadi16 xaddr:$addr), (i32 (LHU xaddr:$addr))>;
786 // 8-bit load and store
787 def : Pat<(truncstorei8 (i32 GPR:$dst), xaddr:$addr), (SB GPR:$dst, xaddr:$addr)>;
788 def : Pat<(zextloadi8 xaddr:$addr), (i32 (LBU xaddr:$addr))>;
791 def : Pat<(store (i32 0), iaddr:$dst), (SWI (i32 R0), iaddr:$dst)>;
793 //===----------------------------------------------------------------------===//
794 // Floating Point Support
795 //===----------------------------------------------------------------------===//
796 include "MBlazeInstrFSL.td"
797 include "MBlazeInstrFPU.td"