1 //===- MBlazeRegisterInfo.td - MBlaze Register defs --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the MicroBlaze register file
12 //===----------------------------------------------------------------------===//
14 // We have banks of 32 registers each.
15 class MBlazeReg<string n> : Register<n> {
17 let Namespace = "MBlaze";
20 // MBlaze CPU Registers
21 class MBlazeGPRReg<bits<5> num, string n> : MBlazeReg<n> {
25 // MBlaze 32-bit (aliased) FPU Registers
26 class FPR<bits<5> num, string n, list<Register> aliases> : MBlazeReg<n> {
28 let Aliases = aliases;
31 //===----------------------------------------------------------------------===//
33 //===----------------------------------------------------------------------===//
35 let Namespace = "MBlaze" in {
37 // General Purpose Registers
38 def R0 : MBlazeGPRReg< 0, "r0">, DwarfRegNum<[0]>;
39 def R1 : MBlazeGPRReg< 1, "r1">, DwarfRegNum<[1]>;
40 def R2 : MBlazeGPRReg< 2, "r2">, DwarfRegNum<[2]>;
41 def R3 : MBlazeGPRReg< 3, "r3">, DwarfRegNum<[3]>;
42 def R4 : MBlazeGPRReg< 4, "r4">, DwarfRegNum<[5]>;
43 def R5 : MBlazeGPRReg< 5, "r5">, DwarfRegNum<[5]>;
44 def R6 : MBlazeGPRReg< 6, "r6">, DwarfRegNum<[6]>;
45 def R7 : MBlazeGPRReg< 7, "r7">, DwarfRegNum<[7]>;
46 def R8 : MBlazeGPRReg< 8, "r8">, DwarfRegNum<[8]>;
47 def R9 : MBlazeGPRReg< 9, "r9">, DwarfRegNum<[9]>;
48 def R10 : MBlazeGPRReg< 10, "r10">, DwarfRegNum<[10]>;
49 def R11 : MBlazeGPRReg< 11, "r11">, DwarfRegNum<[11]>;
50 def R12 : MBlazeGPRReg< 12, "r12">, DwarfRegNum<[12]>;
51 def R13 : MBlazeGPRReg< 13, "r13">, DwarfRegNum<[13]>;
52 def R14 : MBlazeGPRReg< 14, "r14">, DwarfRegNum<[14]>;
53 def R15 : MBlazeGPRReg< 15, "r15">, DwarfRegNum<[15]>;
54 def R16 : MBlazeGPRReg< 16, "r16">, DwarfRegNum<[16]>;
55 def R17 : MBlazeGPRReg< 17, "r17">, DwarfRegNum<[17]>;
56 def R18 : MBlazeGPRReg< 18, "r18">, DwarfRegNum<[18]>;
57 def R19 : MBlazeGPRReg< 19, "r19">, DwarfRegNum<[19]>;
58 def R20 : MBlazeGPRReg< 20, "r20">, DwarfRegNum<[20]>;
59 def R21 : MBlazeGPRReg< 21, "r21">, DwarfRegNum<[21]>;
60 def R22 : MBlazeGPRReg< 22, "r22">, DwarfRegNum<[22]>;
61 def R23 : MBlazeGPRReg< 23, "r23">, DwarfRegNum<[23]>;
62 def R24 : MBlazeGPRReg< 24, "r24">, DwarfRegNum<[24]>;
63 def R25 : MBlazeGPRReg< 25, "r25">, DwarfRegNum<[25]>;
64 def R26 : MBlazeGPRReg< 26, "r26">, DwarfRegNum<[26]>;
65 def R27 : MBlazeGPRReg< 27, "r27">, DwarfRegNum<[27]>;
66 def R28 : MBlazeGPRReg< 28, "r28">, DwarfRegNum<[28]>;
67 def R29 : MBlazeGPRReg< 29, "r29">, DwarfRegNum<[29]>;
68 def R30 : MBlazeGPRReg< 30, "r30">, DwarfRegNum<[30]>;
69 def R31 : MBlazeGPRReg< 31, "r31">, DwarfRegNum<[31]>;
71 /// MBlaze Single point precision FPU Registers
72 def F0 : FPR< 0, "r0", [R0]>, DwarfRegNum<[32]>;
73 def F1 : FPR< 1, "r1", [R1]>, DwarfRegNum<[33]>;
74 def F2 : FPR< 2, "r2", [R2]>, DwarfRegNum<[34]>;
75 def F3 : FPR< 3, "r3", [R3]>, DwarfRegNum<[35]>;
76 def F4 : FPR< 4, "r4", [R4]>, DwarfRegNum<[36]>;
77 def F5 : FPR< 5, "r5", [R5]>, DwarfRegNum<[37]>;
78 def F6 : FPR< 6, "r6", [R6]>, DwarfRegNum<[38]>;
79 def F7 : FPR< 7, "r7", [R7]>, DwarfRegNum<[39]>;
80 def F8 : FPR< 8, "r8", [R8]>, DwarfRegNum<[40]>;
81 def F9 : FPR< 9, "r9", [R9]>, DwarfRegNum<[41]>;
82 def F10 : FPR<10, "r10", [R10]>, DwarfRegNum<[42]>;
83 def F11 : FPR<11, "r11", [R11]>, DwarfRegNum<[43]>;
84 def F12 : FPR<12, "r12", [R12]>, DwarfRegNum<[44]>;
85 def F13 : FPR<13, "r13", [R13]>, DwarfRegNum<[45]>;
86 def F14 : FPR<14, "r14", [R14]>, DwarfRegNum<[46]>;
87 def F15 : FPR<15, "r15", [R15]>, DwarfRegNum<[47]>;
88 def F16 : FPR<16, "r16", [R16]>, DwarfRegNum<[48]>;
89 def F17 : FPR<17, "r17", [R17]>, DwarfRegNum<[49]>;
90 def F18 : FPR<18, "r18", [R18]>, DwarfRegNum<[50]>;
91 def F19 : FPR<19, "r19", [R19]>, DwarfRegNum<[51]>;
92 def F20 : FPR<20, "r20", [R20]>, DwarfRegNum<[52]>;
93 def F21 : FPR<21, "r21", [R21]>, DwarfRegNum<[53]>;
94 def F22 : FPR<22, "r22", [R22]>, DwarfRegNum<[54]>;
95 def F23 : FPR<23, "r23", [R23]>, DwarfRegNum<[55]>;
96 def F24 : FPR<24, "r24", [R24]>, DwarfRegNum<[56]>;
97 def F25 : FPR<25, "r25", [R25]>, DwarfRegNum<[57]>;
98 def F26 : FPR<26, "r26", [R26]>, DwarfRegNum<[58]>;
99 def F27 : FPR<27, "r27", [R27]>, DwarfRegNum<[59]>;
100 def F28 : FPR<28, "r28", [R28]>, DwarfRegNum<[60]>;
101 def F29 : FPR<29, "r29", [R29]>, DwarfRegNum<[61]>;
102 def F30 : FPR<30, "r30", [R30]>, DwarfRegNum<[62]>;
103 def F31 : FPR<31, "r31", [R31]>, DwarfRegNum<[63]>;
106 //===----------------------------------------------------------------------===//
108 //===----------------------------------------------------------------------===//
110 def CPURegs : RegisterClass<"MBlaze", [i32], 32,
112 // Return Values and Arguments
113 R3, R4, R5, R6, R7, R8, R9, R10,
115 // Not preserved across procedure calls
119 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
123 R1, // The stack pointer
124 R2, // Read-only small data area anchor
125 R13, // Read-write small data area anchor
126 R14, // Return address for interrupts
127 R15, // Return address for sub-routines
128 R16, // Return address for trap
129 R17, // Return address for exceptions
130 R18, // Reserved for assembler
131 R19 // The frame-pointer
134 let MethodProtos = [{
135 iterator allocation_order_end(const MachineFunction &MF) const;
137 let MethodBodies = [{
138 CPURegsClass::iterator
139 CPURegsClass::allocation_order_end(const MachineFunction &MF) const {
140 // The last 10 registers on the list above are reserved
146 def FGR32 : RegisterClass<"MBlaze", [f32], 32,
148 // Return Values and Arguments
149 F3, F4, F5, F6, F7, F8, F9, F10,
151 // Not preserved across procedure calls
155 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31,
159 F1, // The stack pointer
160 F2, // Read-only small data area anchor
161 F13, // Read-write small data area anchor
162 F14, // Return address for interrupts
163 F15, // Return address for sub-routines
164 F16, // Return address for trap
165 F17, // Return address for exceptions
166 F18, // Reserved for assembler
167 F19 // The frame pointer
170 let MethodProtos = [{
171 iterator allocation_order_end(const MachineFunction &MF) const;
173 let MethodBodies = [{
175 FGR32Class::allocation_order_end(const MachineFunction &MF) const {
176 // The last 10 registers on the list above are reserved