1 //===- MBlazeSubtarget.cpp - MBlaze Subtarget Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MBlaze specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "MBlazeSubtarget.h"
16 #include "MBlazeRegisterInfo.h"
17 #include "llvm/Support/CommandLine.h"
19 #define GET_SUBTARGETINFO_ENUM
20 #define GET_SUBTARGETINFO_MC_DESC
21 #define GET_SUBTARGETINFO_TARGET_DESC
22 #define GET_SUBTARGETINFO_CTOR
23 #include "MBlazeGenSubtargetInfo.inc"
27 MBlazeSubtarget::MBlazeSubtarget(const std::string &TT,
28 const std::string &CPU,
29 const std::string &FS):
30 MBlazeGenSubtargetInfo(TT, CPU, FS),
31 HasBarrel(false), HasDiv(false), HasMul(false), HasPatCmp(false),
32 HasFPU(false), HasMul64(false), HasSqrt(false)
34 // Parse features string.
35 std::string CPUName = CPU;
38 ParseSubtargetFeatures(CPUName, FS);
40 // Only use instruction scheduling if the selected CPU has an instruction
41 // itinerary (the default CPU is the only one that doesn't).
42 HasItin = CPUName != "mblaze";
43 DEBUG(dbgs() << "CPU " << CPUName << "(" << HasItin << ")\n");
45 // Initialize scheduling itinerary for the specified CPU.
46 InstrItins = getInstrItineraryForCPU(CPUName);
48 // Compute the issue width of the MBlaze itineraries
52 void MBlazeSubtarget::computeIssueWidth() {
53 InstrItins.IssueWidth = 1;
56 bool MBlazeSubtarget::
57 enablePostRAScheduler(CodeGenOpt::Level OptLevel,
58 TargetSubtargetInfo::AntiDepBreakMode& Mode,
59 RegClassVector& CriticalPathRCs) const {
60 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
61 CriticalPathRCs.clear();
62 CriticalPathRCs.push_back(&MBlaze::GPRRegClass);
63 return HasItin && OptLevel >= CodeGenOpt::Default;