1 * Writing out ELF files is close to working but the following needs to
2 be examined more closely:
3 - ELF files are written with the wrong E_MACHINE value because
4 ELFObjectWriter::WriteHeader function does not yet support
5 target specific E_MACHINE values.
6 - ELF relocation records are incorrect because the function
7 ELFObjectWriter::RecordRelocation is hard coded for X86/X86-64.
8 - Relocations use 2-byte / 4-byte to terminology in reference to
9 the size of the immediate value being changed. The Xilinx
10 terminology seems to be (???) 4-byte / 8-byte in reference
11 to the number of bytes of instructions that are being changed.
12 - BRLID and like instructions are always assumed to use a 4-byte
13 immediate value for the relocation and BEQID and like instructions
14 are always assumed to use a 2-byte immediate value for the relocation.
15 I think this means that conditional branches like BEQID can only
16 branch += 32768 bytes (~8192 instructions). We should allow conditional
17 branches to use 4-byte relocations but I'm not sure how to do that
19 - Relocation records for indirect calls are not being generated
20 correctly. These should emit and IMM 0 directly before the ORI
21 instruction that loads the register (just like when a BRLID
22 instruction is used instead of an ORI).
24 * Code generation seems to work relatively well now but the following
25 needs to be examined more closely:
26 - The stack layout needs to be examined to make sure it meets
27 the standard, especially in regards to var arg functions.
28 - The delay slot filler is ad hoc but seems to work. Load and
29 store instructions were prevented from being moved to delay
30 slots but I'm not sure that is necessary.
31 - The processor itineraries are copied from a different backend
32 and need to be updated to model the MicroBlaze correctly.
33 - Look at the MBlazeGenFastISel.inc stuff and make use of it