1 * Writing out ELF files is close to working but the following needs to
2 be examined more closely:
3 - ELF relocation records are incorrect because the function
4 ELFObjectWriter::RecordRelocation is hard coded for X86/X86-64.
5 - Relocations use 2-byte / 4-byte to terminology in reference to
6 the size of the immediate value being changed. The Xilinx
7 terminology seems to be (???) 4-byte / 8-byte in reference
8 to the number of bytes of instructions that are being changed.
9 - BRLID and like instructions are always assumed to use a 4-byte
10 immediate value for the relocation and BEQID and like instructions
11 are always assumed to use a 2-byte immediate value for the relocation.
12 I think this means that conditional branches like BEQID can only
13 branch += 32768 bytes (~8192 instructions). We should allow conditional
14 branches to use 4-byte relocations but I'm not sure how to do that
16 - Relocation records for indirect calls are not being generated
17 correctly. These should emit and IMM 0 directly before the ORI
18 instruction that loads the register (just like when a BRLID
19 instruction is used instead of an ORI).
21 * Code generation seems to work relatively well now but the following
22 needs to be examined more closely:
23 - The stack layout needs to be examined to make sure it meets
24 the standard, especially in regards to var arg functions.
25 - The delay slot filler is ad hoc but seems to work. Load and
26 store instructions were prevented from being moved to delay
27 slots but I'm not sure that is necessary.
28 - The processor itineraries are copied from a different backend
29 and need to be updated to model the MicroBlaze correctly.
30 - Look at the MBlazeGenFastISel.inc stuff and make use of it
33 * A basic assembly parser is present now and seems to parse most things.
34 There are a few things that need to be looked at:
35 - There are some instructions that are not generated by the backend
36 and have not been tested as far as the parser is concerned.
37 - The assembly parser does not use any MicroBlaze specific directives.
38 I should investigate if there are MicroBlaze specific directive and,
39 if there are, add them.
40 - The instruction MFS and MTS use special names for some of the
41 special registers that can be accessed. These special register
42 names should be parsed by the assembly parser.