1 //===- MRegisterInfo.cpp - Target Register Information Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MRegisterInfo interface.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/MRegisterInfo.h"
18 MRegisterInfo::MRegisterInfo(const MRegisterDesc *D, unsigned NR,
19 regclass_iterator RCB, regclass_iterator RCE,
21 : Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
22 assert(NumRegs < FirstVirtualRegister &&
23 "Target has too many physical registers!");
25 PhysRegClasses = new const TargetRegisterClass*[NumRegs];
26 for (unsigned i = 0; i != NumRegs; ++i)
27 PhysRegClasses[i] = 0;
29 // Fill in the PhysRegClasses map
30 for (MRegisterInfo::regclass_iterator I = regclass_begin(),
31 E = regclass_end(); I != E; ++I) {
32 const TargetRegisterClass *RC = *I;
33 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i) {
34 unsigned Reg = RC->getRegister(i);
35 assert(PhysRegClasses[Reg] == 0 && "Register in more than one class?");
36 PhysRegClasses[Reg] = RC;
40 CallFrameSetupOpcode = CFSO;
41 CallFrameDestroyOpcode = CFDO;
45 MRegisterInfo::~MRegisterInfo() {
46 delete[] PhysRegClasses;
49 std::vector<bool> MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
50 std::vector<bool> Allocatable(NumRegs);
51 for (MRegisterInfo::regclass_iterator I = regclass_begin(),
52 E = regclass_end(); I != E; ++I) {
53 const TargetRegisterClass *RC = *I;
54 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
55 E = RC->allocation_order_end(MF); I != E; ++I)
56 Allocatable[*I] = true;
61 } // End llvm namespace