1 //===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MSP430 target.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430TargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SelectionDAGISel.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DerivedTypes.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/Intrinsics.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetLowering.h"
35 struct MSP430ISelAddressMode {
41 struct { // This is really a union, discriminated by BaseType!
47 const GlobalValue *GV;
49 const BlockAddress *BlockAddr;
52 unsigned Align; // CP alignment.
54 MSP430ISelAddressMode()
55 : BaseType(RegBase), Disp(0), GV(0), CP(0), BlockAddr(0),
56 ES(0), JT(-1), Align(0) {
59 bool hasSymbolicDisplacement() const {
60 return GV != 0 || CP != 0 || ES != 0 || JT != -1;
64 errs() << "MSP430ISelAddressMode " << this << '\n';
65 if (BaseType == RegBase && Base.Reg.getNode() != 0) {
66 errs() << "Base.Reg ";
67 Base.Reg.getNode()->dump();
68 } else if (BaseType == FrameIndexBase) {
69 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
71 errs() << " Disp " << Disp << '\n';
78 errs() << " Align" << Align << '\n';
83 errs() << " JT" << JT << " Align" << Align << '\n';
88 /// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
89 /// instructions for SelectionDAG operations.
92 class MSP430DAGToDAGISel : public SelectionDAGISel {
93 const MSP430TargetLowering &Lowering;
94 const MSP430Subtarget &Subtarget;
97 MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
98 : SelectionDAGISel(TM, OptLevel),
99 Lowering(*TM.getTargetLowering()),
100 Subtarget(*TM.getSubtargetImpl()) { }
102 virtual const char *getPassName() const {
103 return "MSP430 DAG->DAG Pattern Instruction Selection";
106 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
107 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
108 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
111 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
112 std::vector<SDValue> &OutOps);
114 // Include the pieces autogenerated from the target description.
115 #include "MSP430GenDAGISel.inc"
118 SDNode *Select(SDNode *N);
119 SDNode *SelectIndexedLoad(SDNode *Op);
120 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
121 unsigned Opc8, unsigned Opc16);
123 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
125 } // end anonymous namespace
127 /// createMSP430ISelDag - This pass converts a legalized DAG into a
128 /// MSP430-specific DAG, ready for instruction scheduling.
130 FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
131 CodeGenOpt::Level OptLevel) {
132 return new MSP430DAGToDAGISel(TM, OptLevel);
136 /// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
137 /// These wrap things that will resolve down into a symbol reference. If no
138 /// match is possible, this returns true, otherwise it returns false.
139 bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
140 // If the addressing mode already has a symbol as the displacement, we can
141 // never match another symbol.
142 if (AM.hasSymbolicDisplacement())
145 SDValue N0 = N.getOperand(0);
147 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
148 AM.GV = G->getGlobal();
149 AM.Disp += G->getOffset();
150 //AM.SymbolFlags = G->getTargetFlags();
151 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
152 AM.CP = CP->getConstVal();
153 AM.Align = CP->getAlignment();
154 AM.Disp += CP->getOffset();
155 //AM.SymbolFlags = CP->getTargetFlags();
156 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
157 AM.ES = S->getSymbol();
158 //AM.SymbolFlags = S->getTargetFlags();
159 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
160 AM.JT = J->getIndex();
161 //AM.SymbolFlags = J->getTargetFlags();
163 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
164 //AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
169 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
170 /// specified addressing mode without any further recursion.
171 bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) {
172 // Is the base register already occupied?
173 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
174 // If so, we cannot select it.
178 // Default, generate it as a register.
179 AM.BaseType = MSP430ISelAddressMode::RegBase;
184 bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
185 DEBUG(errs() << "MatchAddress: "; AM.dump());
187 switch (N.getOpcode()) {
189 case ISD::Constant: {
190 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
195 case MSP430ISD::Wrapper:
196 if (!MatchWrapper(N, AM))
200 case ISD::FrameIndex:
201 if (AM.BaseType == MSP430ISelAddressMode::RegBase
202 && AM.Base.Reg.getNode() == 0) {
203 AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
204 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
210 MSP430ISelAddressMode Backup = AM;
211 if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
212 !MatchAddress(N.getNode()->getOperand(1), AM))
215 if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
216 !MatchAddress(N.getNode()->getOperand(0), AM))
224 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
225 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
226 MSP430ISelAddressMode Backup = AM;
227 uint64_t Offset = CN->getSExtValue();
228 // Start with the LHS as an addr mode.
229 if (!MatchAddress(N.getOperand(0), AM) &&
230 // Address could not have picked a GV address for the displacement.
232 // Check to see if the LHS & C is zero.
233 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
242 return MatchAddressBase(N, AM);
245 /// SelectAddr - returns true if it is able pattern match an addressing mode.
246 /// It returns the operands which make up the maximal addressing mode it can
247 /// match by reference.
248 bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
249 SDValue &Base, SDValue &Disp) {
250 MSP430ISelAddressMode AM;
252 if (MatchAddress(N, AM))
255 EVT VT = N.getValueType();
256 if (AM.BaseType == MSP430ISelAddressMode::RegBase) {
257 if (!AM.Base.Reg.getNode())
258 AM.Base.Reg = CurDAG->getRegister(0, VT);
261 Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase) ?
262 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex,
263 getTargetLowering()->getPointerTy()) :
267 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(N),
269 0/*AM.SymbolFlags*/);
271 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
272 AM.Align, AM.Disp, 0/*AM.SymbolFlags*/);
274 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
275 else if (AM.JT != -1)
276 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
277 else if (AM.BlockAddr)
278 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0,
279 0/*AM.SymbolFlags*/);
281 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i16);
286 bool MSP430DAGToDAGISel::
287 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
288 std::vector<SDValue> &OutOps) {
290 switch (ConstraintCode) {
291 default: return true;
293 if (!SelectAddr(Op, Op0, Op1))
298 OutOps.push_back(Op0);
299 OutOps.push_back(Op1);
303 static bool isValidIndexedLoad(const LoadSDNode *LD) {
304 ISD::MemIndexedMode AM = LD->getAddressingMode();
305 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
308 EVT VT = LD->getMemoryVT();
310 switch (VT.getSimpleVT().SimpleTy) {
313 if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1)
319 if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2)
330 SDNode *MSP430DAGToDAGISel::SelectIndexedLoad(SDNode *N) {
331 LoadSDNode *LD = cast<LoadSDNode>(N);
332 if (!isValidIndexedLoad(LD))
335 MVT VT = LD->getMemoryVT().getSimpleVT();
338 switch (VT.SimpleTy) {
340 Opcode = MSP430::MOV8rm_POST;
343 Opcode = MSP430::MOV16rm_POST;
349 return CurDAG->getMachineNode(Opcode, SDLoc(N),
350 VT, MVT::i16, MVT::Other,
351 LD->getBasePtr(), LD->getChain());
354 SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op,
355 SDValue N1, SDValue N2,
356 unsigned Opc8, unsigned Opc16) {
357 if (N1.getOpcode() == ISD::LOAD &&
359 IsLegalToFold(N1, Op, Op, OptLevel)) {
360 LoadSDNode *LD = cast<LoadSDNode>(N1);
361 if (!isValidIndexedLoad(LD))
364 MVT VT = LD->getMemoryVT().getSimpleVT();
365 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
366 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
367 MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
368 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
370 CurDAG->SelectNodeTo(Op, Opc,
371 VT, MVT::i16, MVT::Other,
373 cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
375 ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
376 // Transfer writeback.
377 ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
385 SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) {
388 // Dump information about the Node being selected
389 DEBUG(errs() << "Selecting: ");
390 DEBUG(Node->dump(CurDAG));
391 DEBUG(errs() << "\n");
393 // If we have a custom node, we already have selected!
394 if (Node->isMachineOpcode()) {
395 DEBUG(errs() << "== ";
402 // Few custom selection stuff.
403 switch (Node->getOpcode()) {
405 case ISD::FrameIndex: {
406 assert(Node->getValueType(0) == MVT::i16);
407 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
408 SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
409 if (Node->hasOneUse())
410 return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16,
411 TFI, CurDAG->getTargetConstant(0, MVT::i16));
412 return CurDAG->getMachineNode(MSP430::ADD16ri, dl, MVT::i16,
413 TFI, CurDAG->getTargetConstant(0, MVT::i16));
416 if (SDNode *ResNode = SelectIndexedLoad(Node))
418 // Other cases are autogenerated.
421 if (SDNode *ResNode =
422 SelectIndexedBinOp(Node,
423 Node->getOperand(0), Node->getOperand(1),
424 MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
426 else if (SDNode *ResNode =
427 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
428 MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
431 // Other cases are autogenerated.
434 if (SDNode *ResNode =
435 SelectIndexedBinOp(Node,
436 Node->getOperand(0), Node->getOperand(1),
437 MSP430::SUB8rm_POST, MSP430::SUB16rm_POST))
440 // Other cases are autogenerated.
443 if (SDNode *ResNode =
444 SelectIndexedBinOp(Node,
445 Node->getOperand(0), Node->getOperand(1),
446 MSP430::AND8rm_POST, MSP430::AND16rm_POST))
448 else if (SDNode *ResNode =
449 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
450 MSP430::AND8rm_POST, MSP430::AND16rm_POST))
453 // Other cases are autogenerated.
456 if (SDNode *ResNode =
457 SelectIndexedBinOp(Node,
458 Node->getOperand(0), Node->getOperand(1),
459 MSP430::OR8rm_POST, MSP430::OR16rm_POST))
461 else if (SDNode *ResNode =
462 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
463 MSP430::OR8rm_POST, MSP430::OR16rm_POST))
466 // Other cases are autogenerated.
469 if (SDNode *ResNode =
470 SelectIndexedBinOp(Node,
471 Node->getOperand(0), Node->getOperand(1),
472 MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
474 else if (SDNode *ResNode =
475 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
476 MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
479 // Other cases are autogenerated.
483 // Select the default instruction
484 SDNode *ResNode = SelectCode(Node);
486 DEBUG(errs() << "=> ");
487 if (ResNode == NULL || ResNode == Node)
488 DEBUG(Node->dump(CurDAG));
490 DEBUG(ResNode->dump(CurDAG));
491 DEBUG(errs() << "\n");