1 //===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MSP430 target.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430ISelLowering.h"
16 #include "MSP430TargetMachine.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Intrinsics.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/ADT/Statistic.h"
37 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
39 /// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
40 /// instructions for SelectionDAG operations.
43 class MSP430DAGToDAGISel : public SelectionDAGISel {
44 MSP430TargetLowering &Lowering;
45 const MSP430Subtarget &Subtarget;
48 MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
49 : SelectionDAGISel(TM, OptLevel),
50 Lowering(*TM.getTargetLowering()),
51 Subtarget(*TM.getSubtargetImpl()) { }
53 virtual void InstructionSelect();
55 virtual const char *getPassName() const {
56 return "MSP430 DAG->DAG Pattern Instruction Selection";
60 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
61 std::vector<SDValue> &OutOps);
63 // Include the pieces autogenerated from the target description.
64 #include "MSP430GenDAGISel.inc"
67 void PreprocessForRMW();
68 SDNode *Select(SDValue Op);
69 bool SelectAddr(SDValue Op, SDValue Addr, SDValue &Base, SDValue &Disp);
75 } // end anonymous namespace
77 /// createMSP430ISelDag - This pass converts a legalized DAG into a
78 /// MSP430-specific DAG, ready for instruction scheduling.
80 FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
81 CodeGenOpt::Level OptLevel) {
82 return new MSP430DAGToDAGISel(TM, OptLevel);
85 // FIXME: This is pretty dummy routine and needs to be rewritten in the future.
86 bool MSP430DAGToDAGISel::SelectAddr(SDValue Op, SDValue Addr,
87 SDValue &Base, SDValue &Disp) {
88 // Try to match frame address first.
89 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
90 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);
91 Disp = CurDAG->getTargetConstant(0, MVT::i16);
95 switch (Addr.getOpcode()) {
97 // Operand is a result from ADD with constant operand which fits into i16.
98 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
99 uint64_t CVal = CN->getZExtValue();
100 // Offset should fit into 16 bits.
101 if (((CVal << 48) >> 48) == CVal) {
102 SDValue N0 = Addr.getOperand(0);
103 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N0))
104 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);
108 Disp = CurDAG->getTargetConstant(CVal, MVT::i16);
113 case MSP430ISD::Wrapper:
114 SDValue N0 = Addr.getOperand(0);
115 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
116 Base = CurDAG->getTargetGlobalAddress(G->getGlobal(),
117 MVT::i16, G->getOffset());
118 Disp = CurDAG->getTargetConstant(0, MVT::i16);
120 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(N0)) {
121 Base = CurDAG->getTargetExternalSymbol(E->getSymbol(), MVT::i16);
122 Disp = CurDAG->getTargetConstant(0, MVT::i16);
128 Disp = CurDAG->getTargetConstant(0, MVT::i16);
134 bool MSP430DAGToDAGISel::
135 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
136 std::vector<SDValue> &OutOps) {
138 switch (ConstraintCode) {
139 default: return true;
141 if (!SelectAddr(Op, Op, Op0, Op1))
146 OutOps.push_back(Op0);
147 OutOps.push_back(Op1);
151 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
152 /// and move load below the TokenFactor. Replace store's chain operand with
153 /// load's chain result.
154 static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
155 SDValue Store, SDValue TF) {
156 SmallVector<SDValue, 4> Ops;
157 for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
158 if (Load.getNode() == TF.getOperand(i).getNode())
159 Ops.push_back(Load.getOperand(0));
161 Ops.push_back(TF.getOperand(i));
162 SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
163 SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
166 CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
167 Store.getOperand(2), Store.getOperand(3));
170 /// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
171 /// The chain produced by the load must only be used by the store's chain
172 /// operand, otherwise this may produce a cycle in the DAG.
173 static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
175 if (N.getOpcode() == ISD::BIT_CONVERT)
178 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
179 if (!LD || LD->isVolatile())
181 if (LD->getAddressingMode() != ISD::UNINDEXED)
184 ISD::LoadExtType ExtType = LD->getExtensionType();
185 if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
189 LD->hasNUsesOfValue(1, 1) &&
190 N.getOperand(1) == Address &&
191 LD->isOperandOf(Chain.getNode())) {
198 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
199 /// This is only run if not in -O0 mode.
200 /// This allows the instruction selector to pick more read-modify-write
201 /// instructions. This is a common case:
211 /// [TokenFactor] [Op]
218 /// The fact the store's chain operand != load's chain will prevent the
219 /// (store (op (load))) instruction from being selected. We can transform it to:
238 void MSP430DAGToDAGISel::PreprocessForRMW() {
239 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
240 E = CurDAG->allnodes_end(); I != E; ++I) {
241 if (!ISD::isNON_TRUNCStore(I))
243 SDValue Chain = I->getOperand(0);
245 if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
248 SDValue N1 = I->getOperand(1);
249 SDValue N2 = I->getOperand(2);
250 if ((N1.getValueType().isFloatingPoint() &&
251 !N1.getValueType().isVector()) ||
257 unsigned Opcode = N1.getNode()->getOpcode();
265 SDValue N10 = N1.getOperand(0);
266 SDValue N11 = N1.getOperand(1);
267 RModW = isRMWLoad(N10, Chain, N2, Load);
269 RModW = isRMWLoad(N11, Chain, N2, Load);
275 SDValue N10 = N1.getOperand(0);
276 RModW = isRMWLoad(N10, Chain, N2, Load);
282 MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain);
288 /// InstructionSelect - This callback is invoked by
289 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
290 void MSP430DAGToDAGISel::InstructionSelect() {
293 DEBUG(errs() << "Selection DAG after RMW preprocessing:\n");
294 DEBUG(CurDAG->dump());
298 // Codegen the basic block.
299 DEBUG(errs() << "===== Instruction selection begins:\n");
302 DEBUG(errs() << "===== Instruction selection ends:\n");
304 CurDAG->RemoveDeadNodes();
307 SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
308 SDNode *Node = Op.getNode();
309 DebugLoc dl = Op.getDebugLoc();
311 // Dump information about the Node being selected
312 DEBUG(errs().indent(Indent) << "Selecting: ");
313 DEBUG(Node->dump(CurDAG));
314 DEBUG(errs() << "\n");
317 // If we have a custom node, we already have selected!
318 if (Node->isMachineOpcode()) {
319 DEBUG(errs().indent(Indent-2) << "== ";
326 // Few custom selection stuff.
327 switch (Node->getOpcode()) {
329 case ISD::FrameIndex: {
330 assert(Op.getValueType() == MVT::i16);
331 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
332 SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
333 if (Node->hasOneUse())
334 return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16,
335 TFI, CurDAG->getTargetConstant(0, MVT::i16));
336 return CurDAG->getMachineNode(MSP430::ADD16ri, dl, MVT::i16,
337 TFI, CurDAG->getTargetConstant(0, MVT::i16));
341 // Select the default instruction
342 SDNode *ResNode = SelectCode(Op);
344 DEBUG(errs() << std::string(Indent-2, ' ') << "=> ");
345 if (ResNode == NULL || ResNode == Op.getNode())
346 DEBUG(Op.getNode()->dump(CurDAG));
348 DEBUG(ResNode->dump(CurDAG));
349 DEBUG(errs() << "\n");