1 //===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MSP430 target.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430ISelLowering.h"
16 #include "MSP430TargetMachine.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Intrinsics.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/ADT/Statistic.h"
37 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
41 struct MSP430ISelAddressMode {
47 struct { // This is really a union, discriminated by BaseType!
55 BlockAddress *BlockAddr;
58 unsigned Align; // CP alignment.
60 MSP430ISelAddressMode()
61 : BaseType(RegBase), Disp(0), GV(0), CP(0), BlockAddr(0),
62 ES(0), JT(-1), Align(0) {
65 bool hasSymbolicDisplacement() const {
66 return GV != 0 || CP != 0 || ES != 0 || JT != -1;
69 bool hasBaseReg() const {
70 return Base.Reg.getNode() != 0;
73 void setBaseReg(SDValue Reg) {
79 errs() << "MSP430ISelAddressMode " << this << '\n';
80 if (BaseType == RegBase && Base.Reg.getNode() != 0) {
81 errs() << "Base.Reg ";
82 Base.Reg.getNode()->dump();
83 } else if (BaseType == FrameIndexBase) {
84 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
86 errs() << " Disp " << Disp << '\n';
93 errs() << " Align" << Align << '\n';
98 errs() << " JT" << JT << " Align" << Align << '\n';
103 /// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
104 /// instructions for SelectionDAG operations.
107 class MSP430DAGToDAGISel : public SelectionDAGISel {
108 MSP430TargetLowering &Lowering;
109 const MSP430Subtarget &Subtarget;
112 MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
113 : SelectionDAGISel(TM, OptLevel),
114 Lowering(*TM.getTargetLowering()),
115 Subtarget(*TM.getSubtargetImpl()) { }
117 virtual void PreprocessISelDAG();
118 virtual void PostprocessISelDAG();
120 virtual const char *getPassName() const {
121 return "MSP430 DAG->DAG Pattern Instruction Selection";
124 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
125 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
126 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
128 bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const;
131 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
132 std::vector<SDValue> &OutOps);
134 // Include the pieces autogenerated from the target description.
135 #include "MSP430GenDAGISel.inc"
138 DenseMap<SDNode*, SDNode*> RMWStores;
139 void PreprocessForRMW();
140 SDNode *Select(SDNode *N);
141 SDNode *SelectIndexedLoad(SDNode *Op);
142 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
143 unsigned Opc8, unsigned Opc16);
145 bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Disp);
147 } // end anonymous namespace
149 /// createMSP430ISelDag - This pass converts a legalized DAG into a
150 /// MSP430-specific DAG, ready for instruction scheduling.
152 FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
153 CodeGenOpt::Level OptLevel) {
154 return new MSP430DAGToDAGISel(TM, OptLevel);
158 /// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
159 /// These wrap things that will resolve down into a symbol reference. If no
160 /// match is possible, this returns true, otherwise it returns false.
161 bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
162 // If the addressing mode already has a symbol as the displacement, we can
163 // never match another symbol.
164 if (AM.hasSymbolicDisplacement())
167 SDValue N0 = N.getOperand(0);
169 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
170 AM.GV = G->getGlobal();
171 AM.Disp += G->getOffset();
172 //AM.SymbolFlags = G->getTargetFlags();
173 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
174 AM.CP = CP->getConstVal();
175 AM.Align = CP->getAlignment();
176 AM.Disp += CP->getOffset();
177 //AM.SymbolFlags = CP->getTargetFlags();
178 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
179 AM.ES = S->getSymbol();
180 //AM.SymbolFlags = S->getTargetFlags();
181 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
182 AM.JT = J->getIndex();
183 //AM.SymbolFlags = J->getTargetFlags();
185 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
186 //AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
191 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
192 /// specified addressing mode without any further recursion.
193 bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) {
194 // Is the base register already occupied?
195 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
196 // If so, we cannot select it.
200 // Default, generate it as a register.
201 AM.BaseType = MSP430ISelAddressMode::RegBase;
206 bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
208 errs() << "MatchAddress: ";
212 switch (N.getOpcode()) {
214 case ISD::Constant: {
215 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
220 case MSP430ISD::Wrapper:
221 if (!MatchWrapper(N, AM))
225 case ISD::FrameIndex:
226 if (AM.BaseType == MSP430ISelAddressMode::RegBase
227 && AM.Base.Reg.getNode() == 0) {
228 AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
229 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
235 MSP430ISelAddressMode Backup = AM;
236 if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
237 !MatchAddress(N.getNode()->getOperand(1), AM))
240 if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
241 !MatchAddress(N.getNode()->getOperand(0), AM))
249 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
250 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
251 MSP430ISelAddressMode Backup = AM;
252 uint64_t Offset = CN->getSExtValue();
253 // Start with the LHS as an addr mode.
254 if (!MatchAddress(N.getOperand(0), AM) &&
255 // Address could not have picked a GV address for the displacement.
257 // Check to see if the LHS & C is zero.
258 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
267 return MatchAddressBase(N, AM);
270 /// SelectAddr - returns true if it is able pattern match an addressing mode.
271 /// It returns the operands which make up the maximal addressing mode it can
272 /// match by reference.
273 bool MSP430DAGToDAGISel::SelectAddr(SDNode *Op, SDValue N,
274 SDValue &Base, SDValue &Disp) {
275 MSP430ISelAddressMode AM;
277 if (MatchAddress(N, AM))
280 EVT VT = N.getValueType();
281 if (AM.BaseType == MSP430ISelAddressMode::RegBase) {
282 if (!AM.Base.Reg.getNode())
283 AM.Base.Reg = CurDAG->getRegister(0, VT);
286 Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase) ?
287 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
291 Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i16, AM.Disp,
292 0/*AM.SymbolFlags*/);
294 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
295 AM.Align, AM.Disp, 0/*AM.SymbolFlags*/);
297 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
298 else if (AM.JT != -1)
299 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
300 else if (AM.BlockAddr)
301 Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32,
302 true, 0/*AM.SymbolFlags*/);
304 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i16);
309 bool MSP430DAGToDAGISel::
310 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
311 std::vector<SDValue> &OutOps) {
313 switch (ConstraintCode) {
314 default: return true;
316 if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
321 OutOps.push_back(Op0);
322 OutOps.push_back(Op1);
326 bool MSP430DAGToDAGISel::IsLegalToFold(SDValue N, SDNode *U,
327 SDNode *Root) const {
328 if (OptLevel == CodeGenOpt::None) return false;
330 /// RMW preprocessing creates the following code:
347 /// The path Store => Load2 => Load1 is via chain. Note that in general it is
348 /// not allowed to fold Load1 into Op (and Store) since it will creates a
349 /// cycle. However, this is perfectly legal for the loads moved below the
350 /// TokenFactor by PreprocessForRMW. Query the map Store => Load1 (created
351 /// during preprocessing) to determine whether it's legal to introduce such
352 /// "cycle" for a moment.
353 DenseMap<SDNode*, SDNode*>::const_iterator I = RMWStores.find(Root);
354 if (I != RMWStores.end() && I->second == N.getNode())
357 // Proceed to 'generic' cycle finder code
358 return SelectionDAGISel::IsLegalToFold(N, U, Root);
362 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
363 /// and move load below the TokenFactor. Replace store's chain operand with
364 /// load's chain result.
365 static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
366 SDValue Store, SDValue TF) {
367 SmallVector<SDValue, 4> Ops;
368 for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
369 if (Load.getNode() == TF.getOperand(i).getNode())
370 Ops.push_back(Load.getOperand(0));
372 Ops.push_back(TF.getOperand(i));
373 SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
374 SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
377 CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
378 Store.getOperand(2), Store.getOperand(3));
381 /// MoveBelowTokenFactor2 - Replace TokenFactor operand with load's chain operand
382 /// and move load below the TokenFactor. Replace store's chain operand with
383 /// load's chain result. This a version which sinks two loads below token factor.
384 /// Look into PreprocessForRMW comments for explanation of transform.
385 static void MoveBelowTokenFactor2(SelectionDAG *CurDAG,
386 SDValue Load1, SDValue Load2,
387 SDValue Store, SDValue TF) {
388 SmallVector<SDValue, 4> Ops;
389 for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i) {
390 SDNode* N = TF.getOperand(i).getNode();
391 if (Load2.getNode() == N)
392 Ops.push_back(Load2.getOperand(0));
393 else if (Load1.getNode() != N)
394 Ops.push_back(TF.getOperand(i));
397 SDValue NewTF = SDValue(CurDAG->MorphNodeTo(TF.getNode(),
399 TF.getNode()->getVTList(),
400 &Ops[0], Ops.size()), TF.getResNo());
401 SDValue NewLoad2 = CurDAG->UpdateNodeOperands(Load2, NewTF,
403 Load2.getOperand(2));
405 SDValue NewLoad1 = CurDAG->UpdateNodeOperands(Load1, NewLoad2.getValue(1),
407 Load1.getOperand(2));
409 CurDAG->UpdateNodeOperands(Store,
410 NewLoad1.getValue(1),
412 Store.getOperand(2), Store.getOperand(3));
415 /// isAllowedToSink - return true if N a load which can be moved below token
416 /// factor. Basically, the load should be non-volatile and has single use.
417 static bool isLoadAllowedToSink(SDValue N, SDValue Chain) {
418 if (N.getOpcode() == ISD::BIT_CONVERT)
421 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
422 if (!LD || LD->isVolatile())
424 if (LD->getAddressingMode() != ISD::UNINDEXED)
427 ISD::LoadExtType ExtType = LD->getExtensionType();
428 if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
431 return (N.hasOneUse() &&
432 LD->hasNUsesOfValue(1, 1) &&
433 LD->isOperandOf(Chain.getNode()));
437 /// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
438 /// The chain produced by the load must only be used by the store's chain
439 /// operand, otherwise this may produce a cycle in the DAG.
440 static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
442 if (isLoadAllowedToSink(N, Chain) &&
443 N.getOperand(1) == Address) {
450 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
451 /// This is only run if not in -O0 mode.
452 /// This allows the instruction selector to pick more read-modify-write
453 /// instructions. This is a common case:
463 /// [TokenFactor] [Op]
470 /// The fact the store's chain operand != load's chain will prevent the
471 /// (store (op (load))) instruction from being selected. We can transform it to:
491 /// We also recognize the case where second operand of Op is load as well and
492 /// move it below token factor as well creating DAG as follows:
516 /// This allows selection of mem-mem instructions. Yay!
518 void MSP430DAGToDAGISel::PreprocessForRMW() {
519 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
520 E = CurDAG->allnodes_end(); I != E; ++I) {
521 if (!ISD::isNON_TRUNCStore(I))
523 SDValue Chain = I->getOperand(0);
525 if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
528 SDValue N1 = I->getOperand(1);
529 SDValue N2 = I->getOperand(2);
530 if ((N1.getValueType().isFloatingPoint() &&
531 !N1.getValueType().isVector()) ||
536 SDValue Load1, Load2;
537 unsigned Opcode = N1.getNode()->getOpcode();
545 SDValue N10 = N1.getOperand(0);
546 SDValue N11 = N1.getOperand(1);
547 if (isRMWLoad(N10, Chain, N2, Load1)) {
548 if (isLoadAllowedToSink(N11, Chain)) {
553 } else if (isRMWLoad(N11, Chain, N2, Load1)) {
554 if (isLoadAllowedToSink(N10, Chain)) {
565 SDValue N10 = N1.getOperand(0);
566 SDValue N11 = N1.getOperand(1);
567 if (isRMWLoad(N10, Chain, N2, Load1)) {
568 if (isLoadAllowedToSink(N11, Chain)) {
578 NumLoadMoved += RModW;
580 MoveBelowTokenFactor(CurDAG, Load1, SDValue(I, 0), Chain);
581 else if (RModW == 2) {
582 MoveBelowTokenFactor2(CurDAG, Load1, Load2, SDValue(I, 0), Chain);
584 RMWStores[Store] = Load2.getNode();
590 static bool isValidIndexedLoad(const LoadSDNode *LD) {
591 ISD::MemIndexedMode AM = LD->getAddressingMode();
592 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
595 EVT VT = LD->getMemoryVT();
597 switch (VT.getSimpleVT().SimpleTy) {
600 if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1)
606 if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2)
617 SDNode *MSP430DAGToDAGISel::SelectIndexedLoad(SDNode *N) {
618 LoadSDNode *LD = cast<LoadSDNode>(N);
619 if (!isValidIndexedLoad(LD))
622 MVT VT = LD->getMemoryVT().getSimpleVT();
625 switch (VT.SimpleTy) {
627 Opcode = MSP430::MOV8rm_POST;
630 Opcode = MSP430::MOV16rm_POST;
636 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(),
637 VT, MVT::i16, MVT::Other,
638 LD->getBasePtr(), LD->getChain());
641 SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op,
642 SDValue N1, SDValue N2,
643 unsigned Opc8, unsigned Opc16) {
644 if (N1.getOpcode() == ISD::LOAD &&
646 IsLegalToFold(N1, Op, Op)) {
647 LoadSDNode *LD = cast<LoadSDNode>(N1);
648 if (!isValidIndexedLoad(LD))
651 MVT VT = LD->getMemoryVT().getSimpleVT();
652 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
653 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
654 MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
655 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
657 CurDAG->SelectNodeTo(Op, Opc,
658 VT, MVT::i16, MVT::Other,
660 cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
662 ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
663 // Transfer writeback.
664 ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
672 void MSP430DAGToDAGISel::PreprocessISelDAG() {
676 void MSP430DAGToDAGISel::PostprocessISelDAG() {
680 SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) {
681 DebugLoc dl = Node->getDebugLoc();
683 // Dump information about the Node being selected
684 DEBUG(errs() << "Selecting: ");
685 DEBUG(Node->dump(CurDAG));
686 DEBUG(errs() << "\n");
688 // If we have a custom node, we already have selected!
689 if (Node->isMachineOpcode()) {
690 DEBUG(errs() << "== ";
696 // Few custom selection stuff.
697 switch (Node->getOpcode()) {
699 case ISD::FrameIndex: {
700 assert(Node->getValueType(0) == MVT::i16);
701 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
702 SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
703 if (Node->hasOneUse())
704 return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16,
705 TFI, CurDAG->getTargetConstant(0, MVT::i16));
706 return CurDAG->getMachineNode(MSP430::ADD16ri, dl, MVT::i16,
707 TFI, CurDAG->getTargetConstant(0, MVT::i16));
710 if (SDNode *ResNode = SelectIndexedLoad(Node))
712 // Other cases are autogenerated.
715 if (SDNode *ResNode =
716 SelectIndexedBinOp(Node,
717 Node->getOperand(0), Node->getOperand(1),
718 MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
720 else if (SDNode *ResNode =
721 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
722 MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
725 // Other cases are autogenerated.
728 if (SDNode *ResNode =
729 SelectIndexedBinOp(Node,
730 Node->getOperand(0), Node->getOperand(1),
731 MSP430::SUB8rm_POST, MSP430::SUB16rm_POST))
734 // Other cases are autogenerated.
737 if (SDNode *ResNode =
738 SelectIndexedBinOp(Node,
739 Node->getOperand(0), Node->getOperand(1),
740 MSP430::AND8rm_POST, MSP430::AND16rm_POST))
742 else if (SDNode *ResNode =
743 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
744 MSP430::AND8rm_POST, MSP430::AND16rm_POST))
747 // Other cases are autogenerated.
750 if (SDNode *ResNode =
751 SelectIndexedBinOp(Node,
752 Node->getOperand(0), Node->getOperand(1),
753 MSP430::OR8rm_POST, MSP430::OR16rm_POST))
755 else if (SDNode *ResNode =
756 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
757 MSP430::OR8rm_POST, MSP430::OR16rm_POST))
760 // Other cases are autogenerated.
763 if (SDNode *ResNode =
764 SelectIndexedBinOp(Node,
765 Node->getOperand(0), Node->getOperand(1),
766 MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
768 else if (SDNode *ResNode =
769 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
770 MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
773 // Other cases are autogenerated.
777 // Select the default instruction
778 SDNode *ResNode = SelectCode(Node);
780 DEBUG(errs() << "=> ");
781 if (ResNode == NULL || ResNode == Node)
782 DEBUG(Node->dump(CurDAG));
784 DEBUG(ResNode->dump(CurDAG));
785 DEBUG(errs() << "\n");