1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MSP430TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "MSP430ISelLowering.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430Subtarget.h"
18 #include "MSP430TargetMachine.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/GlobalAlias.h"
31 #include "llvm/IR/GlobalVariable.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
39 #define DEBUG_TYPE "msp430-lower"
47 static cl::opt<HWMultUseMode>
48 HWMultMode("msp430-hwmult-mode", cl::Hidden,
49 cl::desc("Hardware multiplier use mode"),
50 cl::init(HWMultNoIntr),
52 clEnumValN(NoHWMult, "no",
53 "Do not use hardware multiplier"),
54 clEnumValN(HWMultIntr, "interrupts",
55 "Assume hardware multiplier can be used inside interrupts"),
56 clEnumValN(HWMultNoIntr, "use",
57 "Assume hardware multiplier cannot be used inside interrupts"),
60 MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
61 const MSP430Subtarget &STI)
62 : TargetLowering(TM) {
64 // Set up the register classes.
65 addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
66 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
68 // Compute derived properties from the register classes
69 computeRegisterProperties(STI.getRegisterInfo());
71 // Provide all sorts of operation actions
72 setStackPointerRegisterToSaveRestore(MSP430::SP);
73 setBooleanContents(ZeroOrOneBooleanContent);
74 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
76 // We have post-incremented loads / stores.
77 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
78 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
80 for (MVT VT : MVT::integer_valuetypes()) {
81 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
82 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
83 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
85 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
88 // We don't have any truncstores
89 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
91 setOperationAction(ISD::SRA, MVT::i8, Custom);
92 setOperationAction(ISD::SHL, MVT::i8, Custom);
93 setOperationAction(ISD::SRL, MVT::i8, Custom);
94 setOperationAction(ISD::SRA, MVT::i16, Custom);
95 setOperationAction(ISD::SHL, MVT::i16, Custom);
96 setOperationAction(ISD::SRL, MVT::i16, Custom);
97 setOperationAction(ISD::ROTL, MVT::i8, Expand);
98 setOperationAction(ISD::ROTR, MVT::i8, Expand);
99 setOperationAction(ISD::ROTL, MVT::i16, Expand);
100 setOperationAction(ISD::ROTR, MVT::i16, Expand);
101 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
102 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
103 setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
104 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
105 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
106 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
107 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
108 setOperationAction(ISD::SETCC, MVT::i8, Custom);
109 setOperationAction(ISD::SETCC, MVT::i16, Custom);
110 setOperationAction(ISD::SELECT, MVT::i8, Expand);
111 setOperationAction(ISD::SELECT, MVT::i16, Expand);
112 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
113 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
114 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
115 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
116 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
118 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
119 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
120 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Expand);
121 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
122 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
123 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
124 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Expand);
125 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Expand);
126 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
127 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
129 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
130 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
131 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
132 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
133 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
134 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
136 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
138 // FIXME: Implement efficiently multiplication by a constant
139 setOperationAction(ISD::MUL, MVT::i8, Expand);
140 setOperationAction(ISD::MULHS, MVT::i8, Expand);
141 setOperationAction(ISD::MULHU, MVT::i8, Expand);
142 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
143 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
144 setOperationAction(ISD::MUL, MVT::i16, Expand);
145 setOperationAction(ISD::MULHS, MVT::i16, Expand);
146 setOperationAction(ISD::MULHU, MVT::i16, Expand);
147 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
148 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
150 setOperationAction(ISD::UDIV, MVT::i8, Expand);
151 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
152 setOperationAction(ISD::UREM, MVT::i8, Expand);
153 setOperationAction(ISD::SDIV, MVT::i8, Expand);
154 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
155 setOperationAction(ISD::SREM, MVT::i8, Expand);
156 setOperationAction(ISD::UDIV, MVT::i16, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
158 setOperationAction(ISD::UREM, MVT::i16, Expand);
159 setOperationAction(ISD::SDIV, MVT::i16, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
161 setOperationAction(ISD::SREM, MVT::i16, Expand);
164 setOperationAction(ISD::VASTART, MVT::Other, Custom);
165 setOperationAction(ISD::VAARG, MVT::Other, Expand);
166 setOperationAction(ISD::VAEND, MVT::Other, Expand);
167 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
168 setOperationAction(ISD::JumpTable, MVT::i16, Custom);
171 if (HWMultMode == HWMultIntr) {
172 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw");
173 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
174 } else if (HWMultMode == HWMultNoIntr) {
175 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw_noint");
176 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
179 setMinFunctionAlignment(1);
180 setPrefFunctionAlignment(2);
183 SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
184 SelectionDAG &DAG) const {
185 switch (Op.getOpcode()) {
186 case ISD::SHL: // FALLTHROUGH
188 case ISD::SRA: return LowerShifts(Op, DAG);
189 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
190 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
191 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
192 case ISD::SETCC: return LowerSETCC(Op, DAG);
193 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
194 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
195 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
196 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
197 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
198 case ISD::VASTART: return LowerVASTART(Op, DAG);
199 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
201 llvm_unreachable("unimplemented operand");
205 //===----------------------------------------------------------------------===//
206 // MSP430 Inline Assembly Support
207 //===----------------------------------------------------------------------===//
209 /// getConstraintType - Given a constraint letter, return the type of
210 /// constraint it is for this target.
211 TargetLowering::ConstraintType
212 MSP430TargetLowering::getConstraintType(StringRef Constraint) const {
213 if (Constraint.size() == 1) {
214 switch (Constraint[0]) {
216 return C_RegisterClass;
221 return TargetLowering::getConstraintType(Constraint);
224 std::pair<unsigned, const TargetRegisterClass *>
225 MSP430TargetLowering::getRegForInlineAsmConstraint(
226 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
227 if (Constraint.size() == 1) {
228 // GCC Constraint Letters
229 switch (Constraint[0]) {
231 case 'r': // GENERAL_REGS
233 return std::make_pair(0U, &MSP430::GR8RegClass);
235 return std::make_pair(0U, &MSP430::GR16RegClass);
239 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
242 //===----------------------------------------------------------------------===//
243 // Calling Convention Implementation
244 //===----------------------------------------------------------------------===//
246 #include "MSP430GenCallingConv.inc"
248 /// For each argument in a function store the number of pieces it is composed
250 template<typename ArgT>
251 static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args,
252 SmallVectorImpl<unsigned> &Out) {
253 unsigned CurrentArgIndex = ~0U;
254 for (unsigned i = 0, e = Args.size(); i != e; i++) {
255 if (CurrentArgIndex == Args[i].OrigArgIndex) {
264 static void AnalyzeVarArgs(CCState &State,
265 const SmallVectorImpl<ISD::OutputArg> &Outs) {
266 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
269 static void AnalyzeVarArgs(CCState &State,
270 const SmallVectorImpl<ISD::InputArg> &Ins) {
271 State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
274 /// Analyze incoming and outgoing function arguments. We need custom C++ code
275 /// to handle special constraints in the ABI like reversing the order of the
276 /// pieces of splitted arguments. In addition, all pieces of a certain argument
277 /// have to be passed either using registers or the stack but never mixing both.
278 template<typename ArgT>
279 static void AnalyzeArguments(CCState &State,
280 SmallVectorImpl<CCValAssign> &ArgLocs,
281 const SmallVectorImpl<ArgT> &Args) {
282 static const MCPhysReg RegList[] = {
283 MSP430::R15, MSP430::R14, MSP430::R13, MSP430::R12
285 static const unsigned NbRegs = array_lengthof(RegList);
287 if (State.isVarArg()) {
288 AnalyzeVarArgs(State, Args);
292 SmallVector<unsigned, 4> ArgsParts;
293 ParseFunctionArgs(Args, ArgsParts);
295 unsigned RegsLeft = NbRegs;
296 bool UseStack = false;
299 for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
300 MVT ArgVT = Args[ValNo].VT;
301 ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
303 CCValAssign::LocInfo LocInfo = CCValAssign::Full;
306 if (LocVT == MVT::i8) {
308 if (ArgFlags.isSExt())
309 LocInfo = CCValAssign::SExt;
310 else if (ArgFlags.isZExt())
311 LocInfo = CCValAssign::ZExt;
313 LocInfo = CCValAssign::AExt;
316 // Handle byval arguments
317 if (ArgFlags.isByVal()) {
318 State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
322 unsigned Parts = ArgsParts[i];
324 if (!UseStack && Parts <= RegsLeft) {
325 unsigned FirstVal = ValNo;
326 for (unsigned j = 0; j < Parts; j++) {
327 unsigned Reg = State.AllocateReg(RegList);
328 State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
332 // Reverse the order of the pieces to agree with the "big endian" format
333 // required in the calling convention ABI.
334 SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal;
335 std::reverse(B, B + Parts);
338 for (unsigned j = 0; j < Parts; j++)
339 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
344 static void AnalyzeRetResult(CCState &State,
345 const SmallVectorImpl<ISD::InputArg> &Ins) {
346 State.AnalyzeCallResult(Ins, RetCC_MSP430);
349 static void AnalyzeRetResult(CCState &State,
350 const SmallVectorImpl<ISD::OutputArg> &Outs) {
351 State.AnalyzeReturn(Outs, RetCC_MSP430);
354 template<typename ArgT>
355 static void AnalyzeReturnValues(CCState &State,
356 SmallVectorImpl<CCValAssign> &RVLocs,
357 const SmallVectorImpl<ArgT> &Args) {
358 AnalyzeRetResult(State, Args);
360 // Reverse splitted return values to get the "big endian" format required
361 // to agree with the calling convention ABI.
362 std::reverse(RVLocs.begin(), RVLocs.end());
366 MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
367 CallingConv::ID CallConv,
369 const SmallVectorImpl<ISD::InputArg>
373 SmallVectorImpl<SDValue> &InVals)
378 llvm_unreachable("Unsupported calling convention");
380 case CallingConv::Fast:
381 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
382 case CallingConv::MSP430_INTR:
385 report_fatal_error("ISRs cannot have arguments");
390 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
391 SmallVectorImpl<SDValue> &InVals) const {
392 SelectionDAG &DAG = CLI.DAG;
394 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
395 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
396 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
397 SDValue Chain = CLI.Chain;
398 SDValue Callee = CLI.Callee;
399 bool &isTailCall = CLI.IsTailCall;
400 CallingConv::ID CallConv = CLI.CallConv;
401 bool isVarArg = CLI.IsVarArg;
403 // MSP430 target does not yet support tail call optimization.
408 llvm_unreachable("Unsupported calling convention");
409 case CallingConv::Fast:
411 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
412 Outs, OutVals, Ins, dl, DAG, InVals);
413 case CallingConv::MSP430_INTR:
414 report_fatal_error("ISRs cannot be called directly");
418 /// LowerCCCArguments - transform physical registers into virtual registers and
419 /// generate load operations for arguments places on the stack.
420 // FIXME: struct return stuff
422 MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
423 CallingConv::ID CallConv,
425 const SmallVectorImpl<ISD::InputArg>
429 SmallVectorImpl<SDValue> &InVals)
431 MachineFunction &MF = DAG.getMachineFunction();
432 MachineFrameInfo *MFI = MF.getFrameInfo();
433 MachineRegisterInfo &RegInfo = MF.getRegInfo();
434 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
436 // Assign locations to all of the incoming arguments.
437 SmallVector<CCValAssign, 16> ArgLocs;
438 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
440 AnalyzeArguments(CCInfo, ArgLocs, Ins);
442 // Create frame index for the start of the first vararg value
444 unsigned Offset = CCInfo.getNextStackOffset();
445 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, Offset, true));
448 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
449 CCValAssign &VA = ArgLocs[i];
451 // Arguments passed in registers
452 EVT RegVT = VA.getLocVT();
453 switch (RegVT.getSimpleVT().SimpleTy) {
457 errs() << "LowerFormalArguments Unhandled argument type: "
458 << RegVT.getSimpleVT().SimpleTy << "\n";
460 llvm_unreachable(nullptr);
463 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
464 RegInfo.addLiveIn(VA.getLocReg(), VReg);
465 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
467 // If this is an 8-bit value, it is really passed promoted to 16
468 // bits. Insert an assert[sz]ext to capture this, then truncate to the
470 if (VA.getLocInfo() == CCValAssign::SExt)
471 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
472 DAG.getValueType(VA.getValVT()));
473 else if (VA.getLocInfo() == CCValAssign::ZExt)
474 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
475 DAG.getValueType(VA.getValVT()));
477 if (VA.getLocInfo() != CCValAssign::Full)
478 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
480 InVals.push_back(ArgValue);
484 assert(VA.isMemLoc());
487 ISD::ArgFlagsTy Flags = Ins[i].Flags;
489 if (Flags.isByVal()) {
490 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
491 VA.getLocMemOffset(), true);
492 InVal = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
494 // Load the argument to a virtual register
495 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
497 errs() << "LowerFormalArguments Unhandled argument type: "
498 << EVT(VA.getLocVT()).getEVTString()
501 // Create the frame index object for this incoming parameter...
502 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
504 // Create the SelectionDAG nodes corresponding to a load
505 //from this parameter
506 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
508 VA.getLocVT(), dl, Chain, FIN,
509 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
510 false, false, false, 0);
513 InVals.push_back(InVal);
521 MSP430TargetLowering::LowerReturn(SDValue Chain,
522 CallingConv::ID CallConv, bool isVarArg,
523 const SmallVectorImpl<ISD::OutputArg> &Outs,
524 const SmallVectorImpl<SDValue> &OutVals,
525 SDLoc dl, SelectionDAG &DAG) const {
527 // CCValAssign - represent the assignment of the return value to a location
528 SmallVector<CCValAssign, 16> RVLocs;
530 // ISRs cannot return any value.
531 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
532 report_fatal_error("ISRs cannot return any value");
534 // CCState - Info about the registers and stack slot.
535 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
538 // Analize return values.
539 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
542 SmallVector<SDValue, 4> RetOps(1, Chain);
544 // Copy the result values into the output registers.
545 for (unsigned i = 0; i != RVLocs.size(); ++i) {
546 CCValAssign &VA = RVLocs[i];
547 assert(VA.isRegLoc() && "Can only return in registers!");
549 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
552 // Guarantee that all emitted copies are stuck together,
553 // avoiding something bad.
554 Flag = Chain.getValue(1);
555 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
558 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
559 MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
561 RetOps[0] = Chain; // Update chain.
563 // Add the flag if we have it.
565 RetOps.push_back(Flag);
567 return DAG.getNode(Opc, dl, MVT::Other, RetOps);
570 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
571 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
574 MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
575 CallingConv::ID CallConv, bool isVarArg,
577 const SmallVectorImpl<ISD::OutputArg>
579 const SmallVectorImpl<SDValue> &OutVals,
580 const SmallVectorImpl<ISD::InputArg> &Ins,
581 SDLoc dl, SelectionDAG &DAG,
582 SmallVectorImpl<SDValue> &InVals) const {
583 // Analyze operands of the call, assigning locations to each operand.
584 SmallVector<CCValAssign, 16> ArgLocs;
585 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
587 AnalyzeArguments(CCInfo, ArgLocs, Outs);
589 // Get a count of how many bytes are to be pushed on the stack.
590 unsigned NumBytes = CCInfo.getNextStackOffset();
591 auto PtrVT = getPointerTy(DAG.getDataLayout());
593 Chain = DAG.getCALLSEQ_START(Chain,
594 DAG.getConstant(NumBytes, dl, PtrVT, true), dl);
596 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
597 SmallVector<SDValue, 12> MemOpChains;
600 // Walk the register/memloc assignments, inserting copies/loads.
601 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
602 CCValAssign &VA = ArgLocs[i];
604 SDValue Arg = OutVals[i];
606 // Promote the value if needed.
607 switch (VA.getLocInfo()) {
608 default: llvm_unreachable("Unknown loc info!");
609 case CCValAssign::Full: break;
610 case CCValAssign::SExt:
611 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
613 case CCValAssign::ZExt:
614 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
616 case CCValAssign::AExt:
617 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
621 // Arguments that can be passed on register must be kept at RegsToPass
624 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
626 assert(VA.isMemLoc());
628 if (!StackPtr.getNode())
629 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT);
632 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
633 DAG.getIntPtrConstant(VA.getLocMemOffset(), dl));
636 ISD::ArgFlagsTy Flags = Outs[i].Flags;
638 if (Flags.isByVal()) {
639 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16);
640 MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
641 Flags.getByValAlign(),
643 /*AlwaysInline=*/true,
644 /*isTailCall=*/false,
645 MachinePointerInfo(),
646 MachinePointerInfo());
648 MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(),
652 MemOpChains.push_back(MemOp);
656 // Transform all store nodes into one single node because all store nodes are
657 // independent of each other.
658 if (!MemOpChains.empty())
659 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
661 // Build a sequence of copy-to-reg nodes chained together with token chain and
662 // flag operands which copy the outgoing args into registers. The InFlag in
663 // necessary since all emitted instructions must be stuck together.
665 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
666 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
667 RegsToPass[i].second, InFlag);
668 InFlag = Chain.getValue(1);
671 // If the callee is a GlobalAddress node (quite common, every direct call is)
672 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
673 // Likewise ExternalSymbol -> TargetExternalSymbol.
674 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
675 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
676 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
677 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
679 // Returns a chain & a flag for retval copy to use.
680 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
681 SmallVector<SDValue, 8> Ops;
682 Ops.push_back(Chain);
683 Ops.push_back(Callee);
685 // Add argument registers to the end of the list so that they are
686 // known live into the call.
687 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
688 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
689 RegsToPass[i].second.getValueType()));
691 if (InFlag.getNode())
692 Ops.push_back(InFlag);
694 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
695 InFlag = Chain.getValue(1);
697 // Create the CALLSEQ_END node.
698 Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
699 DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
700 InFlag = Chain.getValue(1);
702 // Handle result values, copying them out of physregs into vregs that we
704 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
708 /// LowerCallResult - Lower the result values of a call into the
709 /// appropriate copies out of appropriate physical registers.
712 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
713 CallingConv::ID CallConv, bool isVarArg,
714 const SmallVectorImpl<ISD::InputArg> &Ins,
715 SDLoc dl, SelectionDAG &DAG,
716 SmallVectorImpl<SDValue> &InVals) const {
718 // Assign locations to each value returned by this call.
719 SmallVector<CCValAssign, 16> RVLocs;
720 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
723 AnalyzeReturnValues(CCInfo, RVLocs, Ins);
725 // Copy all of the result registers out of their specified physreg.
726 for (unsigned i = 0; i != RVLocs.size(); ++i) {
727 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
728 RVLocs[i].getValVT(), InFlag).getValue(1);
729 InFlag = Chain.getValue(2);
730 InVals.push_back(Chain.getValue(0));
736 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
737 SelectionDAG &DAG) const {
738 unsigned Opc = Op.getOpcode();
739 SDNode* N = Op.getNode();
740 EVT VT = Op.getValueType();
743 // Expand non-constant shifts to loops:
744 if (!isa<ConstantSDNode>(N->getOperand(1)))
746 default: llvm_unreachable("Invalid shift opcode!");
748 return DAG.getNode(MSP430ISD::SHL, dl,
749 VT, N->getOperand(0), N->getOperand(1));
751 return DAG.getNode(MSP430ISD::SRA, dl,
752 VT, N->getOperand(0), N->getOperand(1));
754 return DAG.getNode(MSP430ISD::SRL, dl,
755 VT, N->getOperand(0), N->getOperand(1));
758 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
760 // Expand the stuff into sequence of shifts.
761 // FIXME: for some shift amounts this might be done better!
762 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
763 SDValue Victim = N->getOperand(0);
765 if (Opc == ISD::SRL && ShiftAmount) {
766 // Emit a special goodness here:
767 // srl A, 1 => clrc; rrc A
768 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
772 while (ShiftAmount--)
773 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
779 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
780 SelectionDAG &DAG) const {
781 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
782 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
783 auto PtrVT = getPointerTy(DAG.getDataLayout());
785 // Create the TargetGlobalAddress node, folding in the constant offset.
786 SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset);
787 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result);
790 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
791 SelectionDAG &DAG) const {
793 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
794 auto PtrVT = getPointerTy(DAG.getDataLayout());
795 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT);
797 return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
800 SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
801 SelectionDAG &DAG) const {
803 auto PtrVT = getPointerTy(DAG.getDataLayout());
804 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
805 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
807 return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
810 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
812 SDLoc dl, SelectionDAG &DAG) {
813 // FIXME: Handle bittests someday
814 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
816 // FIXME: Handle jump negative someday
817 MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
819 default: llvm_unreachable("Invalid integer condition!");
821 TCC = MSP430CC::COND_E; // aka COND_Z
822 // Minor optimization: if LHS is a constant, swap operands, then the
823 // constant can be folded into comparison.
824 if (LHS.getOpcode() == ISD::Constant)
828 TCC = MSP430CC::COND_NE; // aka COND_NZ
829 // Minor optimization: if LHS is a constant, swap operands, then the
830 // constant can be folded into comparison.
831 if (LHS.getOpcode() == ISD::Constant)
835 std::swap(LHS, RHS); // FALLTHROUGH
837 // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
838 // fold constant into instruction.
839 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
841 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
842 TCC = MSP430CC::COND_LO;
845 TCC = MSP430CC::COND_HS; // aka COND_C
848 std::swap(LHS, RHS); // FALLTHROUGH
850 // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
851 // fold constant into instruction.
852 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
854 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
855 TCC = MSP430CC::COND_HS;
858 TCC = MSP430CC::COND_LO; // aka COND_NC
861 std::swap(LHS, RHS); // FALLTHROUGH
863 // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
864 // fold constant into instruction.
865 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
867 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
868 TCC = MSP430CC::COND_L;
871 TCC = MSP430CC::COND_GE;
874 std::swap(LHS, RHS); // FALLTHROUGH
876 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
877 // fold constant into instruction.
878 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
880 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
881 TCC = MSP430CC::COND_GE;
884 TCC = MSP430CC::COND_L;
888 TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
889 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
893 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
894 SDValue Chain = Op.getOperand(0);
895 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
896 SDValue LHS = Op.getOperand(2);
897 SDValue RHS = Op.getOperand(3);
898 SDValue Dest = Op.getOperand(4);
902 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
904 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
905 Chain, Dest, TargetCC, Flag);
908 SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
909 SDValue LHS = Op.getOperand(0);
910 SDValue RHS = Op.getOperand(1);
913 // If we are doing an AND and testing against zero, then the CMP
914 // will not be generated. The AND (or BIT) will generate the condition codes,
915 // but they are different from CMP.
916 // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
917 // lowering & isel wouldn't diverge.
919 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
920 if (RHSC->isNullValue() && LHS.hasOneUse() &&
921 (LHS.getOpcode() == ISD::AND ||
922 (LHS.getOpcode() == ISD::TRUNCATE &&
923 LHS.getOperand(0).getOpcode() == ISD::AND))) {
927 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
929 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
931 // Get the condition codes directly from the status register, if its easy.
932 // Otherwise a branch will be generated. Note that the AND and BIT
933 // instructions generate different flags than CMP, the carry bit can be used
938 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
942 case MSP430CC::COND_HS:
943 // Res = SR & 1, no processing is required
945 case MSP430CC::COND_LO:
949 case MSP430CC::COND_NE:
951 // C = ~Z, thus Res = SR & 1, no processing is required
953 // Res = ~((SR >> 1) & 1)
958 case MSP430CC::COND_E:
960 // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
961 // Res = (SR >> 1) & 1 is 1 word shorter.
964 EVT VT = Op.getValueType();
965 SDValue One = DAG.getConstant(1, dl, VT);
967 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
970 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
971 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
972 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
974 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
977 SDValue Zero = DAG.getConstant(0, dl, VT);
978 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
979 SDValue Ops[] = {One, Zero, TargetCC, Flag};
980 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
984 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
985 SelectionDAG &DAG) const {
986 SDValue LHS = Op.getOperand(0);
987 SDValue RHS = Op.getOperand(1);
988 SDValue TrueV = Op.getOperand(2);
989 SDValue FalseV = Op.getOperand(3);
990 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
994 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
996 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
997 SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
999 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1002 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
1003 SelectionDAG &DAG) const {
1004 SDValue Val = Op.getOperand(0);
1005 EVT VT = Op.getValueType();
1008 assert(VT == MVT::i16 && "Only support i16 for now!");
1010 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1011 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1012 DAG.getValueType(Val.getValueType()));
1016 MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
1017 MachineFunction &MF = DAG.getMachineFunction();
1018 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1019 int ReturnAddrIndex = FuncInfo->getRAIndex();
1020 auto PtrVT = getPointerTy(MF.getDataLayout());
1022 if (ReturnAddrIndex == 0) {
1023 // Set up a frame object for the return address.
1024 uint64_t SlotSize = MF.getDataLayout().getPointerSize();
1025 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
1027 FuncInfo->setRAIndex(ReturnAddrIndex);
1030 return DAG.getFrameIndex(ReturnAddrIndex, PtrVT);
1033 SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
1034 SelectionDAG &DAG) const {
1035 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1036 MFI->setReturnAddressIsTaken(true);
1038 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1041 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1043 auto PtrVT = getPointerTy(DAG.getDataLayout());
1046 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1048 DAG.getConstant(DAG.getDataLayout().getPointerSize(), dl, MVT::i16);
1049 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1050 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1051 MachinePointerInfo(), false, false, false, 0);
1054 // Just load the return address.
1055 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1056 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
1057 MachinePointerInfo(), false, false, false, 0);
1060 SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
1061 SelectionDAG &DAG) const {
1062 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1063 MFI->setFrameAddressIsTaken(true);
1065 EVT VT = Op.getValueType();
1066 SDLoc dl(Op); // FIXME probably not meaningful
1067 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1068 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1071 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1072 MachinePointerInfo(),
1073 false, false, false, 0);
1077 SDValue MSP430TargetLowering::LowerVASTART(SDValue Op,
1078 SelectionDAG &DAG) const {
1079 MachineFunction &MF = DAG.getMachineFunction();
1080 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1081 auto PtrVT = getPointerTy(DAG.getDataLayout());
1083 // Frame index of first vararg argument
1084 SDValue FrameIndex =
1085 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1086 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1088 // Create a store of the frame index to the location operand
1089 return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex,
1090 Op.getOperand(1), MachinePointerInfo(SV),
1094 SDValue MSP430TargetLowering::LowerJumpTable(SDValue Op,
1095 SelectionDAG &DAG) const {
1096 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1097 auto PtrVT = getPointerTy(DAG.getDataLayout());
1098 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1099 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result);
1102 /// getPostIndexedAddressParts - returns true by value, base pointer and
1103 /// offset pointer and addressing mode by reference if this node can be
1104 /// combined with a load / store to form a post-indexed load / store.
1105 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1108 ISD::MemIndexedMode &AM,
1109 SelectionDAG &DAG) const {
1111 LoadSDNode *LD = cast<LoadSDNode>(N);
1112 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1115 EVT VT = LD->getMemoryVT();
1116 if (VT != MVT::i8 && VT != MVT::i16)
1119 if (Op->getOpcode() != ISD::ADD)
1122 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1123 uint64_t RHSC = RHS->getZExtValue();
1124 if ((VT == MVT::i16 && RHSC != 2) ||
1125 (VT == MVT::i8 && RHSC != 1))
1128 Base = Op->getOperand(0);
1129 Offset = DAG.getConstant(RHSC, SDLoc(N), VT);
1138 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1139 switch ((MSP430ISD::NodeType)Opcode) {
1140 case MSP430ISD::FIRST_NUMBER: break;
1141 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
1142 case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG";
1143 case MSP430ISD::RRA: return "MSP430ISD::RRA";
1144 case MSP430ISD::RLA: return "MSP430ISD::RLA";
1145 case MSP430ISD::RRC: return "MSP430ISD::RRC";
1146 case MSP430ISD::CALL: return "MSP430ISD::CALL";
1147 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
1148 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
1149 case MSP430ISD::CMP: return "MSP430ISD::CMP";
1150 case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
1151 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
1152 case MSP430ISD::SHL: return "MSP430ISD::SHL";
1153 case MSP430ISD::SRA: return "MSP430ISD::SRA";
1154 case MSP430ISD::SRL: return "MSP430ISD::SRL";
1159 bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
1161 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1164 return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1167 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1168 if (!VT1.isInteger() || !VT2.isInteger())
1171 return (VT1.getSizeInBits() > VT2.getSizeInBits());
1174 bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1175 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1176 return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1179 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1180 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1181 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1184 bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
1185 return isZExtFree(Val.getValueType(), VT2);
1188 //===----------------------------------------------------------------------===//
1189 // Other Lowering Code
1190 //===----------------------------------------------------------------------===//
1193 MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1194 MachineBasicBlock *BB) const {
1195 MachineFunction *F = BB->getParent();
1196 MachineRegisterInfo &RI = F->getRegInfo();
1197 DebugLoc dl = MI->getDebugLoc();
1198 const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo();
1201 const TargetRegisterClass * RC;
1202 switch (MI->getOpcode()) {
1203 default: llvm_unreachable("Invalid shift opcode!");
1205 Opc = MSP430::SHL8r1;
1206 RC = &MSP430::GR8RegClass;
1209 Opc = MSP430::SHL16r1;
1210 RC = &MSP430::GR16RegClass;
1213 Opc = MSP430::SAR8r1;
1214 RC = &MSP430::GR8RegClass;
1217 Opc = MSP430::SAR16r1;
1218 RC = &MSP430::GR16RegClass;
1221 Opc = MSP430::SAR8r1c;
1222 RC = &MSP430::GR8RegClass;
1225 Opc = MSP430::SAR16r1c;
1226 RC = &MSP430::GR16RegClass;
1230 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1231 MachineFunction::iterator I = ++BB->getIterator();
1233 // Create loop block
1234 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1235 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1237 F->insert(I, LoopBB);
1238 F->insert(I, RemBB);
1240 // Update machine-CFG edges by transferring all successors of the current
1241 // block to the block containing instructions after shift.
1242 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1244 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1246 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1247 BB->addSuccessor(LoopBB);
1248 BB->addSuccessor(RemBB);
1249 LoopBB->addSuccessor(RemBB);
1250 LoopBB->addSuccessor(LoopBB);
1252 unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1253 unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1254 unsigned ShiftReg = RI.createVirtualRegister(RC);
1255 unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1256 unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1257 unsigned SrcReg = MI->getOperand(1).getReg();
1258 unsigned DstReg = MI->getOperand(0).getReg();
1263 BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1264 .addReg(ShiftAmtSrcReg).addImm(0);
1265 BuildMI(BB, dl, TII.get(MSP430::JCC))
1267 .addImm(MSP430CC::COND_E);
1270 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1271 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1272 // ShiftReg2 = shift ShiftReg
1273 // ShiftAmt2 = ShiftAmt - 1;
1274 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1275 .addReg(SrcReg).addMBB(BB)
1276 .addReg(ShiftReg2).addMBB(LoopBB);
1277 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1278 .addReg(ShiftAmtSrcReg).addMBB(BB)
1279 .addReg(ShiftAmtReg2).addMBB(LoopBB);
1280 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1282 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1283 .addReg(ShiftAmtReg).addImm(1);
1284 BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1286 .addImm(MSP430CC::COND_NE);
1289 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1290 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1291 .addReg(SrcReg).addMBB(BB)
1292 .addReg(ShiftReg2).addMBB(LoopBB);
1294 MI->eraseFromParent(); // The pseudo instruction is gone now.
1299 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1300 MachineBasicBlock *BB) const {
1301 unsigned Opc = MI->getOpcode();
1303 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1304 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1305 Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1306 return EmitShiftInstr(MI, BB);
1308 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1309 DebugLoc dl = MI->getDebugLoc();
1311 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1312 "Unexpected instr type to insert");
1314 // To "insert" a SELECT instruction, we actually have to insert the diamond
1315 // control-flow pattern. The incoming instruction knows the destination vreg
1316 // to set, the condition code register to branch on, the true/false values to
1317 // select between, and a branch opcode to use.
1318 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1319 MachineFunction::iterator I = ++BB->getIterator();
1324 // cmpTY ccX, r1, r2
1326 // fallthrough --> copy0MBB
1327 MachineBasicBlock *thisMBB = BB;
1328 MachineFunction *F = BB->getParent();
1329 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1330 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1331 F->insert(I, copy0MBB);
1332 F->insert(I, copy1MBB);
1333 // Update machine-CFG edges by transferring all successors of the current
1334 // block to the new block which will contain the Phi node for the select.
1335 copy1MBB->splice(copy1MBB->begin(), BB,
1336 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1337 copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1338 // Next, add the true and fallthrough blocks as its successors.
1339 BB->addSuccessor(copy0MBB);
1340 BB->addSuccessor(copy1MBB);
1342 BuildMI(BB, dl, TII.get(MSP430::JCC))
1344 .addImm(MI->getOperand(3).getImm());
1347 // %FalseValue = ...
1348 // # fallthrough to copy1MBB
1351 // Update machine-CFG edges
1352 BB->addSuccessor(copy1MBB);
1355 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1358 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1359 MI->getOperand(0).getReg())
1360 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1361 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1363 MI->eraseFromParent(); // The pseudo instruction is gone now.