1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MSP430TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "msp430-lower"
16 #include "MSP430ISelLowering.h"
18 #include "MSP430MachineFunctionInfo.h"
19 #include "MSP430TargetMachine.h"
20 #include "MSP430Subtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/GlobalAlias.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/PseudoSourceValue.h"
33 #include "llvm/CodeGen/SelectionDAGISel.h"
34 #include "llvm/CodeGen/ValueTypes.h"
35 #include "llvm/Target/TargetLoweringObjectFile.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/ADT/VectorExtras.h"
49 static cl::opt<HWMultUseMode>
50 HWMultMode("msp430-hwmult-mode",
51 cl::desc("Hardware multiplier use mode"),
52 cl::init(HWMultNoIntr),
54 clEnumValN(NoHWMult, "no",
55 "Do not use hardware multiplier"),
56 clEnumValN(HWMultIntr, "interrupts",
57 "Assume hardware multiplier can be used inside interrupts"),
58 clEnumValN(HWMultNoIntr, "use",
59 "Assume hardware multiplier cannot be used inside interrupts"),
62 MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
63 TargetLowering(tm, new TargetLoweringObjectFileELF()),
64 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
68 // Set up the register classes.
69 addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
70 addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
72 // Compute derived properties from the register classes
73 computeRegisterProperties();
75 // Provide all sorts of operation actions
77 // Division is expensive
78 setIntDivIsCheap(false);
80 // Even if we have only 1 bit shift here, we can perform
81 // shifts of the whole bitwidth 1 bit per step.
82 setShiftAmountType(MVT::i8);
84 setStackPointerRegisterToSaveRestore(MSP430::SPW);
85 setBooleanContents(ZeroOrOneBooleanContent);
86 setSchedulingPreference(SchedulingForLatency);
88 // We have post-incremented loads / stores.
89 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
90 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
92 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
93 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
94 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
95 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
96 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
98 // We don't have any truncstores
99 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
101 setOperationAction(ISD::SRA, MVT::i8, Custom);
102 setOperationAction(ISD::SHL, MVT::i8, Custom);
103 setOperationAction(ISD::SRL, MVT::i8, Custom);
104 setOperationAction(ISD::SRA, MVT::i16, Custom);
105 setOperationAction(ISD::SHL, MVT::i16, Custom);
106 setOperationAction(ISD::SRL, MVT::i16, Custom);
107 setOperationAction(ISD::ROTL, MVT::i8, Expand);
108 setOperationAction(ISD::ROTR, MVT::i8, Expand);
109 setOperationAction(ISD::ROTL, MVT::i16, Expand);
110 setOperationAction(ISD::ROTR, MVT::i16, Expand);
111 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
112 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
114 setOperationAction(ISD::BRIND, MVT::Other, Expand);
115 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
116 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
117 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
118 setOperationAction(ISD::SETCC, MVT::i8, Custom);
119 setOperationAction(ISD::SETCC, MVT::i16, Custom);
120 setOperationAction(ISD::SELECT, MVT::i8, Expand);
121 setOperationAction(ISD::SELECT, MVT::i16, Expand);
122 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
123 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
124 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
125 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
126 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
128 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
129 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
130 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
131 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
132 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
133 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
135 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
136 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
137 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
138 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
139 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
140 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
142 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
144 // FIXME: Implement efficiently multiplication by a constant
145 setOperationAction(ISD::MUL, MVT::i8, Expand);
146 setOperationAction(ISD::MULHS, MVT::i8, Expand);
147 setOperationAction(ISD::MULHU, MVT::i8, Expand);
148 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
149 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
150 setOperationAction(ISD::MUL, MVT::i16, Expand);
151 setOperationAction(ISD::MULHS, MVT::i16, Expand);
152 setOperationAction(ISD::MULHU, MVT::i16, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
156 setOperationAction(ISD::UDIV, MVT::i8, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
158 setOperationAction(ISD::UREM, MVT::i8, Expand);
159 setOperationAction(ISD::SDIV, MVT::i8, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
161 setOperationAction(ISD::SREM, MVT::i8, Expand);
162 setOperationAction(ISD::UDIV, MVT::i16, Expand);
163 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
164 setOperationAction(ISD::UREM, MVT::i16, Expand);
165 setOperationAction(ISD::SDIV, MVT::i16, Expand);
166 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
167 setOperationAction(ISD::SREM, MVT::i16, Expand);
170 if (HWMultMode == HWMultIntr) {
171 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw");
172 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
173 } else if (HWMultMode == HWMultNoIntr) {
174 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw_noint");
175 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
179 SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
180 switch (Op.getOpcode()) {
181 case ISD::SHL: // FALLTHROUGH
183 case ISD::SRA: return LowerShifts(Op, DAG);
184 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
185 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
186 case ISD::SETCC: return LowerSETCC(Op, DAG);
187 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
188 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
189 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
190 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
191 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
193 llvm_unreachable("unimplemented operand");
198 /// getFunctionAlignment - Return the Log2 alignment of this function.
199 unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
200 return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 2;
203 //===----------------------------------------------------------------------===//
204 // MSP430 Inline Assembly Support
205 //===----------------------------------------------------------------------===//
207 /// getConstraintType - Given a constraint letter, return the type of
208 /// constraint it is for this target.
209 TargetLowering::ConstraintType
210 MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
211 if (Constraint.size() == 1) {
212 switch (Constraint[0]) {
214 return C_RegisterClass;
219 return TargetLowering::getConstraintType(Constraint);
222 std::pair<unsigned, const TargetRegisterClass*>
223 MSP430TargetLowering::
224 getRegForInlineAsmConstraint(const std::string &Constraint,
226 if (Constraint.size() == 1) {
227 // GCC Constraint Letters
228 switch (Constraint[0]) {
230 case 'r': // GENERAL_REGS
232 return std::make_pair(0U, MSP430::GR8RegisterClass);
234 return std::make_pair(0U, MSP430::GR16RegisterClass);
238 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
241 //===----------------------------------------------------------------------===//
242 // Calling Convention Implementation
243 //===----------------------------------------------------------------------===//
245 #include "MSP430GenCallingConv.inc"
248 MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
249 CallingConv::ID CallConv,
251 const SmallVectorImpl<ISD::InputArg>
255 SmallVectorImpl<SDValue> &InVals) {
259 llvm_unreachable("Unsupported calling convention");
261 case CallingConv::Fast:
262 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
263 case CallingConv::MSP430_INTR:
267 llvm_report_error("ISRs cannot have arguments");
274 MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
275 CallingConv::ID CallConv, bool isVarArg,
277 const SmallVectorImpl<ISD::OutputArg> &Outs,
278 const SmallVectorImpl<ISD::InputArg> &Ins,
279 DebugLoc dl, SelectionDAG &DAG,
280 SmallVectorImpl<SDValue> &InVals) {
284 llvm_unreachable("Unsupported calling convention");
285 case CallingConv::Fast:
287 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
288 Outs, Ins, dl, DAG, InVals);
289 case CallingConv::MSP430_INTR:
290 llvm_report_error("ISRs cannot be called directly");
295 /// LowerCCCArguments - transform physical registers into virtual registers and
296 /// generate load operations for arguments places on the stack.
297 // FIXME: struct return stuff
300 MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
301 CallingConv::ID CallConv,
303 const SmallVectorImpl<ISD::InputArg>
307 SmallVectorImpl<SDValue> &InVals) {
308 MachineFunction &MF = DAG.getMachineFunction();
309 MachineFrameInfo *MFI = MF.getFrameInfo();
310 MachineRegisterInfo &RegInfo = MF.getRegInfo();
312 // Assign locations to all of the incoming arguments.
313 SmallVector<CCValAssign, 16> ArgLocs;
314 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
315 ArgLocs, *DAG.getContext());
316 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
318 assert(!isVarArg && "Varargs not supported yet");
320 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
321 CCValAssign &VA = ArgLocs[i];
323 // Arguments passed in registers
324 EVT RegVT = VA.getLocVT();
325 switch (RegVT.getSimpleVT().SimpleTy) {
329 errs() << "LowerFormalArguments Unhandled argument type: "
330 << RegVT.getSimpleVT().SimpleTy << "\n";
336 RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
337 RegInfo.addLiveIn(VA.getLocReg(), VReg);
338 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
340 // If this is an 8-bit value, it is really passed promoted to 16
341 // bits. Insert an assert[sz]ext to capture this, then truncate to the
343 if (VA.getLocInfo() == CCValAssign::SExt)
344 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
345 DAG.getValueType(VA.getValVT()));
346 else if (VA.getLocInfo() == CCValAssign::ZExt)
347 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
348 DAG.getValueType(VA.getValVT()));
350 if (VA.getLocInfo() != CCValAssign::Full)
351 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
353 InVals.push_back(ArgValue);
357 assert(VA.isMemLoc());
358 // Load the argument to a virtual register
359 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
361 errs() << "LowerFormalArguments Unhandled argument type: "
362 << VA.getLocVT().getSimpleVT().SimpleTy
365 // Create the frame index object for this incoming parameter...
366 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true, false);
368 // Create the SelectionDAG nodes corresponding to a load
369 //from this parameter
370 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
371 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
372 PseudoSourceValue::getFixedStack(FI), 0));
380 MSP430TargetLowering::LowerReturn(SDValue Chain,
381 CallingConv::ID CallConv, bool isVarArg,
382 const SmallVectorImpl<ISD::OutputArg> &Outs,
383 DebugLoc dl, SelectionDAG &DAG) {
385 // CCValAssign - represent the assignment of the return value to a location
386 SmallVector<CCValAssign, 16> RVLocs;
388 // ISRs cannot return any value.
389 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
390 llvm_report_error("ISRs cannot return any value");
394 // CCState - Info about the registers and stack slot.
395 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
396 RVLocs, *DAG.getContext());
398 // Analize return values.
399 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
401 // If this is the first return lowered for this function, add the regs to the
402 // liveout set for the function.
403 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
404 for (unsigned i = 0; i != RVLocs.size(); ++i)
405 if (RVLocs[i].isRegLoc())
406 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
411 // Copy the result values into the output registers.
412 for (unsigned i = 0; i != RVLocs.size(); ++i) {
413 CCValAssign &VA = RVLocs[i];
414 assert(VA.isRegLoc() && "Can only return in registers!");
416 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
419 // Guarantee that all emitted copies are stuck together,
420 // avoiding something bad.
421 Flag = Chain.getValue(1);
424 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
425 MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
428 return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
431 return DAG.getNode(Opc, dl, MVT::Other, Chain);
434 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
435 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
438 MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
439 CallingConv::ID CallConv, bool isVarArg,
441 const SmallVectorImpl<ISD::OutputArg>
443 const SmallVectorImpl<ISD::InputArg> &Ins,
444 DebugLoc dl, SelectionDAG &DAG,
445 SmallVectorImpl<SDValue> &InVals) {
446 // Analyze operands of the call, assigning locations to each operand.
447 SmallVector<CCValAssign, 16> ArgLocs;
448 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
449 ArgLocs, *DAG.getContext());
451 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
453 // Get a count of how many bytes are to be pushed on the stack.
454 unsigned NumBytes = CCInfo.getNextStackOffset();
456 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
457 getPointerTy(), true));
459 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
460 SmallVector<SDValue, 12> MemOpChains;
463 // Walk the register/memloc assignments, inserting copies/loads.
464 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
465 CCValAssign &VA = ArgLocs[i];
467 SDValue Arg = Outs[i].Val;
469 // Promote the value if needed.
470 switch (VA.getLocInfo()) {
471 default: llvm_unreachable("Unknown loc info!");
472 case CCValAssign::Full: break;
473 case CCValAssign::SExt:
474 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
476 case CCValAssign::ZExt:
477 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
479 case CCValAssign::AExt:
480 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
484 // Arguments that can be passed on register must be kept at RegsToPass
487 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
489 assert(VA.isMemLoc());
491 if (StackPtr.getNode() == 0)
492 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
494 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
496 DAG.getIntPtrConstant(VA.getLocMemOffset()));
499 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
500 PseudoSourceValue::getStack(),
501 VA.getLocMemOffset()));
505 // Transform all store nodes into one single node because all store nodes are
506 // independent of each other.
507 if (!MemOpChains.empty())
508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
509 &MemOpChains[0], MemOpChains.size());
511 // Build a sequence of copy-to-reg nodes chained together with token chain and
512 // flag operands which copy the outgoing args into registers. The InFlag in
513 // necessary since all emited instructions must be stuck together.
515 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
516 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
517 RegsToPass[i].second, InFlag);
518 InFlag = Chain.getValue(1);
521 // If the callee is a GlobalAddress node (quite common, every direct call is)
522 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
523 // Likewise ExternalSymbol -> TargetExternalSymbol.
524 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
525 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
526 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
527 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
529 // Returns a chain & a flag for retval copy to use.
530 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
531 SmallVector<SDValue, 8> Ops;
532 Ops.push_back(Chain);
533 Ops.push_back(Callee);
535 // Add argument registers to the end of the list so that they are
536 // known live into the call.
537 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
538 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
539 RegsToPass[i].second.getValueType()));
541 if (InFlag.getNode())
542 Ops.push_back(InFlag);
544 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
545 InFlag = Chain.getValue(1);
547 // Create the CALLSEQ_END node.
548 Chain = DAG.getCALLSEQ_END(Chain,
549 DAG.getConstant(NumBytes, getPointerTy(), true),
550 DAG.getConstant(0, getPointerTy(), true),
552 InFlag = Chain.getValue(1);
554 // Handle result values, copying them out of physregs into vregs that we
556 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
560 /// LowerCallResult - Lower the result values of a call into the
561 /// appropriate copies out of appropriate physical registers.
564 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
565 CallingConv::ID CallConv, bool isVarArg,
566 const SmallVectorImpl<ISD::InputArg> &Ins,
567 DebugLoc dl, SelectionDAG &DAG,
568 SmallVectorImpl<SDValue> &InVals) {
570 // Assign locations to each value returned by this call.
571 SmallVector<CCValAssign, 16> RVLocs;
572 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
573 RVLocs, *DAG.getContext());
575 CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
577 // Copy all of the result registers out of their specified physreg.
578 for (unsigned i = 0; i != RVLocs.size(); ++i) {
579 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
580 RVLocs[i].getValVT(), InFlag).getValue(1);
581 InFlag = Chain.getValue(2);
582 InVals.push_back(Chain.getValue(0));
588 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
590 unsigned Opc = Op.getOpcode();
591 SDNode* N = Op.getNode();
592 EVT VT = Op.getValueType();
593 DebugLoc dl = N->getDebugLoc();
595 // Expand non-constant shifts to loops:
596 if (!isa<ConstantSDNode>(N->getOperand(1)))
599 assert(0 && "Invalid shift opcode!");
601 return DAG.getNode(MSP430ISD::SHL, dl,
602 VT, N->getOperand(0), N->getOperand(1));
604 return DAG.getNode(MSP430ISD::SRA, dl,
605 VT, N->getOperand(0), N->getOperand(1));
607 return DAG.getNode(MSP430ISD::SRL, dl,
608 VT, N->getOperand(0), N->getOperand(1));
611 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
613 // Expand the stuff into sequence of shifts.
614 // FIXME: for some shift amounts this might be done better!
615 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
616 SDValue Victim = N->getOperand(0);
618 if (Opc == ISD::SRL && ShiftAmount) {
619 // Emit a special goodness here:
620 // srl A, 1 => clrc; rrc A
621 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
625 while (ShiftAmount--)
626 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
632 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
633 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
634 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
636 // Create the TargetGlobalAddress node, folding in the constant offset.
637 SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
638 return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
639 getPointerTy(), Result);
642 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
644 DebugLoc dl = Op.getDebugLoc();
645 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
646 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
648 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
651 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
653 DebugLoc dl, SelectionDAG &DAG) {
654 // FIXME: Handle bittests someday
655 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
657 // FIXME: Handle jump negative someday
658 MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
660 default: llvm_unreachable("Invalid integer condition!");
662 TCC = MSP430CC::COND_E; // aka COND_Z
663 // Minor optimization: if RHS is a constant, swap operands, then the
664 // constant can be folded into comparison.
665 if (RHS.getOpcode() == ISD::Constant)
669 TCC = MSP430CC::COND_NE; // aka COND_NZ
670 // Minor optimization: if RHS is a constant, swap operands, then the
671 // constant can be folded into comparison.
672 if (RHS.getOpcode() == ISD::Constant)
676 std::swap(LHS, RHS); // FALLTHROUGH
678 TCC = MSP430CC::COND_HS; // aka COND_C
681 std::swap(LHS, RHS); // FALLTHROUGH
683 TCC = MSP430CC::COND_LO; // aka COND_NC
686 std::swap(LHS, RHS); // FALLTHROUGH
688 TCC = MSP430CC::COND_GE;
691 std::swap(LHS, RHS); // FALLTHROUGH
693 TCC = MSP430CC::COND_L;
697 TargetCC = DAG.getConstant(TCC, MVT::i8);
698 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
702 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
703 SDValue Chain = Op.getOperand(0);
704 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
705 SDValue LHS = Op.getOperand(2);
706 SDValue RHS = Op.getOperand(3);
707 SDValue Dest = Op.getOperand(4);
708 DebugLoc dl = Op.getDebugLoc();
711 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
713 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
714 Chain, Dest, TargetCC, Flag);
718 SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
719 SDValue LHS = Op.getOperand(0);
720 SDValue RHS = Op.getOperand(1);
721 DebugLoc dl = Op.getDebugLoc();
723 // If we are doing an AND and testing against zero, then the CMP
724 // will not be generated. The AND (or BIT) will generate the condition codes,
725 // but they are different from CMP.
727 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
728 if (RHSC->isNullValue() && LHS.hasOneUse() &&
729 (LHS.getOpcode() == ISD::AND ||
730 (LHS.getOpcode() == ISD::TRUNCATE &&
731 LHS.getOperand(0).getOpcode() == ISD::AND))) {
735 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
737 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
739 // Get the condition codes directly from the status register, if its easy.
740 // Otherwise a branch will be generated. Note that the AND and BIT
741 // instructions generate different flags than CMP, the carry bit can be used
746 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
750 case MSP430CC::COND_HS:
751 // Res = SRW & 1, no processing is required
753 case MSP430CC::COND_LO:
757 case MSP430CC::COND_NE:
759 // C = ~Z, thus Res = SRW & 1, no processing is required
761 // Res = (SRW >> 1) & 1
765 case MSP430CC::COND_E:
767 // C = ~Z, thus Res = ~(SRW & 1)
769 // Res = ~((SRW >> 1) & 1)
775 EVT VT = Op.getValueType();
776 SDValue One = DAG.getConstant(1, VT);
778 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
781 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
782 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
783 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
785 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
788 SDValue Zero = DAG.getConstant(0, VT);
789 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
790 SmallVector<SDValue, 4> Ops;
793 Ops.push_back(TargetCC);
795 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
799 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
800 SDValue LHS = Op.getOperand(0);
801 SDValue RHS = Op.getOperand(1);
802 SDValue TrueV = Op.getOperand(2);
803 SDValue FalseV = Op.getOperand(3);
804 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
805 DebugLoc dl = Op.getDebugLoc();
808 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
810 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
811 SmallVector<SDValue, 4> Ops;
812 Ops.push_back(TrueV);
813 Ops.push_back(FalseV);
814 Ops.push_back(TargetCC);
817 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
820 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
822 SDValue Val = Op.getOperand(0);
823 EVT VT = Op.getValueType();
824 DebugLoc dl = Op.getDebugLoc();
826 assert(VT == MVT::i16 && "Only support i16 for now!");
828 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
829 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
830 DAG.getValueType(Val.getValueType()));
833 SDValue MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
834 MachineFunction &MF = DAG.getMachineFunction();
835 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
836 int ReturnAddrIndex = FuncInfo->getRAIndex();
838 if (ReturnAddrIndex == 0) {
839 // Set up a frame object for the return address.
840 uint64_t SlotSize = TD->getPointerSize();
841 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
843 FuncInfo->setRAIndex(ReturnAddrIndex);
846 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
849 SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
850 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
851 DebugLoc dl = Op.getDebugLoc();
854 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
856 DAG.getConstant(TD->getPointerSize(), MVT::i16);
857 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
858 DAG.getNode(ISD::ADD, dl, getPointerTy(),
863 // Just load the return address.
864 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
865 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
869 SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
870 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
871 MFI->setFrameAddressIsTaken(true);
872 EVT VT = Op.getValueType();
873 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
874 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
875 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
878 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
882 /// getPostIndexedAddressParts - returns true by value, base pointer and
883 /// offset pointer and addressing mode by reference if this node can be
884 /// combined with a load / store to form a post-indexed load / store.
885 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
888 ISD::MemIndexedMode &AM,
889 SelectionDAG &DAG) const {
891 LoadSDNode *LD = cast<LoadSDNode>(N);
892 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
895 EVT VT = LD->getMemoryVT();
896 if (VT != MVT::i8 && VT != MVT::i16)
899 if (Op->getOpcode() != ISD::ADD)
902 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
903 uint64_t RHSC = RHS->getZExtValue();
904 if ((VT == MVT::i16 && RHSC != 2) ||
905 (VT == MVT::i8 && RHSC != 1))
908 Base = Op->getOperand(0);
909 Offset = DAG.getConstant(RHSC, VT);
918 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
920 default: return NULL;
921 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
922 case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG";
923 case MSP430ISD::RRA: return "MSP430ISD::RRA";
924 case MSP430ISD::RLA: return "MSP430ISD::RLA";
925 case MSP430ISD::RRC: return "MSP430ISD::RRC";
926 case MSP430ISD::CALL: return "MSP430ISD::CALL";
927 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
928 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
929 case MSP430ISD::CMP: return "MSP430ISD::CMP";
930 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
931 case MSP430ISD::SHL: return "MSP430ISD::SHL";
932 case MSP430ISD::SRA: return "MSP430ISD::SRA";
936 //===----------------------------------------------------------------------===//
937 // Other Lowering Code
938 //===----------------------------------------------------------------------===//
941 MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
942 MachineBasicBlock *BB,
943 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
944 MachineFunction *F = BB->getParent();
945 MachineRegisterInfo &RI = F->getRegInfo();
946 DebugLoc dl = MI->getDebugLoc();
947 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
950 const TargetRegisterClass * RC;
951 switch (MI->getOpcode()) {
953 assert(0 && "Invalid shift opcode!");
955 Opc = MSP430::SHL8r1;
956 RC = MSP430::GR8RegisterClass;
959 Opc = MSP430::SHL16r1;
960 RC = MSP430::GR16RegisterClass;
963 Opc = MSP430::SAR8r1;
964 RC = MSP430::GR8RegisterClass;
967 Opc = MSP430::SAR16r1;
968 RC = MSP430::GR16RegisterClass;
971 Opc = MSP430::SAR8r1c;
972 RC = MSP430::GR8RegisterClass;
975 Opc = MSP430::SAR16r1c;
976 RC = MSP430::GR16RegisterClass;
980 const BasicBlock *LLVM_BB = BB->getBasicBlock();
981 MachineFunction::iterator I = BB;
985 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
986 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
988 F->insert(I, LoopBB);
991 // Update machine-CFG edges by transferring all successors of the current
992 // block to the block containing instructions after shift.
993 RemBB->transferSuccessors(BB);
995 // Inform sdisel of the edge changes.
996 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
997 SE = BB->succ_end(); SI != SE; ++SI)
998 EM->insert(std::make_pair(*SI, RemBB));
1000 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1001 BB->addSuccessor(LoopBB);
1002 BB->addSuccessor(RemBB);
1003 LoopBB->addSuccessor(RemBB);
1004 LoopBB->addSuccessor(LoopBB);
1006 unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1007 unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1008 unsigned ShiftReg = RI.createVirtualRegister(RC);
1009 unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1010 unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1011 unsigned SrcReg = MI->getOperand(1).getReg();
1012 unsigned DstReg = MI->getOperand(0).getReg();
1017 BuildMI(BB, dl, TII.get(MSP430::CMP8ir))
1018 .addImm(0).addReg(ShiftAmtSrcReg);
1019 BuildMI(BB, dl, TII.get(MSP430::JCC))
1021 .addImm(MSP430CC::COND_E);
1024 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1025 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1026 // ShiftReg2 = shift ShiftReg
1027 // ShiftAmt2 = ShiftAmt - 1;
1028 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1029 .addReg(SrcReg).addMBB(BB)
1030 .addReg(ShiftReg2).addMBB(LoopBB);
1031 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1032 .addReg(ShiftAmtSrcReg).addMBB(BB)
1033 .addReg(ShiftAmtReg2).addMBB(LoopBB);
1034 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1036 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1037 .addReg(ShiftAmtReg).addImm(1);
1038 BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1040 .addImm(MSP430CC::COND_NE);
1043 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1044 BuildMI(RemBB, dl, TII.get(MSP430::PHI), DstReg)
1045 .addReg(SrcReg).addMBB(BB)
1046 .addReg(ShiftReg2).addMBB(LoopBB);
1052 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1053 MachineBasicBlock *BB,
1054 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
1055 unsigned Opc = MI->getOpcode();
1057 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1058 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1059 Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1060 return EmitShiftInstr(MI, BB, EM);
1062 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1063 DebugLoc dl = MI->getDebugLoc();
1065 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1066 "Unexpected instr type to insert");
1068 // To "insert" a SELECT instruction, we actually have to insert the diamond
1069 // control-flow pattern. The incoming instruction knows the destination vreg
1070 // to set, the condition code register to branch on, the true/false values to
1071 // select between, and a branch opcode to use.
1072 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1073 MachineFunction::iterator I = BB;
1079 // cmpTY ccX, r1, r2
1081 // fallthrough --> copy0MBB
1082 MachineBasicBlock *thisMBB = BB;
1083 MachineFunction *F = BB->getParent();
1084 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1085 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1086 BuildMI(BB, dl, TII.get(MSP430::JCC))
1088 .addImm(MI->getOperand(3).getImm());
1089 F->insert(I, copy0MBB);
1090 F->insert(I, copy1MBB);
1091 // Inform sdisel of the edge changes.
1092 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
1093 SE = BB->succ_end(); SI != SE; ++SI)
1094 EM->insert(std::make_pair(*SI, copy1MBB));
1095 // Update machine-CFG edges by transferring all successors of the current
1096 // block to the new block which will contain the Phi node for the select.
1097 copy1MBB->transferSuccessors(BB);
1098 // Next, add the true and fallthrough blocks as its successors.
1099 BB->addSuccessor(copy0MBB);
1100 BB->addSuccessor(copy1MBB);
1103 // %FalseValue = ...
1104 // # fallthrough to copy1MBB
1107 // Update machine-CFG edges
1108 BB->addSuccessor(copy1MBB);
1111 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1114 BuildMI(BB, dl, TII.get(MSP430::PHI),
1115 MI->getOperand(0).getReg())
1116 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1117 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1119 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.