1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MSP430TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "msp430-lower"
16 #include "MSP430ISelLowering.h"
18 #include "MSP430TargetMachine.h"
19 #include "MSP430Subtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/ADT/VectorExtras.h"
38 MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
39 TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
41 // Set up the register classes.
42 addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
43 addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
45 // Compute derived properties from the register classes
46 computeRegisterProperties();
48 // Provide all sorts of operation actions
50 // Division is expensive
51 setIntDivIsCheap(false);
53 // Even if we have only 1 bit shift here, we can perform
54 // shifts of the whole bitwidth 1 bit per step.
55 setShiftAmountType(MVT::i8);
57 setStackPointerRegisterToSaveRestore(MSP430::SPW);
58 setBooleanContents(ZeroOrOneBooleanContent);
59 setSchedulingPreference(SchedulingForLatency);
61 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
62 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
63 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
64 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
65 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
67 // We don't have any truncstores
68 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
70 setOperationAction(ISD::SRA, MVT::i8, Custom);
71 setOperationAction(ISD::SHL, MVT::i8, Custom);
72 setOperationAction(ISD::SRL, MVT::i8, Custom);
73 setOperationAction(ISD::SRA, MVT::i16, Custom);
74 setOperationAction(ISD::SHL, MVT::i16, Custom);
75 setOperationAction(ISD::SRL, MVT::i16, Custom);
76 setOperationAction(ISD::RET, MVT::Other, Custom);
77 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
78 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
79 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
80 setOperationAction(ISD::BRIND, MVT::Other, Expand);
81 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
82 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
83 setOperationAction(ISD::SETCC, MVT::i8, Custom);
84 setOperationAction(ISD::SETCC, MVT::i16, Custom);
85 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
86 setOperationAction(ISD::SELECT, MVT::i8, Custom);
87 setOperationAction(ISD::SELECT, MVT::i16, Custom);
88 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
90 // FIXME: Implement efficiently multiplication by a constant
91 setOperationAction(ISD::MUL, MVT::i16, Expand);
92 setOperationAction(ISD::MULHS, MVT::i16, Expand);
93 setOperationAction(ISD::MULHU, MVT::i16, Expand);
94 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
95 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
97 setOperationAction(ISD::UDIV, MVT::i16, Expand);
98 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
99 setOperationAction(ISD::SDIV, MVT::i16, Expand);
100 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
103 SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
104 switch (Op.getOpcode()) {
105 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
106 case ISD::SHL: // FALLTHROUGH
108 case ISD::SRA: return LowerShifts(Op, DAG);
109 case ISD::RET: return LowerRET(Op, DAG);
110 case ISD::CALL: return LowerCALL(Op, DAG);
111 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
112 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
113 case ISD::SETCC: return LowerSETCC(Op, DAG);
114 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
115 case ISD::SELECT: return LowerSELECT(Op, DAG);
116 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
118 assert(0 && "unimplemented operand");
123 //===----------------------------------------------------------------------===//
124 // Calling Convention Implementation
125 //===----------------------------------------------------------------------===//
127 #include "MSP430GenCallingConv.inc"
129 SDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
131 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
134 assert(0 && "Unsupported calling convention");
136 case CallingConv::Fast:
137 return LowerCCCArguments(Op, DAG);
141 SDValue MSP430TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
142 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
143 unsigned CallingConv = TheCall->getCallingConv();
144 switch (CallingConv) {
146 assert(0 && "Unsupported calling convention");
147 case CallingConv::Fast:
149 return LowerCCCCallTo(Op, DAG, CallingConv);
153 /// LowerCCCArguments - transform physical registers into virtual registers and
154 /// generate load operations for arguments places on the stack.
155 // FIXME: struct return stuff
157 SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op,
159 MachineFunction &MF = DAG.getMachineFunction();
160 MachineFrameInfo *MFI = MF.getFrameInfo();
161 MachineRegisterInfo &RegInfo = MF.getRegInfo();
162 SDValue Root = Op.getOperand(0);
163 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
164 unsigned CC = MF.getFunction()->getCallingConv();
165 DebugLoc dl = Op.getDebugLoc();
167 // Assign locations to all of the incoming arguments.
168 SmallVector<CCValAssign, 16> ArgLocs;
169 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
170 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MSP430);
172 assert(!isVarArg && "Varargs not supported yet");
174 SmallVector<SDValue, 16> ArgValues;
175 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
176 CCValAssign &VA = ArgLocs[i];
178 // Arguments passed in registers
179 MVT RegVT = VA.getLocVT();
180 switch (RegVT.getSimpleVT()) {
182 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
183 << RegVT.getSimpleVT()
188 RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
189 RegInfo.addLiveIn(VA.getLocReg(), VReg);
190 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
192 // If this is an 8-bit value, it is really passed promoted to 16
193 // bits. Insert an assert[sz]ext to capture this, then truncate to the
195 if (VA.getLocInfo() == CCValAssign::SExt)
196 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
197 DAG.getValueType(VA.getValVT()));
198 else if (VA.getLocInfo() == CCValAssign::ZExt)
199 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
200 DAG.getValueType(VA.getValVT()));
202 if (VA.getLocInfo() != CCValAssign::Full)
203 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
205 ArgValues.push_back(ArgValue);
209 assert(VA.isMemLoc());
210 // Load the argument to a virtual register
211 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
213 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
214 << VA.getLocVT().getSimpleVT()
217 // Create the frame index object for this incoming parameter...
218 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
220 // Create the SelectionDAG nodes corresponding to a load
221 //from this parameter
222 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
223 ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
224 PseudoSourceValue::getFixedStack(FI), 0));
228 ArgValues.push_back(Root);
230 // Return the new list of results.
231 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
232 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
235 SDValue MSP430TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
236 // CCValAssign - represent the assignment of the return value to a location
237 SmallVector<CCValAssign, 16> RVLocs;
238 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
239 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
240 DebugLoc dl = Op.getDebugLoc();
242 // CCState - Info about the registers and stack slot.
243 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
245 // Analize return values of ISD::RET
246 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_MSP430);
248 // If this is the first return lowered for this function, add the regs to the
249 // liveout set for the function.
250 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
251 for (unsigned i = 0; i != RVLocs.size(); ++i)
252 if (RVLocs[i].isRegLoc())
253 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
256 // The chain is always operand #0
257 SDValue Chain = Op.getOperand(0);
260 // Copy the result values into the output registers.
261 for (unsigned i = 0; i != RVLocs.size(); ++i) {
262 CCValAssign &VA = RVLocs[i];
263 assert(VA.isRegLoc() && "Can only return in registers!");
265 // ISD::RET => ret chain, (regnum1,val1), ...
266 // So i*2+1 index only the regnums
267 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
268 Op.getOperand(i*2+1), Flag);
270 // Guarantee that all emitted copies are stuck together,
271 // avoiding something bad.
272 Flag = Chain.getValue(1);
276 return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
279 return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
282 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
283 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
285 SDValue MSP430TargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
287 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
288 SDValue Chain = TheCall->getChain();
289 SDValue Callee = TheCall->getCallee();
290 bool isVarArg = TheCall->isVarArg();
291 DebugLoc dl = Op.getDebugLoc();
293 // Analyze operands of the call, assigning locations to each operand.
294 SmallVector<CCValAssign, 16> ArgLocs;
295 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
297 CCInfo.AnalyzeCallOperands(TheCall, CC_MSP430);
299 // Get a count of how many bytes are to be pushed on the stack.
300 unsigned NumBytes = CCInfo.getNextStackOffset();
302 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
303 getPointerTy(), true));
305 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
306 SmallVector<SDValue, 12> MemOpChains;
309 // Walk the register/memloc assignments, inserting copies/loads.
310 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
311 CCValAssign &VA = ArgLocs[i];
313 // Arguments start after the 5 first operands of ISD::CALL
314 SDValue Arg = TheCall->getArg(i);
316 // Promote the value if needed.
317 switch (VA.getLocInfo()) {
318 default: assert(0 && "Unknown loc info!");
319 case CCValAssign::Full: break;
320 case CCValAssign::SExt:
321 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
323 case CCValAssign::ZExt:
324 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
326 case CCValAssign::AExt:
327 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
331 // Arguments that can be passed on register must be kept at RegsToPass
334 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
336 assert(VA.isMemLoc());
338 if (StackPtr.getNode() == 0)
339 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
341 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
343 DAG.getIntPtrConstant(VA.getLocMemOffset()));
346 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
347 PseudoSourceValue::getStack(),
348 VA.getLocMemOffset()));
352 // Transform all store nodes into one single node because all store nodes are
353 // independent of each other.
354 if (!MemOpChains.empty())
355 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
356 &MemOpChains[0], MemOpChains.size());
358 // Build a sequence of copy-to-reg nodes chained together with token chain and
359 // flag operands which copy the outgoing args into registers. The InFlag in
360 // necessary since all emited instructions must be stuck together.
362 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
363 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
364 RegsToPass[i].second, InFlag);
365 InFlag = Chain.getValue(1);
368 // If the callee is a GlobalAddress node (quite common, every direct call is)
369 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
370 // Likewise ExternalSymbol -> TargetExternalSymbol.
371 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
372 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
373 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
374 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
376 // Returns a chain & a flag for retval copy to use.
377 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
378 SmallVector<SDValue, 8> Ops;
379 Ops.push_back(Chain);
380 Ops.push_back(Callee);
382 // Add argument registers to the end of the list so that they are
383 // known live into the call.
384 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
385 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
386 RegsToPass[i].second.getValueType()));
388 if (InFlag.getNode())
389 Ops.push_back(InFlag);
391 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
392 InFlag = Chain.getValue(1);
394 // Create the CALLSEQ_END node.
395 Chain = DAG.getCALLSEQ_END(Chain,
396 DAG.getConstant(NumBytes, getPointerTy(), true),
397 DAG.getConstant(0, getPointerTy(), true),
399 InFlag = Chain.getValue(1);
401 // Handle result values, copying them out of physregs into vregs that we
403 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
407 /// LowerCallResult - Lower the result values of an ISD::CALL into the
408 /// appropriate copies out of appropriate physical registers. This assumes that
409 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
410 /// being lowered. Returns a SDNode with the same number of values as the
413 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
415 unsigned CallingConv,
417 bool isVarArg = TheCall->isVarArg();
418 DebugLoc dl = TheCall->getDebugLoc();
420 // Assign locations to each value returned by this call.
421 SmallVector<CCValAssign, 16> RVLocs;
422 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
424 CCInfo.AnalyzeCallResult(TheCall, RetCC_MSP430);
425 SmallVector<SDValue, 8> ResultVals;
427 // Copy all of the result registers out of their specified physreg.
428 for (unsigned i = 0; i != RVLocs.size(); ++i) {
429 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
430 RVLocs[i].getValVT(), InFlag).getValue(1);
431 InFlag = Chain.getValue(2);
432 ResultVals.push_back(Chain.getValue(0));
435 ResultVals.push_back(Chain);
437 // Merge everything together with a MERGE_VALUES node.
438 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
439 &ResultVals[0], ResultVals.size()).getNode();
442 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
444 unsigned Opc = Op.getOpcode();
445 SDNode* N = Op.getNode();
446 MVT VT = Op.getValueType();
447 DebugLoc dl = N->getDebugLoc();
449 // We currently only lower shifts of constant argument.
450 if (!isa<ConstantSDNode>(N->getOperand(1)))
453 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
455 // Expand the stuff into sequence of shifts.
456 // FIXME: for some shift amounts this might be done better!
457 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
458 SDValue Victim = N->getOperand(0);
460 if (Opc == ISD::SRL && ShiftAmount) {
461 // Emit a special goodness here:
462 // srl A, 1 => clrc; rrc A
463 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
467 while (ShiftAmount--)
468 Victim = DAG.getNode((Opc == ISD::SRA ? MSP430ISD::RRA : MSP430ISD::RLA),
474 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
475 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
476 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
478 // Create the TargetGlobalAddress node, folding in the constant offset.
479 SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
480 return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
481 getPointerTy(), Result);
484 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
486 DebugLoc dl = Op.getDebugLoc();
487 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
488 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
490 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
494 MVT MSP430TargetLowering::getSetCCResultType(MVT VT) const {
498 SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
499 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
500 SDValue LHS = Op.getOperand(0);
501 SDValue RHS = Op.getOperand(1);
502 DebugLoc dl = Op.getDebugLoc();
503 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
505 // FIXME: Handle bittests someday
506 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
508 // FIXME: Handle jump negative someday
509 unsigned TargetCC = 0;
511 default: assert(0 && "Invalid integer condition!");
513 TargetCC = MSP430::COND_E; // aka COND_Z
516 TargetCC = MSP430::COND_NE; // aka COND_NZ
519 std::swap(LHS, RHS); // FALLTHROUGH
521 TargetCC = MSP430::COND_HS; // aka COND_C
524 std::swap(LHS, RHS); // FALLTHROUGH
526 TargetCC = MSP430::COND_LO; // aka COND_NC
529 std::swap(LHS, RHS); // FALLTHROUGH
531 TargetCC = MSP430::COND_GE;
534 std::swap(LHS, RHS); // FALLTHROUGH
536 TargetCC = MSP430::COND_L;
540 SDValue Cond = DAG.getNode(MSP430ISD::CMP, dl, MVT::i16, LHS, RHS);
541 return DAG.getNode(MSP430ISD::SETCC, dl, MVT::i8,
542 DAG.getConstant(TargetCC, MVT::i8), Cond);
545 SDValue MSP430TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
546 SDValue Chain = Op.getOperand(0);
547 SDValue Cond = Op.getOperand(1);
548 SDValue Dest = Op.getOperand(2);
549 DebugLoc dl = Op.getDebugLoc();
552 // Lower condition if not lowered yet
553 if (Cond.getOpcode() == ISD::SETCC)
554 Cond = LowerSETCC(Cond, DAG);
556 // If condition flag is set by a MSP430ISD::CMP, then use it as the condition
557 // setting operand in place of the MSP430ISD::SETCC.
558 if (Cond.getOpcode() == MSP430ISD::SETCC) {
559 CC = Cond.getOperand(0);
560 Cond = Cond.getOperand(1);
562 assert(0 && "Unimplemented condition!");
564 return DAG.getNode(MSP430ISD::BRCOND, dl, Op.getValueType(),
565 Chain, Dest, CC, Cond);
568 SDValue MSP430TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
569 SDValue Cond = Op.getOperand(0);
570 SDValue TrueV = Op.getOperand(1);
571 SDValue FalseV = Op.getOperand(2);
572 DebugLoc dl = Op.getDebugLoc();
575 // Lower condition if not lowered yet
576 if (Cond.getOpcode() == ISD::SETCC)
577 Cond = LowerSETCC(Cond, DAG);
579 // If condition flag is set by a MSP430ISD::CMP, then use it as the condition
580 // setting operand in place of the MSP430ISD::SETCC.
581 if (Cond.getOpcode() == MSP430ISD::SETCC) {
582 CC = Cond.getOperand(0);
583 Cond = Cond.getOperand(1);
584 TrueV = Cond.getOperand(0);
585 FalseV = Cond.getOperand(1);
587 CC = DAG.getConstant(MSP430::COND_NE, MVT::i16);
588 Cond = DAG.getNode(MSP430ISD::CMP, dl, MVT::i16,
589 Cond, DAG.getConstant(0, MVT::i16));
592 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
593 SmallVector<SDValue, 4> Ops;
594 Ops.push_back(TrueV);
595 Ops.push_back(FalseV);
599 return DAG.getNode(MSP430ISD::SELECT, dl, VTs, &Ops[0], Ops.size());
602 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
604 SDValue Val = Op.getOperand(0);
605 MVT VT = Op.getValueType();
606 DebugLoc dl = Op.getDebugLoc();
608 assert(VT == MVT::i16 && "Only support i16 for now!");
610 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
611 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
612 DAG.getValueType(Val.getValueType()));
615 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
617 default: return NULL;
618 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
619 case MSP430ISD::RRA: return "MSP430ISD::RRA";
620 case MSP430ISD::RLA: return "MSP430ISD::RLA";
621 case MSP430ISD::RRC: return "MSP430ISD::RRC";
622 case MSP430ISD::CALL: return "MSP430ISD::CALL";
623 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
624 case MSP430ISD::BRCOND: return "MSP430ISD::BRCOND";
625 case MSP430ISD::CMP: return "MSP430ISD::CMP";
626 case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
627 case MSP430ISD::SELECT: return "MSP430ISD::SELECT";
631 //===----------------------------------------------------------------------===//
632 // Other Lowering Code
633 //===----------------------------------------------------------------------===//
636 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
637 MachineBasicBlock *BB) const {
638 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
639 DebugLoc dl = MI->getDebugLoc();
640 assert((MI->getOpcode() == MSP430::Select16) &&
641 "Unexpected instr type to insert");
643 // To "insert" a SELECT instruction, we actually have to insert the diamond
644 // control-flow pattern. The incoming instruction knows the destination vreg
645 // to set, the condition code register to branch on, the true/false values to
646 // select between, and a branch opcode to use.
647 const BasicBlock *LLVM_BB = BB->getBasicBlock();
648 MachineFunction::iterator I = BB;
656 // fallthrough --> copy0MBB
657 MachineBasicBlock *thisMBB = BB;
658 MachineFunction *F = BB->getParent();
659 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
660 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
661 BuildMI(BB, dl, TII.get(MSP430::JCC))
663 .addImm(MI->getOperand(3).getImm());
664 F->insert(I, copy0MBB);
665 F->insert(I, copy1MBB);
666 // Update machine-CFG edges by transferring all successors of the current
667 // block to the new block which will contain the Phi node for the select.
668 copy1MBB->transferSuccessors(BB);
669 // Next, add the true and fallthrough blocks as its successors.
670 BB->addSuccessor(copy0MBB);
671 BB->addSuccessor(copy1MBB);
675 // # fallthrough to copy1MBB
678 // Update machine-CFG edges
679 BB->addSuccessor(copy1MBB);
682 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
685 BuildMI(BB, dl, TII.get(MSP430::PHI),
686 MI->getOperand(0).getReg())
687 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
688 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
690 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.