lib/Target/MSP430/MSP430ISelLowering.h

   1 //==-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ------*- C++ -*-==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that MSP430 uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_TARGET_MSP430_ISELLOWERING_H
  16 #define LLVM_TARGET_MSP430_ISELLOWERING_H
  17
  18 #include "MSP430.h"
  19 #include "llvm/CodeGen/SelectionDAG.h"
  20 #include "llvm/Target/TargetLowering.h"
  21
  22 namespace llvm {
  23   namespace MSP430ISD {
  24     enum {
  25       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  26
  27       /// Return with a flag operand. Operand 0 is the chain operand.
  28       RET_FLAG,
  29
  30       /// Same as RET_FLAG, but used for returning from ISRs.
  31       RETI_FLAG,
  32
  33       /// Y = R{R,L}A X, rotate right (left) arithmetically
  34       RRA, RLA,
  35
  36       /// Y = RRC X, rotate right via carry
  37       RRC,
  38
  39       /// CALL - These operations represent an abstract call
  40       /// instruction, which includes a bunch of information.
  41       CALL,
  42
  43       /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
  44       /// and TargetGlobalAddress.
  45       Wrapper,
  46
  47       /// CMP - Compare instruction.
  48       CMP,
  49
  50       /// SetCC. Operand 0 is condition code, and operand 1 is the flag
  51       /// operand produced by a CMP instruction.
  52       SETCC,
  53
  54       /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
  55       /// is the block to branch if condition is true, operand 2 is the
  56       /// condition code, and operand 3 is the flag operand produced by a CMP
  57       /// instruction.
  58       BR_CC,
  59
  60       /// SELECT_CC. Operand 0 and operand 1 are selection variable, operand 3
  61       /// is condition code and operand 4 is flag operand.
  62       SELECT_CC
  63     };
  64   }
  65
  66   class MSP430Subtarget;
  67   class MSP430TargetMachine;
  68
  69   class MSP430TargetLowering : public TargetLowering {
  70   public:
  71     explicit MSP430TargetLowering(MSP430TargetMachine &TM);
  72
  73     /// LowerOperation - Provide custom lowering hooks for some operations.
  74     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
  75
  76     /// getTargetNodeName - This method returns the name of a target specific
  77     /// DAG node.
  78     virtual const char *getTargetNodeName(unsigned Opcode) const;
  79
  80     /// getFunctionAlignment - Return the Log2 alignment of this function.
  81     virtual unsigned getFunctionAlignment(const Function *F) const;
  82
  83     SDValue LowerShifts(SDValue Op, SelectionDAG &DAG);
  84     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
  85     SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
  86     SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
  87     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
  88     SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG);
  89
  90     TargetLowering::ConstraintType
  91     getConstraintType(const std::string &Constraint) const;
  92     std::pair<unsigned, const TargetRegisterClass*>
  93     getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
  94
  95     MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
  96                                                    MachineBasicBlock *BB,
  97                     DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
  98
  99   private:
 100     SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
 101                            CallingConv::ID CallConv, bool isVarArg,
 102                            bool isTailCall,
 103                            const SmallVectorImpl<ISD::OutputArg> &Outs,
 104                            const SmallVectorImpl<ISD::InputArg> &Ins,
 105                            DebugLoc dl, SelectionDAG &DAG,
 106                            SmallVectorImpl<SDValue> &InVals);
 107
 108     SDValue LowerCCCArguments(SDValue Chain,
 109                               CallingConv::ID CallConv,
 110                               bool isVarArg,
 111                               const SmallVectorImpl<ISD::InputArg> &Ins,
 112                               DebugLoc dl,
 113                               SelectionDAG &DAG,
 114                               SmallVectorImpl<SDValue> &InVals);
 115
 116     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 117                             CallingConv::ID CallConv, bool isVarArg,
 118                             const SmallVectorImpl<ISD::InputArg> &Ins,
 119                             DebugLoc dl, SelectionDAG &DAG,
 120                             SmallVectorImpl<SDValue> &InVals);
 121
 122     virtual SDValue
 123       LowerFormalArguments(SDValue Chain,
 124                            CallingConv::ID CallConv, bool isVarArg,
 125                            const SmallVectorImpl<ISD::InputArg> &Ins,
 126                            DebugLoc dl, SelectionDAG &DAG,
 127                            SmallVectorImpl<SDValue> &InVals);
 128     virtual SDValue
 129       LowerCall(SDValue Chain, SDValue Callee,
 130                 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
 131                 const SmallVectorImpl<ISD::OutputArg> &Outs,
 132                 const SmallVectorImpl<ISD::InputArg> &Ins,
 133                 DebugLoc dl, SelectionDAG &DAG,
 134                 SmallVectorImpl<SDValue> &InVals);
 135
 136     virtual SDValue
 137       LowerReturn(SDValue Chain,
 138                   CallingConv::ID CallConv, bool isVarArg,
 139                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 140                   DebugLoc dl, SelectionDAG &DAG);
 141
 142     virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
 143                                             SDValue &Base,
 144                                             SDValue &Offset,
 145                                             ISD::MemIndexedMode &AM,
 146                                             SelectionDAG &DAG) const;
 147
 148     const MSP430Subtarget &Subtarget;
 149     const MSP430TargetMachine &TM;
 150   };
 151 } // namespace llvm
 152
 153 #endif // LLVM_TARGET_MSP430_ISELLOWERING_H