1 //===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that MSP430 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_MSP430_ISELLOWERING_H
16 #define LLVM_TARGET_MSP430_ISELLOWERING_H
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
27 /// Return with a flag operand. Operand 0 is the chain operand.
30 /// Same as RET_FLAG, but used for returning from ISRs.
33 /// Y = R{R,L}A X, rotate right (left) arithmetically
36 /// Y = RRC X, rotate right via carry
39 /// CALL - These operations represent an abstract call
40 /// instruction, which includes a bunch of information.
43 /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
44 /// and TargetGlobalAddress.
47 /// CMP - Compare instruction.
50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
51 /// operand produced by a CMP instruction.
54 /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
55 /// is the block to branch if condition is true, operand 2 is the
56 /// condition code, and operand 3 is the flag operand produced by a CMP
60 /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
61 /// is condition code and operand 4 is flag operand.
64 /// SHL, SRA, SRL - Non-constant shifts.
69 class MSP430Subtarget;
70 class MSP430TargetMachine;
72 class MSP430TargetLowering : public TargetLowering {
74 explicit MSP430TargetLowering(MSP430TargetMachine &TM);
76 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
78 /// LowerOperation - Provide custom lowering hooks for some operations.
79 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
81 /// getTargetNodeName - This method returns the name of a target specific
83 virtual const char *getTargetNodeName(unsigned Opcode) const;
85 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
94 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
95 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
96 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
97 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
99 TargetLowering::ConstraintType
100 getConstraintType(const std::string &Constraint) const;
101 std::pair<unsigned, const TargetRegisterClass*>
102 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
104 /// isTruncateFree - Return true if it's free to truncate a value of type
105 /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
106 /// register R15W to i8 by referencing its sub-register R15B.
107 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
108 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
110 /// isZExtFree - Return true if any actual instruction that defines a value
111 /// of type Ty1 implicit zero-extends the value to Ty2 in the result
112 /// register. This does not necessarily include registers defined in unknown
113 /// ways, such as incoming arguments, or copies from unknown virtual
114 /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
115 /// necessarily apply to truncate instructions. e.g. on msp430, all
116 /// instructions that define 8-bit values implicit zero-extend the result
118 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
119 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
120 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
122 MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
123 MachineBasicBlock *BB) const;
124 MachineBasicBlock* EmitShiftInstr(MachineInstr *MI,
125 MachineBasicBlock *BB) const;
128 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
129 CallingConv::ID CallConv, bool isVarArg,
131 const SmallVectorImpl<ISD::OutputArg> &Outs,
132 const SmallVectorImpl<SDValue> &OutVals,
133 const SmallVectorImpl<ISD::InputArg> &Ins,
134 SDLoc dl, SelectionDAG &DAG,
135 SmallVectorImpl<SDValue> &InVals) const;
137 SDValue LowerCCCArguments(SDValue Chain,
138 CallingConv::ID CallConv,
140 const SmallVectorImpl<ISD::InputArg> &Ins,
143 SmallVectorImpl<SDValue> &InVals) const;
145 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
146 CallingConv::ID CallConv, bool isVarArg,
147 const SmallVectorImpl<ISD::InputArg> &Ins,
148 SDLoc dl, SelectionDAG &DAG,
149 SmallVectorImpl<SDValue> &InVals) const;
152 LowerFormalArguments(SDValue Chain,
153 CallingConv::ID CallConv, bool isVarArg,
154 const SmallVectorImpl<ISD::InputArg> &Ins,
155 SDLoc dl, SelectionDAG &DAG,
156 SmallVectorImpl<SDValue> &InVals) const;
158 LowerCall(TargetLowering::CallLoweringInfo &CLI,
159 SmallVectorImpl<SDValue> &InVals) const;
162 LowerReturn(SDValue Chain,
163 CallingConv::ID CallConv, bool isVarArg,
164 const SmallVectorImpl<ISD::OutputArg> &Outs,
165 const SmallVectorImpl<SDValue> &OutVals,
166 SDLoc dl, SelectionDAG &DAG) const;
168 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
171 ISD::MemIndexedMode &AM,
172 SelectionDAG &DAG) const;
174 const MSP430Subtarget &Subtarget;
175 const DataLayout *TD;
179 #endif // LLVM_TARGET_MSP430_ISELLOWERING_H