1 //===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430InstrInfo.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430TargetMachine.h"
18 #include "MSP430GenInstrInfo.inc"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/Support/ErrorHandling.h"
28 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
29 : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)),
30 RI(tm, *this), TM(tm) {}
32 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
33 MachineBasicBlock::iterator MI,
34 unsigned SrcReg, bool isKill, int FrameIdx,
35 const TargetRegisterClass *RC) const {
37 if (MI != MBB.end()) DL = MI->getDebugLoc();
38 MachineFunction &MF = *MBB.getParent();
39 MachineFrameInfo &MFI = *MF.getFrameInfo();
41 MachineMemOperand *MMO =
42 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
43 MachineMemOperand::MOStore, 0,
44 MFI.getObjectSize(FrameIdx),
45 MFI.getObjectAlignment(FrameIdx));
47 if (RC == &MSP430::GR16RegClass)
48 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
49 .addFrameIndex(FrameIdx).addImm(0)
50 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
51 else if (RC == &MSP430::GR8RegClass)
52 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
53 .addFrameIndex(FrameIdx).addImm(0)
54 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
56 llvm_unreachable("Cannot store this register to stack slot!");
59 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MI,
61 unsigned DestReg, int FrameIdx,
62 const TargetRegisterClass *RC) const{
64 if (MI != MBB.end()) DL = MI->getDebugLoc();
65 MachineFunction &MF = *MBB.getParent();
66 MachineFrameInfo &MFI = *MF.getFrameInfo();
68 MachineMemOperand *MMO =
69 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
70 MachineMemOperand::MOLoad, 0,
71 MFI.getObjectSize(FrameIdx),
72 MFI.getObjectAlignment(FrameIdx));
74 if (RC == &MSP430::GR16RegClass)
75 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
76 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
77 else if (RC == &MSP430::GR8RegClass)
78 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
79 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
81 llvm_unreachable("Cannot store this register to stack slot!");
84 bool MSP430InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
85 MachineBasicBlock::iterator I,
86 unsigned DestReg, unsigned SrcReg,
87 const TargetRegisterClass *DestRC,
88 const TargetRegisterClass *SrcRC) const {
90 if (I != MBB.end()) DL = I->getDebugLoc();
92 if (DestRC == SrcRC) {
94 if (DestRC == &MSP430::GR16RegClass) {
95 Opc = MSP430::MOV16rr;
96 } else if (DestRC == &MSP430::GR8RegClass) {
102 BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg);
110 MSP430InstrInfo::isMoveInstr(const MachineInstr& MI,
111 unsigned &SrcReg, unsigned &DstReg,
112 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
113 SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
115 switch (MI.getOpcode()) {
119 case MSP430::MOV16rr:
120 assert(MI.getNumOperands() >= 2 &&
121 MI.getOperand(0).isReg() &&
122 MI.getOperand(1).isReg() &&
123 "invalid register-register move instruction");
124 SrcReg = MI.getOperand(1).getReg();
125 DstReg = MI.getOperand(0).getReg();
131 MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
132 MachineBasicBlock::iterator MI,
133 const std::vector<CalleeSavedInfo> &CSI) const {
138 if (MI != MBB.end()) DL = MI->getDebugLoc();
140 MachineFunction &MF = *MBB.getParent();
141 MSP430MachineFunctionInfo *MFI = MF.getInfo<MSP430MachineFunctionInfo>();
142 MFI->setCalleeSavedFrameSize(CSI.size() * 2);
144 for (unsigned i = CSI.size(); i != 0; --i) {
145 unsigned Reg = CSI[i-1].getReg();
146 // Add the callee-saved register as live-in. It's killed at the spill.
148 BuildMI(MBB, MI, DL, get(MSP430::PUSH16r))
149 .addReg(Reg, RegState::Kill);
155 MSP430InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
156 MachineBasicBlock::iterator MI,
157 const std::vector<CalleeSavedInfo> &CSI) const {
162 if (MI != MBB.end()) DL = MI->getDebugLoc();
164 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
165 BuildMI(MBB, MI, DL, get(MSP430::POP16r), CSI[i].getReg());
170 unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
171 MachineBasicBlock::iterator I = MBB.end();
174 while (I != MBB.begin()) {
176 if (I->isDebugValue())
178 if (I->getOpcode() != MSP430::JMP &&
179 I->getOpcode() != MSP430::JCC)
181 // Remove the branch.
182 I->eraseFromParent();
190 bool MSP430InstrInfo::
191 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
192 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
194 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
198 assert(0 && "Invalid branch condition!");
200 case MSP430CC::COND_E:
201 CC = MSP430CC::COND_NE;
203 case MSP430CC::COND_NE:
204 CC = MSP430CC::COND_E;
206 case MSP430CC::COND_L:
207 CC = MSP430CC::COND_GE;
209 case MSP430CC::COND_GE:
210 CC = MSP430CC::COND_L;
212 case MSP430CC::COND_HS:
213 CC = MSP430CC::COND_LO;
215 case MSP430CC::COND_LO:
216 CC = MSP430CC::COND_HS;
224 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
225 const TargetInstrDesc &TID = MI->getDesc();
226 if (!TID.isTerminator()) return false;
228 // Conditional branch is a special case.
229 if (TID.isBranch() && !TID.isBarrier())
231 if (!TID.isPredicable())
233 return !isPredicated(MI);
236 bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
237 MachineBasicBlock *&TBB,
238 MachineBasicBlock *&FBB,
239 SmallVectorImpl<MachineOperand> &Cond,
240 bool AllowModify) const {
241 // Start from the bottom of the block and work up, examining the
242 // terminator instructions.
243 MachineBasicBlock::iterator I = MBB.end();
244 while (I != MBB.begin()) {
246 if (I->isDebugValue())
249 // Working from the bottom, when we see a non-terminator
250 // instruction, we're done.
251 if (!isUnpredicatedTerminator(I))
254 // A terminator that isn't a branch can't easily be handled
256 if (!I->getDesc().isBranch())
259 // Handle unconditional branches.
260 if (I->getOpcode() == MSP430::JMP) {
262 TBB = I->getOperand(0).getMBB();
266 // If the block has any instructions after a JMP, delete them.
267 while (llvm::next(I) != MBB.end())
268 llvm::next(I)->eraseFromParent();
272 // Delete the JMP if it's equivalent to a fall-through.
273 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
275 I->eraseFromParent();
280 // TBB is used to indicate the unconditinal destination.
281 TBB = I->getOperand(0).getMBB();
285 // Handle conditional branches.
286 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
287 MSP430CC::CondCodes BranchCode =
288 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
289 if (BranchCode == MSP430CC::COND_INVALID)
290 return true; // Can't handle weird stuff.
292 // Working from the bottom, handle the first conditional branch.
295 TBB = I->getOperand(0).getMBB();
296 Cond.push_back(MachineOperand::CreateImm(BranchCode));
300 // Handle subsequent conditional branches. Only handle the case where all
301 // conditional branches branch to the same destination.
302 assert(Cond.size() == 1);
305 // Only handle the case where all conditional branches branch to
306 // the same destination.
307 if (TBB != I->getOperand(0).getMBB())
310 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
311 // If the conditions are the same, we can leave them alone.
312 if (OldBranchCode == BranchCode)
322 MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
323 MachineBasicBlock *FBB,
324 const SmallVectorImpl<MachineOperand> &Cond) const {
325 // FIXME this should probably have a DebugLoc operand
328 // Shouldn't be a fall through.
329 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
330 assert((Cond.size() == 1 || Cond.size() == 0) &&
331 "MSP430 branch conditions have one component!");
334 // Unconditional branch?
335 assert(!FBB && "Unconditional branch with multiple successors!");
336 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
340 // Conditional branch.
342 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
346 // Two-way Conditional branch. Insert the second branch.
347 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
353 /// GetInstSize - Return the number of bytes of code the specified
354 /// instruction may be. This returns the maximum number of bytes.
356 unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
357 const TargetInstrDesc &Desc = MI->getDesc();
359 switch (Desc.TSFlags & MSP430II::SizeMask) {
361 switch (Desc.getOpcode()) {
363 assert(0 && "Unknown instruction size!");
364 case TargetOpcode::DBG_LABEL:
365 case TargetOpcode::EH_LABEL:
366 case TargetOpcode::IMPLICIT_DEF:
367 case TargetOpcode::KILL:
369 case TargetOpcode::INLINEASM: {
370 const MachineFunction *MF = MI->getParent()->getParent();
371 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
372 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
373 *MF->getTarget().getMCAsmInfo());
376 case MSP430II::SizeSpecial:
377 switch (MI->getOpcode()) {
379 assert(0 && "Unknown instruction size!");
380 case MSP430::SAR8r1c:
381 case MSP430::SAR16r1c:
384 case MSP430II::Size2Bytes:
386 case MSP430II::Size4Bytes:
388 case MSP430II::Size6Bytes: