1 //===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430InstrInfo.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430TargetMachine.h"
18 #include "MSP430GenInstrInfo.inc"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/Support/ErrorHandling.h"
28 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
29 : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)),
30 RI(tm, *this), TM(tm) {}
32 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
33 MachineBasicBlock::iterator MI,
34 unsigned SrcReg, bool isKill, int FrameIdx,
35 const TargetRegisterClass *RC,
36 const TargetRegisterInfo *TRI) const {
38 if (MI != MBB.end()) DL = MI->getDebugLoc();
39 MachineFunction &MF = *MBB.getParent();
40 MachineFrameInfo &MFI = *MF.getFrameInfo();
42 MachineMemOperand *MMO =
43 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
44 MachineMemOperand::MOStore, 0,
45 MFI.getObjectSize(FrameIdx),
46 MFI.getObjectAlignment(FrameIdx));
48 if (RC == &MSP430::GR16RegClass)
49 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
50 .addFrameIndex(FrameIdx).addImm(0)
51 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
52 else if (RC == &MSP430::GR8RegClass)
53 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
54 .addFrameIndex(FrameIdx).addImm(0)
55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
57 llvm_unreachable("Cannot store this register to stack slot!");
60 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MI,
62 unsigned DestReg, int FrameIdx,
63 const TargetRegisterClass *RC,
64 const TargetRegisterInfo *TRI) const{
66 if (MI != MBB.end()) DL = MI->getDebugLoc();
67 MachineFunction &MF = *MBB.getParent();
68 MachineFrameInfo &MFI = *MF.getFrameInfo();
70 MachineMemOperand *MMO =
71 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
72 MachineMemOperand::MOLoad, 0,
73 MFI.getObjectSize(FrameIdx),
74 MFI.getObjectAlignment(FrameIdx));
76 if (RC == &MSP430::GR16RegClass)
77 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
78 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
79 else if (RC == &MSP430::GR8RegClass)
80 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
81 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
83 llvm_unreachable("Cannot store this register to stack slot!");
86 bool MSP430InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator I,
88 unsigned DestReg, unsigned SrcReg,
89 const TargetRegisterClass *DestRC,
90 const TargetRegisterClass *SrcRC,
92 if (DestRC == SrcRC) {
94 if (DestRC == &MSP430::GR16RegClass) {
95 Opc = MSP430::MOV16rr;
96 } else if (DestRC == &MSP430::GR8RegClass) {
102 BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg);
110 MSP430InstrInfo::isMoveInstr(const MachineInstr& MI,
111 unsigned &SrcReg, unsigned &DstReg,
112 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
113 SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
115 switch (MI.getOpcode()) {
119 case MSP430::MOV16rr:
120 assert(MI.getNumOperands() >= 2 &&
121 MI.getOperand(0).isReg() &&
122 MI.getOperand(1).isReg() &&
123 "invalid register-register move instruction");
124 SrcReg = MI.getOperand(1).getReg();
125 DstReg = MI.getOperand(0).getReg();
131 MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
132 MachineBasicBlock::iterator MI,
133 const std::vector<CalleeSavedInfo> &CSI,
134 const TargetRegisterInfo *TRI) const {
139 if (MI != MBB.end()) DL = MI->getDebugLoc();
141 MachineFunction &MF = *MBB.getParent();
142 MSP430MachineFunctionInfo *MFI = MF.getInfo<MSP430MachineFunctionInfo>();
143 MFI->setCalleeSavedFrameSize(CSI.size() * 2);
145 for (unsigned i = CSI.size(); i != 0; --i) {
146 unsigned Reg = CSI[i-1].getReg();
147 // Add the callee-saved register as live-in. It's killed at the spill.
149 BuildMI(MBB, MI, DL, get(MSP430::PUSH16r))
150 .addReg(Reg, RegState::Kill);
156 MSP430InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
157 MachineBasicBlock::iterator MI,
158 const std::vector<CalleeSavedInfo> &CSI,
159 const TargetRegisterInfo *TRI) const {
164 if (MI != MBB.end()) DL = MI->getDebugLoc();
166 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
167 BuildMI(MBB, MI, DL, get(MSP430::POP16r), CSI[i].getReg());
172 unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
173 MachineBasicBlock::iterator I = MBB.end();
176 while (I != MBB.begin()) {
178 if (I->isDebugValue())
180 if (I->getOpcode() != MSP430::JMP &&
181 I->getOpcode() != MSP430::JCC &&
182 I->getOpcode() != MSP430::Br &&
183 I->getOpcode() != MSP430::Bm)
185 // Remove the branch.
186 I->eraseFromParent();
194 bool MSP430InstrInfo::
195 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
196 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
198 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
202 assert(0 && "Invalid branch condition!");
204 case MSP430CC::COND_E:
205 CC = MSP430CC::COND_NE;
207 case MSP430CC::COND_NE:
208 CC = MSP430CC::COND_E;
210 case MSP430CC::COND_L:
211 CC = MSP430CC::COND_GE;
213 case MSP430CC::COND_GE:
214 CC = MSP430CC::COND_L;
216 case MSP430CC::COND_HS:
217 CC = MSP430CC::COND_LO;
219 case MSP430CC::COND_LO:
220 CC = MSP430CC::COND_HS;
228 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
229 const TargetInstrDesc &TID = MI->getDesc();
230 if (!TID.isTerminator()) return false;
232 // Conditional branch is a special case.
233 if (TID.isBranch() && !TID.isBarrier())
235 if (!TID.isPredicable())
237 return !isPredicated(MI);
240 bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
241 MachineBasicBlock *&TBB,
242 MachineBasicBlock *&FBB,
243 SmallVectorImpl<MachineOperand> &Cond,
244 bool AllowModify) const {
245 // Start from the bottom of the block and work up, examining the
246 // terminator instructions.
247 MachineBasicBlock::iterator I = MBB.end();
248 while (I != MBB.begin()) {
250 if (I->isDebugValue())
253 // Working from the bottom, when we see a non-terminator
254 // instruction, we're done.
255 if (!isUnpredicatedTerminator(I))
258 // A terminator that isn't a branch can't easily be handled
260 if (!I->getDesc().isBranch())
263 // Cannot handle indirect branches.
264 if (I->getOpcode() == MSP430::Br ||
265 I->getOpcode() == MSP430::Bm)
268 // Handle unconditional branches.
269 if (I->getOpcode() == MSP430::JMP) {
271 TBB = I->getOperand(0).getMBB();
275 // If the block has any instructions after a JMP, delete them.
276 while (llvm::next(I) != MBB.end())
277 llvm::next(I)->eraseFromParent();
281 // Delete the JMP if it's equivalent to a fall-through.
282 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
284 I->eraseFromParent();
289 // TBB is used to indicate the unconditinal destination.
290 TBB = I->getOperand(0).getMBB();
294 // Handle conditional branches.
295 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
296 MSP430CC::CondCodes BranchCode =
297 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
298 if (BranchCode == MSP430CC::COND_INVALID)
299 return true; // Can't handle weird stuff.
301 // Working from the bottom, handle the first conditional branch.
304 TBB = I->getOperand(0).getMBB();
305 Cond.push_back(MachineOperand::CreateImm(BranchCode));
309 // Handle subsequent conditional branches. Only handle the case where all
310 // conditional branches branch to the same destination.
311 assert(Cond.size() == 1);
314 // Only handle the case where all conditional branches branch to
315 // the same destination.
316 if (TBB != I->getOperand(0).getMBB())
319 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
320 // If the conditions are the same, we can leave them alone.
321 if (OldBranchCode == BranchCode)
331 MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
332 MachineBasicBlock *FBB,
333 const SmallVectorImpl<MachineOperand> &Cond,
335 // Shouldn't be a fall through.
336 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
337 assert((Cond.size() == 1 || Cond.size() == 0) &&
338 "MSP430 branch conditions have one component!");
341 // Unconditional branch?
342 assert(!FBB && "Unconditional branch with multiple successors!");
343 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
347 // Conditional branch.
349 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
353 // Two-way Conditional branch. Insert the second branch.
354 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
360 /// GetInstSize - Return the number of bytes of code the specified
361 /// instruction may be. This returns the maximum number of bytes.
363 unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
364 const TargetInstrDesc &Desc = MI->getDesc();
366 switch (Desc.TSFlags & MSP430II::SizeMask) {
368 switch (Desc.getOpcode()) {
370 assert(0 && "Unknown instruction size!");
371 case TargetOpcode::DBG_LABEL:
372 case TargetOpcode::EH_LABEL:
373 case TargetOpcode::IMPLICIT_DEF:
374 case TargetOpcode::KILL:
375 case TargetOpcode::DBG_VALUE:
377 case TargetOpcode::INLINEASM: {
378 const MachineFunction *MF = MI->getParent()->getParent();
379 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
380 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
381 *MF->getTarget().getMCAsmInfo());
384 case MSP430II::SizeSpecial:
385 switch (MI->getOpcode()) {
387 assert(0 && "Unknown instruction size!");
388 case MSP430::SAR8r1c:
389 case MSP430::SAR16r1c:
392 case MSP430II::Size2Bytes:
394 case MSP430II::Size4Bytes:
396 case MSP430II::Size6Bytes: