1 //===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430InstrInfo.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430TargetMachine.h"
18 #include "MSP430GenInstrInfo.inc"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/Support/ErrorHandling.h"
28 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
29 : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)),
30 RI(tm, *this), TM(tm) {}
32 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
33 MachineBasicBlock::iterator MI,
34 unsigned SrcReg, bool isKill, int FrameIdx,
35 const TargetRegisterClass *RC,
36 const TargetRegisterInfo *TRI) const {
38 if (MI != MBB.end()) DL = MI->getDebugLoc();
39 MachineFunction &MF = *MBB.getParent();
40 MachineFrameInfo &MFI = *MF.getFrameInfo();
42 MachineMemOperand *MMO =
43 MF.getMachineMemOperand(
44 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
45 MachineMemOperand::MOStore,
46 MFI.getObjectSize(FrameIdx),
47 MFI.getObjectAlignment(FrameIdx));
49 if (RC == &MSP430::GR16RegClass)
50 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
51 .addFrameIndex(FrameIdx).addImm(0)
52 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
53 else if (RC == &MSP430::GR8RegClass)
54 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
55 .addFrameIndex(FrameIdx).addImm(0)
56 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
58 llvm_unreachable("Cannot store this register to stack slot!");
61 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MI,
63 unsigned DestReg, int FrameIdx,
64 const TargetRegisterClass *RC,
65 const TargetRegisterInfo *TRI) const{
67 if (MI != MBB.end()) DL = MI->getDebugLoc();
68 MachineFunction &MF = *MBB.getParent();
69 MachineFrameInfo &MFI = *MF.getFrameInfo();
71 MachineMemOperand *MMO =
72 MF.getMachineMemOperand(
73 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
74 MachineMemOperand::MOLoad,
75 MFI.getObjectSize(FrameIdx),
76 MFI.getObjectAlignment(FrameIdx));
78 if (RC == &MSP430::GR16RegClass)
79 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
80 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
81 else if (RC == &MSP430::GR8RegClass)
82 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
85 llvm_unreachable("Cannot store this register to stack slot!");
88 void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator I, DebugLoc DL,
90 unsigned DestReg, unsigned SrcReg,
93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
94 Opc = MSP430::MOV16rr;
95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
98 llvm_unreachable("Impossible reg-to-reg copy");
100 BuildMI(MBB, I, DL, get(Opc), DestReg)
101 .addReg(SrcReg, getKillRegState(KillSrc));
104 unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
105 MachineBasicBlock::iterator I = MBB.end();
108 while (I != MBB.begin()) {
110 if (I->isDebugValue())
112 if (I->getOpcode() != MSP430::JMP &&
113 I->getOpcode() != MSP430::JCC &&
114 I->getOpcode() != MSP430::Br &&
115 I->getOpcode() != MSP430::Bm)
117 // Remove the branch.
118 I->eraseFromParent();
126 bool MSP430InstrInfo::
127 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
128 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
130 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
134 assert(0 && "Invalid branch condition!");
136 case MSP430CC::COND_E:
137 CC = MSP430CC::COND_NE;
139 case MSP430CC::COND_NE:
140 CC = MSP430CC::COND_E;
142 case MSP430CC::COND_L:
143 CC = MSP430CC::COND_GE;
145 case MSP430CC::COND_GE:
146 CC = MSP430CC::COND_L;
148 case MSP430CC::COND_HS:
149 CC = MSP430CC::COND_LO;
151 case MSP430CC::COND_LO:
152 CC = MSP430CC::COND_HS;
160 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
161 const TargetInstrDesc &TID = MI->getDesc();
162 if (!TID.isTerminator()) return false;
164 // Conditional branch is a special case.
165 if (TID.isBranch() && !TID.isBarrier())
167 if (!TID.isPredicable())
169 return !isPredicated(MI);
172 bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
173 MachineBasicBlock *&TBB,
174 MachineBasicBlock *&FBB,
175 SmallVectorImpl<MachineOperand> &Cond,
176 bool AllowModify) const {
177 // Start from the bottom of the block and work up, examining the
178 // terminator instructions.
179 MachineBasicBlock::iterator I = MBB.end();
180 while (I != MBB.begin()) {
182 if (I->isDebugValue())
185 // Working from the bottom, when we see a non-terminator
186 // instruction, we're done.
187 if (!isUnpredicatedTerminator(I))
190 // A terminator that isn't a branch can't easily be handled
192 if (!I->getDesc().isBranch())
195 // Cannot handle indirect branches.
196 if (I->getOpcode() == MSP430::Br ||
197 I->getOpcode() == MSP430::Bm)
200 // Handle unconditional branches.
201 if (I->getOpcode() == MSP430::JMP) {
203 TBB = I->getOperand(0).getMBB();
207 // If the block has any instructions after a JMP, delete them.
208 while (llvm::next(I) != MBB.end())
209 llvm::next(I)->eraseFromParent();
213 // Delete the JMP if it's equivalent to a fall-through.
214 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
216 I->eraseFromParent();
221 // TBB is used to indicate the unconditinal destination.
222 TBB = I->getOperand(0).getMBB();
226 // Handle conditional branches.
227 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
228 MSP430CC::CondCodes BranchCode =
229 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
230 if (BranchCode == MSP430CC::COND_INVALID)
231 return true; // Can't handle weird stuff.
233 // Working from the bottom, handle the first conditional branch.
236 TBB = I->getOperand(0).getMBB();
237 Cond.push_back(MachineOperand::CreateImm(BranchCode));
241 // Handle subsequent conditional branches. Only handle the case where all
242 // conditional branches branch to the same destination.
243 assert(Cond.size() == 1);
246 // Only handle the case where all conditional branches branch to
247 // the same destination.
248 if (TBB != I->getOperand(0).getMBB())
251 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
252 // If the conditions are the same, we can leave them alone.
253 if (OldBranchCode == BranchCode)
263 MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
264 MachineBasicBlock *FBB,
265 const SmallVectorImpl<MachineOperand> &Cond,
267 // Shouldn't be a fall through.
268 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
269 assert((Cond.size() == 1 || Cond.size() == 0) &&
270 "MSP430 branch conditions have one component!");
273 // Unconditional branch?
274 assert(!FBB && "Unconditional branch with multiple successors!");
275 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
279 // Conditional branch.
281 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
285 // Two-way Conditional branch. Insert the second branch.
286 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
292 /// GetInstSize - Return the number of bytes of code the specified
293 /// instruction may be. This returns the maximum number of bytes.
295 unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
296 const TargetInstrDesc &Desc = MI->getDesc();
298 switch (Desc.TSFlags & MSP430II::SizeMask) {
300 switch (Desc.getOpcode()) {
302 assert(0 && "Unknown instruction size!");
303 case TargetOpcode::PROLOG_LABEL:
304 case TargetOpcode::EH_LABEL:
305 case TargetOpcode::IMPLICIT_DEF:
306 case TargetOpcode::KILL:
307 case TargetOpcode::DBG_VALUE:
309 case TargetOpcode::INLINEASM: {
310 const MachineFunction *MF = MI->getParent()->getParent();
311 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
312 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
313 *MF->getTarget().getMCAsmInfo());
316 case MSP430II::SizeSpecial:
317 switch (MI->getOpcode()) {
319 assert(0 && "Unknown instruction size!");
320 case MSP430::SAR8r1c:
321 case MSP430::SAR16r1c:
324 case MSP430II::Size2Bytes:
326 case MSP430II::Size4Bytes:
328 case MSP430II::Size6Bytes: