1 //===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430InstrInfo.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430TargetMachine.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/TargetRegistry.h"
26 #define GET_INSTRINFO_CTOR
27 #include "MSP430GenInstrInfo.inc"
31 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
32 : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
33 RI(tm, *this), TM(tm) {}
35 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator MI,
37 unsigned SrcReg, bool isKill, int FrameIdx,
38 const TargetRegisterClass *RC,
39 const TargetRegisterInfo *TRI) const {
41 if (MI != MBB.end()) DL = MI->getDebugLoc();
42 MachineFunction &MF = *MBB.getParent();
43 MachineFrameInfo &MFI = *MF.getFrameInfo();
45 MachineMemOperand *MMO =
46 MF.getMachineMemOperand(
47 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
48 MachineMemOperand::MOStore,
49 MFI.getObjectSize(FrameIdx),
50 MFI.getObjectAlignment(FrameIdx));
52 if (RC == &MSP430::GR16RegClass)
53 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
54 .addFrameIndex(FrameIdx).addImm(0)
55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
56 else if (RC == &MSP430::GR8RegClass)
57 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
58 .addFrameIndex(FrameIdx).addImm(0)
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
61 llvm_unreachable("Cannot store this register to stack slot!");
64 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator MI,
66 unsigned DestReg, int FrameIdx,
67 const TargetRegisterClass *RC,
68 const TargetRegisterInfo *TRI) const{
70 if (MI != MBB.end()) DL = MI->getDebugLoc();
71 MachineFunction &MF = *MBB.getParent();
72 MachineFrameInfo &MFI = *MF.getFrameInfo();
74 MachineMemOperand *MMO =
75 MF.getMachineMemOperand(
76 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
77 MachineMemOperand::MOLoad,
78 MFI.getObjectSize(FrameIdx),
79 MFI.getObjectAlignment(FrameIdx));
81 if (RC == &MSP430::GR16RegClass)
82 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
84 else if (RC == &MSP430::GR8RegClass)
85 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
86 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
88 llvm_unreachable("Cannot store this register to stack slot!");
91 void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator I, DebugLoc DL,
93 unsigned DestReg, unsigned SrcReg,
96 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
97 Opc = MSP430::MOV16rr;
98 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
101 llvm_unreachable("Impossible reg-to-reg copy");
103 BuildMI(MBB, I, DL, get(Opc), DestReg)
104 .addReg(SrcReg, getKillRegState(KillSrc));
107 unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
108 MachineBasicBlock::iterator I = MBB.end();
111 while (I != MBB.begin()) {
113 if (I->isDebugValue())
115 if (I->getOpcode() != MSP430::JMP &&
116 I->getOpcode() != MSP430::JCC &&
117 I->getOpcode() != MSP430::Br &&
118 I->getOpcode() != MSP430::Bm)
120 // Remove the branch.
121 I->eraseFromParent();
129 bool MSP430InstrInfo::
130 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
131 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
137 assert(0 && "Invalid branch condition!");
139 case MSP430CC::COND_E:
140 CC = MSP430CC::COND_NE;
142 case MSP430CC::COND_NE:
143 CC = MSP430CC::COND_E;
145 case MSP430CC::COND_L:
146 CC = MSP430CC::COND_GE;
148 case MSP430CC::COND_GE:
149 CC = MSP430CC::COND_L;
151 case MSP430CC::COND_HS:
152 CC = MSP430CC::COND_LO;
154 case MSP430CC::COND_LO:
155 CC = MSP430CC::COND_HS;
163 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
164 const MCInstrDesc &MCID = MI->getDesc();
165 if (!MCID.isTerminator()) return false;
167 // Conditional branch is a special case.
168 if (MCID.isBranch() && !MCID.isBarrier())
170 if (!MCID.isPredicable())
172 return !isPredicated(MI);
175 bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
176 MachineBasicBlock *&TBB,
177 MachineBasicBlock *&FBB,
178 SmallVectorImpl<MachineOperand> &Cond,
179 bool AllowModify) const {
180 // Start from the bottom of the block and work up, examining the
181 // terminator instructions.
182 MachineBasicBlock::iterator I = MBB.end();
183 while (I != MBB.begin()) {
185 if (I->isDebugValue())
188 // Working from the bottom, when we see a non-terminator
189 // instruction, we're done.
190 if (!isUnpredicatedTerminator(I))
193 // A terminator that isn't a branch can't easily be handled
195 if (!I->getDesc().isBranch())
198 // Cannot handle indirect branches.
199 if (I->getOpcode() == MSP430::Br ||
200 I->getOpcode() == MSP430::Bm)
203 // Handle unconditional branches.
204 if (I->getOpcode() == MSP430::JMP) {
206 TBB = I->getOperand(0).getMBB();
210 // If the block has any instructions after a JMP, delete them.
211 while (llvm::next(I) != MBB.end())
212 llvm::next(I)->eraseFromParent();
216 // Delete the JMP if it's equivalent to a fall-through.
217 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
219 I->eraseFromParent();
224 // TBB is used to indicate the unconditinal destination.
225 TBB = I->getOperand(0).getMBB();
229 // Handle conditional branches.
230 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
231 MSP430CC::CondCodes BranchCode =
232 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
233 if (BranchCode == MSP430CC::COND_INVALID)
234 return true; // Can't handle weird stuff.
236 // Working from the bottom, handle the first conditional branch.
239 TBB = I->getOperand(0).getMBB();
240 Cond.push_back(MachineOperand::CreateImm(BranchCode));
244 // Handle subsequent conditional branches. Only handle the case where all
245 // conditional branches branch to the same destination.
246 assert(Cond.size() == 1);
249 // Only handle the case where all conditional branches branch to
250 // the same destination.
251 if (TBB != I->getOperand(0).getMBB())
254 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
255 // If the conditions are the same, we can leave them alone.
256 if (OldBranchCode == BranchCode)
266 MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
267 MachineBasicBlock *FBB,
268 const SmallVectorImpl<MachineOperand> &Cond,
270 // Shouldn't be a fall through.
271 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
272 assert((Cond.size() == 1 || Cond.size() == 0) &&
273 "MSP430 branch conditions have one component!");
276 // Unconditional branch?
277 assert(!FBB && "Unconditional branch with multiple successors!");
278 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
282 // Conditional branch.
284 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
288 // Two-way Conditional branch. Insert the second branch.
289 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
295 /// GetInstSize - Return the number of bytes of code the specified
296 /// instruction may be. This returns the maximum number of bytes.
298 unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
299 const MCInstrDesc &Desc = MI->getDesc();
301 switch (Desc.TSFlags & MSP430II::SizeMask) {
303 switch (Desc.getOpcode()) {
305 assert(0 && "Unknown instruction size!");
306 case TargetOpcode::PROLOG_LABEL:
307 case TargetOpcode::EH_LABEL:
308 case TargetOpcode::IMPLICIT_DEF:
309 case TargetOpcode::KILL:
310 case TargetOpcode::DBG_VALUE:
312 case TargetOpcode::INLINEASM: {
313 const MachineFunction *MF = MI->getParent()->getParent();
314 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
315 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
316 *MF->getTarget().getMCAsmInfo());
319 case MSP430II::SizeSpecial:
320 switch (MI->getOpcode()) {
322 assert(0 && "Unknown instruction size!");
323 case MSP430::SAR8r1c:
324 case MSP430::SAR16r1c:
327 case MSP430II::Size2Bytes:
329 case MSP430II::Size4Bytes:
331 case MSP430II::Size6Bytes: