1 //===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430InstrInfo.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430TargetMachine.h"
18 #include "MSP430GenInstrInfo.inc"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/Support/ErrorHandling.h"
28 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
29 : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)),
30 RI(tm, *this), TM(tm) {}
32 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
33 MachineBasicBlock::iterator MI,
34 unsigned SrcReg, bool isKill, int FrameIdx,
35 const TargetRegisterClass *RC,
36 const TargetRegisterInfo *TRI) const {
38 if (MI != MBB.end()) DL = MI->getDebugLoc();
39 MachineFunction &MF = *MBB.getParent();
40 MachineFrameInfo &MFI = *MF.getFrameInfo();
42 MachineMemOperand *MMO =
43 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
44 MachineMemOperand::MOStore, 0,
45 MFI.getObjectSize(FrameIdx),
46 MFI.getObjectAlignment(FrameIdx));
48 if (RC == &MSP430::GR16RegClass)
49 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
50 .addFrameIndex(FrameIdx).addImm(0)
51 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
52 else if (RC == &MSP430::GR8RegClass)
53 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
54 .addFrameIndex(FrameIdx).addImm(0)
55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
57 llvm_unreachable("Cannot store this register to stack slot!");
60 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MI,
62 unsigned DestReg, int FrameIdx,
63 const TargetRegisterClass *RC,
64 const TargetRegisterInfo *TRI) const{
66 if (MI != MBB.end()) DL = MI->getDebugLoc();
67 MachineFunction &MF = *MBB.getParent();
68 MachineFrameInfo &MFI = *MF.getFrameInfo();
70 MachineMemOperand *MMO =
71 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
72 MachineMemOperand::MOLoad, 0,
73 MFI.getObjectSize(FrameIdx),
74 MFI.getObjectAlignment(FrameIdx));
76 if (RC == &MSP430::GR16RegClass)
77 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
78 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
79 else if (RC == &MSP430::GR8RegClass)
80 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
81 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
83 llvm_unreachable("Cannot store this register to stack slot!");
86 void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator I, DebugLoc DL,
88 unsigned DestReg, unsigned SrcReg,
91 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
92 Opc = MSP430::MOV16rr;
93 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
96 llvm_unreachable("Impossible reg-to-reg copy");
98 BuildMI(MBB, I, DL, get(Opc), DestReg)
99 .addReg(SrcReg, getKillRegState(KillSrc));
103 MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
104 MachineBasicBlock::iterator MI,
105 const std::vector<CalleeSavedInfo> &CSI,
106 const TargetRegisterInfo *TRI) const {
111 if (MI != MBB.end()) DL = MI->getDebugLoc();
113 MachineFunction &MF = *MBB.getParent();
114 MSP430MachineFunctionInfo *MFI = MF.getInfo<MSP430MachineFunctionInfo>();
115 MFI->setCalleeSavedFrameSize(CSI.size() * 2);
117 for (unsigned i = CSI.size(); i != 0; --i) {
118 unsigned Reg = CSI[i-1].getReg();
119 // Add the callee-saved register as live-in. It's killed at the spill.
121 BuildMI(MBB, MI, DL, get(MSP430::PUSH16r))
122 .addReg(Reg, RegState::Kill);
128 MSP430InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
129 MachineBasicBlock::iterator MI,
130 const std::vector<CalleeSavedInfo> &CSI,
131 const TargetRegisterInfo *TRI) const {
136 if (MI != MBB.end()) DL = MI->getDebugLoc();
138 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
139 BuildMI(MBB, MI, DL, get(MSP430::POP16r), CSI[i].getReg());
144 unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
145 MachineBasicBlock::iterator I = MBB.end();
148 while (I != MBB.begin()) {
150 if (I->isDebugValue())
152 if (I->getOpcode() != MSP430::JMP &&
153 I->getOpcode() != MSP430::JCC &&
154 I->getOpcode() != MSP430::Br &&
155 I->getOpcode() != MSP430::Bm)
157 // Remove the branch.
158 I->eraseFromParent();
166 bool MSP430InstrInfo::
167 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
168 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
170 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
174 assert(0 && "Invalid branch condition!");
176 case MSP430CC::COND_E:
177 CC = MSP430CC::COND_NE;
179 case MSP430CC::COND_NE:
180 CC = MSP430CC::COND_E;
182 case MSP430CC::COND_L:
183 CC = MSP430CC::COND_GE;
185 case MSP430CC::COND_GE:
186 CC = MSP430CC::COND_L;
188 case MSP430CC::COND_HS:
189 CC = MSP430CC::COND_LO;
191 case MSP430CC::COND_LO:
192 CC = MSP430CC::COND_HS;
200 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
201 const TargetInstrDesc &TID = MI->getDesc();
202 if (!TID.isTerminator()) return false;
204 // Conditional branch is a special case.
205 if (TID.isBranch() && !TID.isBarrier())
207 if (!TID.isPredicable())
209 return !isPredicated(MI);
212 bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
213 MachineBasicBlock *&TBB,
214 MachineBasicBlock *&FBB,
215 SmallVectorImpl<MachineOperand> &Cond,
216 bool AllowModify) const {
217 // Start from the bottom of the block and work up, examining the
218 // terminator instructions.
219 MachineBasicBlock::iterator I = MBB.end();
220 while (I != MBB.begin()) {
222 if (I->isDebugValue())
225 // Working from the bottom, when we see a non-terminator
226 // instruction, we're done.
227 if (!isUnpredicatedTerminator(I))
230 // A terminator that isn't a branch can't easily be handled
232 if (!I->getDesc().isBranch())
235 // Cannot handle indirect branches.
236 if (I->getOpcode() == MSP430::Br ||
237 I->getOpcode() == MSP430::Bm)
240 // Handle unconditional branches.
241 if (I->getOpcode() == MSP430::JMP) {
243 TBB = I->getOperand(0).getMBB();
247 // If the block has any instructions after a JMP, delete them.
248 while (llvm::next(I) != MBB.end())
249 llvm::next(I)->eraseFromParent();
253 // Delete the JMP if it's equivalent to a fall-through.
254 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
256 I->eraseFromParent();
261 // TBB is used to indicate the unconditinal destination.
262 TBB = I->getOperand(0).getMBB();
266 // Handle conditional branches.
267 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
268 MSP430CC::CondCodes BranchCode =
269 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
270 if (BranchCode == MSP430CC::COND_INVALID)
271 return true; // Can't handle weird stuff.
273 // Working from the bottom, handle the first conditional branch.
276 TBB = I->getOperand(0).getMBB();
277 Cond.push_back(MachineOperand::CreateImm(BranchCode));
281 // Handle subsequent conditional branches. Only handle the case where all
282 // conditional branches branch to the same destination.
283 assert(Cond.size() == 1);
286 // Only handle the case where all conditional branches branch to
287 // the same destination.
288 if (TBB != I->getOperand(0).getMBB())
291 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
292 // If the conditions are the same, we can leave them alone.
293 if (OldBranchCode == BranchCode)
303 MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
304 MachineBasicBlock *FBB,
305 const SmallVectorImpl<MachineOperand> &Cond,
307 // Shouldn't be a fall through.
308 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
309 assert((Cond.size() == 1 || Cond.size() == 0) &&
310 "MSP430 branch conditions have one component!");
313 // Unconditional branch?
314 assert(!FBB && "Unconditional branch with multiple successors!");
315 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
319 // Conditional branch.
321 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
325 // Two-way Conditional branch. Insert the second branch.
326 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
332 /// GetInstSize - Return the number of bytes of code the specified
333 /// instruction may be. This returns the maximum number of bytes.
335 unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
336 const TargetInstrDesc &Desc = MI->getDesc();
338 switch (Desc.TSFlags & MSP430II::SizeMask) {
340 switch (Desc.getOpcode()) {
342 assert(0 && "Unknown instruction size!");
343 case TargetOpcode::PROLOG_LABEL:
344 case TargetOpcode::EH_LABEL:
345 case TargetOpcode::IMPLICIT_DEF:
346 case TargetOpcode::KILL:
347 case TargetOpcode::DBG_VALUE:
349 case TargetOpcode::INLINEASM: {
350 const MachineFunction *MF = MI->getParent()->getParent();
351 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
352 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
353 *MF->getTarget().getMCAsmInfo());
356 case MSP430II::SizeSpecial:
357 switch (MI->getOpcode()) {
359 assert(0 && "Unknown instruction size!");
360 case MSP430::SAR8r1c:
361 case MSP430::SAR16r1c:
364 case MSP430II::Size2Bytes:
366 case MSP430II::Size4Bytes:
368 case MSP430II::Size6Bytes: