1 //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the MSP430 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "MSP430InstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
25 def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
27 def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
29 //===----------------------------------------------------------------------===//
30 // MSP430 Specific Node Definitions.
31 //===----------------------------------------------------------------------===//
32 def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
33 [SDNPHasChain, SDNPOptInFlag]>;
35 def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
37 def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
38 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
39 def MSP430callseq_start :
40 SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart,
41 [SDNPHasChain, SDNPOutFlag]>;
42 def MSP430callseq_end :
43 SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd,
44 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
46 //===----------------------------------------------------------------------===//
47 // MSP430 Operand Definitions.
48 //===----------------------------------------------------------------------===//
51 def memsrc : Operand<i16> {
52 let PrintMethod = "printSrcMemOperand";
53 let MIOperandInfo = (ops i16imm, GR16);
56 def memdst : Operand<i16> {
57 let PrintMethod = "printSrcMemOperand";
58 let MIOperandInfo = (ops i16imm, GR16);
62 //===----------------------------------------------------------------------===//
63 // MSP430 Complex Pattern Definitions.
64 //===----------------------------------------------------------------------===//
66 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
68 //===----------------------------------------------------------------------===//
70 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
71 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
73 //===----------------------------------------------------------------------===//
76 // ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
77 // a stack adjustment and the codegen must know that they may modify the stack
78 // pointer before prolog-epilog rewriting occurs.
79 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
80 // sub / add which can clobber SRW.
81 let Defs = [SPW, SRW], Uses = [SPW] in {
82 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
84 [(MSP430callseq_start timm:$amt)]>;
85 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
87 [(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
91 let neverHasSideEffects = 1 in
92 def NOP : Pseudo<(outs), (ins), "nop", []>;
94 // FIXME: Provide proper encoding!
95 let isReturn = 1, isTerminator = 1 in {
96 def RET : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
99 //===----------------------------------------------------------------------===//
100 // Call Instructions...
103 // All calls clobber the non-callee saved registers. SPW is marked as
104 // a use to prevent stack-pointer assignments that appear immediately
105 // before calls from potentially appearing dead. Uses for argument
106 // registers are added manually.
107 let Defs = [R12W, R13W, R14W, R15W, SRW],
109 def CALL32r : Pseudo<(outs), (ins GR16:$dst, variable_ops),
110 "call\t{*}$dst", [(MSP430call GR16:$dst)]>;
111 def CALL32m : Pseudo<(outs), (ins memsrc:$dst, variable_ops),
112 "call\t{*}$dst", [(MSP430call (load addr:$dst))]>;
116 //===----------------------------------------------------------------------===//
119 // FIXME: Provide proper encoding!
120 let neverHasSideEffects = 1 in {
121 def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
122 "mov.b\t{$src, $dst|$dst, $src}",
124 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
125 "mov.w\t{$src, $dst|$dst, $src}",
129 // FIXME: Provide proper encoding!
130 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
131 def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
132 "mov.b\t{$src, $dst|$dst, $src}",
133 [(set GR8:$dst, imm:$src)]>;
134 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
135 "mov.w\t{$src, $dst|$dst, $src}",
136 [(set GR16:$dst, imm:$src)]>;
139 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
140 def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
141 "mov.b\t{$src, $dst|$dst, $src}",
142 [(set GR8:$dst, (load addr:$src))]>;
143 def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
144 "mov.w\t{$src, $dst|$dst, $src}",
145 [(set GR16:$dst, (load addr:$src))]>;
148 def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
149 "mov.b\t{$src, $dst|$dst, $src}",
150 [(set GR16:$dst, (zext GR8:$src))]>;
151 def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
152 "mov.b\t{$src, $dst|$dst, $src}",
153 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
155 def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
156 "mov.b\t{$src, $dst|$dst, $src}",
157 [(store (i8 imm:$src), addr:$dst)]>;
158 def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
159 "mov.w\t{$src, $dst|$dst, $src}",
160 [(store (i16 imm:$src), addr:$dst)]>;
162 def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
163 "mov.b\t{$src, $dst|$dst, $src}",
164 [(store GR8:$src, addr:$dst)]>;
165 def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
166 "mov.w\t{$src, $dst|$dst, $src}",
167 [(store GR16:$src, addr:$dst)]>;
169 //===----------------------------------------------------------------------===//
170 // Arithmetic Instructions
172 let isTwoAddress = 1 in {
174 let Defs = [SRW] in {
176 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
177 // FIXME: Provide proper encoding!
178 def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
179 "add.b\t{$src2, $dst|$dst, $src2}",
180 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
182 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
183 "add.w\t{$src2, $dst|$dst, $src2}",
184 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
188 def ADD8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
189 "add.b\t{$src2, $dst|$dst, $src2}",
190 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
192 def ADD16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
193 "add.w\t{$src2, $dst|$dst, $src2}",
194 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
197 def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
198 "add.b\t{$src2, $dst|$dst, $src2}",
199 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
201 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
202 "add.w\t{$src2, $dst|$dst, $src2}",
203 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
206 let isTwoAddress = 0 in {
207 def ADD8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
208 "add.b\t{$src, $dst|$dst, $src}",
209 [(store (add (load addr:$dst), GR8:$src), addr:$dst),
211 def ADD16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
212 "add.w\t{$src, $dst|$dst, $src}",
213 [(store (add (load addr:$dst), GR16:$src), addr:$dst),
216 def ADD8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
217 "add.b\t{$src, $dst|$dst, $src}",
218 [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
220 def ADD16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
221 "add.w\t{$src, $dst|$dst, $src}",
222 [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
225 def ADD8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
226 "add.b\t{$src, $dst|$dst, $src}",
227 [(store (add (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
229 def ADD16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
230 "add.w\t{$src, $dst|$dst, $src}",
231 [(store (add (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
235 let Uses = [SRW] in {
237 let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
238 def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
239 "addc.b\t{$src2, $dst|$dst, $src2}",
240 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
242 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
243 "addc.w\t{$src2, $dst|$dst, $src2}",
244 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
248 def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
249 "addc.b\t{$src2, $dst|$dst, $src2}",
250 [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
252 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
253 "addc.w\t{$src2, $dst|$dst, $src2}",
254 [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
257 def ADC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
258 "addc.b\t{$src2, $dst|$dst, $src2}",
259 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2))),
261 def ADC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
262 "addc.w\t{$src2, $dst|$dst, $src2}",
263 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2))),
266 let isTwoAddress = 0 in {
267 def ADC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
268 "addc.b\t{$src, $dst|$dst, $src}",
269 [(store (adde (load addr:$dst), GR8:$src), addr:$dst),
271 def ADC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
272 "addc.w\t{$src, $dst|$dst, $src}",
273 [(store (adde (load addr:$dst), GR16:$src), addr:$dst),
276 def ADC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
277 "addc.b\t{$src, $dst|$dst, $src}",
278 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
280 def ADC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
281 "addc.w\t{$src, $dst|$dst, $src}",
282 [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
285 def ADC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
286 "addc.b\t{$src, $dst|$dst, $src}",
287 [(store (adde (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
289 def ADC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
290 "addc.w\t{$src, $dst|$dst, $src}",
291 [(store (adde (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
297 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
298 def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
299 "and.b\t{$src2, $dst|$dst, $src2}",
300 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
302 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
303 "and.w\t{$src2, $dst|$dst, $src2}",
304 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
308 def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
309 "and.b\t{$src2, $dst|$dst, $src2}",
310 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
312 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
313 "and.w\t{$src2, $dst|$dst, $src2}",
314 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
317 def AND8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
318 "and.b\t{$src2, $dst|$dst, $src2}",
319 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
321 def AND16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
322 "and.w\t{$src2, $dst|$dst, $src2}",
323 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
326 let isTwoAddress = 0 in {
327 def AND8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
328 "and.b\t{$src, $dst|$dst, $src}",
329 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
331 def AND16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
332 "and.w\t{$src, $dst|$dst, $src}",
333 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
336 def AND8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
337 "and.b\t{$src, $dst|$dst, $src}",
338 [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
340 def AND16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
341 "and.w\t{$src, $dst|$dst, $src}",
342 [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
345 def AND8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
346 "and.b\t{$src, $dst|$dst, $src}",
347 [(store (and (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
349 def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
350 "and.w\t{$src, $dst|$dst, $src}",
351 [(store (and (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
356 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
357 def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
358 "xor.b\t{$src2, $dst|$dst, $src2}",
359 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
361 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
362 "xor.w\t{$src2, $dst|$dst, $src2}",
363 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
367 def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
368 "xor.b\t{$src2, $dst|$dst, $src2}",
369 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
371 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
372 "xor.w\t{$src2, $dst|$dst, $src2}",
373 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
376 def XOR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
377 "xor.b\t{$src2, $dst|$dst, $src2}",
378 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
380 def XOR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
381 "xor.w\t{$src2, $dst|$dst, $src2}",
382 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
385 let isTwoAddress = 0 in {
386 def XOR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
387 "xor.b\t{$src, $dst|$dst, $src}",
388 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
390 def XOR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
391 "xor.w\t{$src, $dst|$dst, $src}",
392 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
395 def XOR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
396 "xor.b\t{$src, $dst|$dst, $src}",
397 [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
399 def XOR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
400 "xor.w\t{$src, $dst|$dst, $src}",
401 [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
404 def XOR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
405 "xor.b\t{$src, $dst|$dst, $src}",
406 [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
408 def XOR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
409 "xor.w\t{$src, $dst|$dst, $src}",
410 [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
415 def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
416 "sub.b\t{$src2, $dst|$dst, $src2}",
417 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
419 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
420 "sub.w\t{$src2, $dst|$dst, $src2}",
421 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
424 def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
425 "sub.b\t{$src2, $dst|$dst, $src2}",
426 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
428 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
429 "sub.w\t{$src2, $dst|$dst, $src2}",
430 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
433 def SUB8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
434 "sub.b\t{$src2, $dst|$dst, $src2}",
435 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
437 def SUB16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
438 "sub.w\t{$src2, $dst|$dst, $src2}",
439 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
442 let isTwoAddress = 0 in {
443 def SUB8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
444 "sub.b\t{$src, $dst|$dst, $src}",
445 [(store (sub (load addr:$dst), GR8:$src), addr:$dst),
447 def SUB16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
448 "sub.w\t{$src, $dst|$dst, $src}",
449 [(store (sub (load addr:$dst), GR16:$src), addr:$dst),
452 def SUB8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
453 "sub.b\t{$src, $dst|$dst, $src}",
454 [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
456 def SUB16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
457 "sub.w\t{$src, $dst|$dst, $src}",
458 [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
461 def SUB8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
462 "sub.b\t{$src, $dst|$dst, $src}",
463 [(store (sub (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
465 def SUB16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
466 "sub.w\t{$src, $dst|$dst, $src}",
467 [(store (sub (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
471 let Uses = [SRW] in {
472 def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
473 "subc.b\t{$src2, $dst|$dst, $src2}",
474 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
476 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
477 "subc.w\t{$src2, $dst|$dst, $src2}",
478 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
481 def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
482 "subc.b\t{$src2, $dst|$dst, $src2}",
483 [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
485 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
486 "subc.w\t{$src2, $dst|$dst, $src2}",
487 [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
490 def SBC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
491 "subc.b\t{$src2, $dst|$dst, $src2}",
492 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2))),
494 def SBC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
495 "subc.w\t{$src2, $dst|$dst, $src2}",
496 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2))),
499 let isTwoAddress = 0 in {
500 def SBC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
501 "subc.b\t{$src, $dst|$dst, $src}",
502 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
504 def SBC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
505 "subc.w\t{$src, $dst|$dst, $src}",
506 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
509 def SBC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
510 "subc.b\t{$src, $dst|$dst, $src}",
511 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
513 def SBC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
514 "subc.w\t{$src, $dst|$dst, $src}",
515 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
518 def SBC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
519 "subc.b\t{$src, $dst|$dst, $src}",
520 [(store (sube (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
522 def SBC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
523 "subc.w\t{$src, $dst|$dst, $src}",
524 [(store (sube (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
530 // FIXME: Provide proper encoding!
531 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
533 [(set GR16:$dst, (MSP430rra GR16:$src)),
536 def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
538 [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
541 //def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
543 // [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
548 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
549 def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
550 "bis.b\t{$src2, $dst|$dst, $src2}",
551 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
552 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
553 "bis.w\t{$src2, $dst|$dst, $src2}",
554 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
557 def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
558 "bis.b\t{$src2, $dst|$dst, $src2}",
559 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
560 def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
561 "bis.w\t{$src2, $dst|$dst, $src2}",
562 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
564 def OR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
565 "bis.b\t{$src2, $dst|$dst, $src2}",
566 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
567 def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
568 "bis.w\t{$src2, $dst|$dst, $src2}",
569 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
571 let isTwoAddress = 0 in {
572 def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
573 "bis.b\t{$src, $dst|$dst, $src}",
574 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
576 def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
577 "bis.w\t{$src, $dst|$dst, $src}",
578 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
581 def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
582 "bis.b\t{$src, $dst|$dst, $src}",
583 [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst),
585 def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
586 "bis.w\t{$src, $dst|$dst, $src}",
587 [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst),
590 def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
591 "bis.b\t{$src, $dst|$dst, $src}",
592 [(store (or (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
594 def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
595 "bis.w\t{$src, $dst|$dst, $src}",
596 [(store (or (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
600 } // isTwoAddress = 1
602 //===----------------------------------------------------------------------===//
603 // Non-Instruction Patterns
606 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
609 def : Pat<(i8 (trunc GR16:$src)),
610 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;