1 //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the MSP430 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "MSP430InstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
25 def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
27 //===----------------------------------------------------------------------===//
28 // MSP430 Specific Node Definitions.
29 //===----------------------------------------------------------------------===//
30 def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
31 [SDNPHasChain, SDNPOptInFlag]>;
33 def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
35 def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
36 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
38 //===----------------------------------------------------------------------===//
39 // MSP430 Operand Definitions.
40 //===----------------------------------------------------------------------===//
43 def memsrc : Operand<i16> {
44 let PrintMethod = "printSrcMemOperand";
45 let MIOperandInfo = (ops i16imm, GR16);
48 def memdst : Operand<i16> {
49 let PrintMethod = "printSrcMemOperand";
50 let MIOperandInfo = (ops i16imm, GR16);
54 //===----------------------------------------------------------------------===//
55 // MSP430 Complex Pattern Definitions.
56 //===----------------------------------------------------------------------===//
58 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
60 //===----------------------------------------------------------------------===//
62 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
63 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
65 //===----------------------------------------------------------------------===//
66 // Pseudo Instructions
68 let neverHasSideEffects = 1 in
69 def NOP : Pseudo<(outs), (ins), "nop", []>;
71 //===----------------------------------------------------------------------===//
74 // FIXME: Provide proper encoding!
75 let isReturn = 1, isTerminator = 1 in {
76 def RETI : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
79 //===----------------------------------------------------------------------===//
82 // FIXME: Provide proper encoding!
83 let neverHasSideEffects = 1 in {
84 def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
85 "mov.b\t{$src, $dst|$dst, $src}",
87 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
88 "mov.w\t{$src, $dst|$dst, $src}",
92 // FIXME: Provide proper encoding!
93 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
94 def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
95 "mov.b\t{$src, $dst|$dst, $src}",
96 [(set GR8:$dst, imm:$src)]>;
97 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
98 "mov.w\t{$src, $dst|$dst, $src}",
99 [(set GR16:$dst, imm:$src)]>;
102 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
103 def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
104 "mov.b\t{$src, $dst|$dst, $src}",
105 [(set GR8:$dst, (load addr:$src))]>;
106 def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
107 "mov.w\t{$src, $dst|$dst, $src}",
108 [(set GR16:$dst, (load addr:$src))]>;
111 def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
112 "mov.b\t{$src, $dst|$dst, $src}",
113 [(set GR16:$dst, (zext GR8:$src))]>;
114 def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
115 "mov.b\t{$src, $dst|$dst, $src}",
116 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
118 def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
119 "mov.b\t{$src, $dst|$dst, $src}",
120 [(store (i8 imm:$src), addr:$dst)]>;
121 def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
122 "mov.w\t{$src, $dst|$dst, $src}",
123 [(store (i16 imm:$src), addr:$dst)]>;
125 def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
126 "mov.b\t{$src, $dst|$dst, $src}",
127 [(store GR8:$src, addr:$dst)]>;
128 def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
129 "mov.w\t{$src, $dst|$dst, $src}",
130 [(store GR16:$src, addr:$dst)]>;
132 //===----------------------------------------------------------------------===//
133 // Arithmetic Instructions
135 let isTwoAddress = 1 in {
137 let Defs = [SRW] in {
139 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
140 // FIXME: Provide proper encoding!
141 def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
142 "add.b\t{$src2, $dst|$dst, $src2}",
143 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
145 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
146 "add.w\t{$src2, $dst|$dst, $src2}",
147 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
151 def ADD8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
152 "add.b\t{$src2, $dst|$dst, $src2}",
153 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
155 def ADD16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
156 "add.w\t{$src2, $dst|$dst, $src2}",
157 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
160 def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
161 "add.b\t{$src2, $dst|$dst, $src2}",
162 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
164 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
165 "add.w\t{$src2, $dst|$dst, $src2}",
166 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
169 let isTwoAddress = 0 in {
170 def ADD8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
171 "add.b\t{$src, $dst|$dst, $src}",
172 [(store (add (load addr:$dst), GR8:$src), addr:$dst),
174 def ADD16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
175 "add.w\t{$src, $dst|$dst, $src}",
176 [(store (add (load addr:$dst), GR16:$src), addr:$dst),
179 def ADD8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
180 "add.b\t{$src, $dst|$dst, $src}",
181 [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
183 def ADD16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
184 "add.w\t{$src, $dst|$dst, $src}",
185 [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
188 def ADD8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
189 "add.b\t{$src, $dst|$dst, $src}",
190 [(store (add (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
192 def ADD16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
193 "add.w\t{$src, $dst|$dst, $src}",
194 [(store (add (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
198 let Uses = [SRW] in {
200 let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
201 def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
202 "addc.b\t{$src2, $dst|$dst, $src2}",
203 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
205 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
206 "addc.w\t{$src2, $dst|$dst, $src2}",
207 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
211 def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
212 "addc.b\t{$src2, $dst|$dst, $src2}",
213 [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
215 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
216 "addc.w\t{$src2, $dst|$dst, $src2}",
217 [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
220 def ADC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
221 "addc.b\t{$src2, $dst|$dst, $src2}",
222 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2))),
224 def ADC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
225 "addc.w\t{$src2, $dst|$dst, $src2}",
226 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2))),
229 let isTwoAddress = 0 in {
230 def ADC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
231 "addc.b\t{$src, $dst|$dst, $src}",
232 [(store (adde (load addr:$dst), GR8:$src), addr:$dst),
234 def ADC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
235 "addc.w\t{$src, $dst|$dst, $src}",
236 [(store (adde (load addr:$dst), GR16:$src), addr:$dst),
239 def ADC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
240 "addc.b\t{$src, $dst|$dst, $src}",
241 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
243 def ADC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
244 "addc.w\t{$src, $dst|$dst, $src}",
245 [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
248 def ADC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
249 "addc.b\t{$src, $dst|$dst, $src}",
250 [(store (adde (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
252 def ADC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
253 "addc.w\t{$src, $dst|$dst, $src}",
254 [(store (adde (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
260 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
261 def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
262 "and.b\t{$src2, $dst|$dst, $src2}",
263 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
265 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
266 "and.w\t{$src2, $dst|$dst, $src2}",
267 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
271 def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
272 "and.b\t{$src2, $dst|$dst, $src2}",
273 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
275 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
276 "and.w\t{$src2, $dst|$dst, $src2}",
277 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
280 def AND8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
281 "and.b\t{$src2, $dst|$dst, $src2}",
282 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
284 def AND16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
285 "and.w\t{$src2, $dst|$dst, $src2}",
286 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
289 let isTwoAddress = 0 in {
290 def AND8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
291 "and.b\t{$src, $dst|$dst, $src}",
292 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
294 def AND16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
295 "and.w\t{$src, $dst|$dst, $src}",
296 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
299 def AND8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
300 "and.b\t{$src, $dst|$dst, $src}",
301 [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
303 def AND16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
304 "and.w\t{$src, $dst|$dst, $src}",
305 [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
308 def AND8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
309 "and.b\t{$src, $dst|$dst, $src}",
310 [(store (and (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
312 def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
313 "and.w\t{$src, $dst|$dst, $src}",
314 [(store (and (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
319 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
320 def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
321 "xor.b\t{$src2, $dst|$dst, $src2}",
322 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
324 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
325 "xor.w\t{$src2, $dst|$dst, $src2}",
326 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
330 def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
331 "xor.b\t{$src2, $dst|$dst, $src2}",
332 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
334 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
335 "xor.w\t{$src2, $dst|$dst, $src2}",
336 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
339 def XOR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
340 "xor.b\t{$src2, $dst|$dst, $src2}",
341 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
343 def XOR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
344 "xor.w\t{$src2, $dst|$dst, $src2}",
345 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
348 let isTwoAddress = 0 in {
349 def XOR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
350 "xor.b\t{$src, $dst|$dst, $src}",
351 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
353 def XOR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
354 "xor.w\t{$src, $dst|$dst, $src}",
355 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
358 def XOR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
359 "xor.b\t{$src, $dst|$dst, $src}",
360 [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
362 def XOR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
363 "xor.w\t{$src, $dst|$dst, $src}",
364 [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
367 def XOR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
368 "xor.b\t{$src, $dst|$dst, $src}",
369 [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
371 def XOR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
372 "xor.w\t{$src, $dst|$dst, $src}",
373 [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
378 def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
379 "sub.b\t{$src2, $dst|$dst, $src2}",
380 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
382 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
383 "sub.w\t{$src2, $dst|$dst, $src2}",
384 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
387 def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
388 "sub.b\t{$src2, $dst|$dst, $src2}",
389 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
391 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
392 "sub.w\t{$src2, $dst|$dst, $src2}",
393 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
396 def SUB8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
397 "sub.b\t{$src2, $dst|$dst, $src2}",
398 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
400 def SUB16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
401 "sub.w\t{$src2, $dst|$dst, $src2}",
402 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
405 let isTwoAddress = 0 in {
406 def SUB8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
407 "sub.b\t{$src, $dst|$dst, $src}",
408 [(store (sub (load addr:$dst), GR8:$src), addr:$dst),
410 def SUB16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
411 "sub.w\t{$src, $dst|$dst, $src}",
412 [(store (sub (load addr:$dst), GR16:$src), addr:$dst),
415 def SUB8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
416 "sub.b\t{$src, $dst|$dst, $src}",
417 [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
419 def SUB16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
420 "sub.w\t{$src, $dst|$dst, $src}",
421 [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
424 def SUB8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
425 "sub.b\t{$src, $dst|$dst, $src}",
426 [(store (sub (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
428 def SUB16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
429 "sub.w\t{$src, $dst|$dst, $src}",
430 [(store (sub (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
434 let Uses = [SRW] in {
435 def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
436 "subc.b\t{$src2, $dst|$dst, $src2}",
437 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
439 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
440 "subc.w\t{$src2, $dst|$dst, $src2}",
441 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
444 def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
445 "subc.b\t{$src2, $dst|$dst, $src2}",
446 [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
448 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
449 "subc.w\t{$src2, $dst|$dst, $src2}",
450 [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
453 def SBC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
454 "subc.b\t{$src2, $dst|$dst, $src2}",
455 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2))),
457 def SBC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
458 "subc.w\t{$src2, $dst|$dst, $src2}",
459 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2))),
462 let isTwoAddress = 0 in {
463 def SBC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
464 "subc.b\t{$src, $dst|$dst, $src}",
465 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
467 def SBC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
468 "subc.w\t{$src, $dst|$dst, $src}",
469 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
472 def SBC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
473 "subc.b\t{$src, $dst|$dst, $src}",
474 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
476 def SBC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
477 "subc.w\t{$src, $dst|$dst, $src}",
478 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
481 def SBC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
482 "subc.b\t{$src, $dst|$dst, $src}",
483 [(store (sube (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
485 def SBC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
486 "subc.w\t{$src, $dst|$dst, $src}",
487 [(store (sube (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
493 // FIXME: Provide proper encoding!
494 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
496 [(set GR16:$dst, (MSP430rra GR16:$src)),
499 def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
501 [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
504 //def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
506 // [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
511 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
512 def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
513 "bis.b\t{$src2, $dst|$dst, $src2}",
514 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
515 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
516 "bis.w\t{$src2, $dst|$dst, $src2}",
517 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
520 def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
521 "bis.b\t{$src2, $dst|$dst, $src2}",
522 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
523 def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
524 "bis.w\t{$src2, $dst|$dst, $src2}",
525 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
527 def OR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
528 "bis.b\t{$src2, $dst|$dst, $src2}",
529 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
530 def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
531 "bis.w\t{$src2, $dst|$dst, $src2}",
532 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
534 let isTwoAddress = 0 in {
535 def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
536 "bis.b\t{$src, $dst|$dst, $src}",
537 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
539 def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
540 "bis.w\t{$src, $dst|$dst, $src}",
541 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
544 def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
545 "bis.b\t{$src, $dst|$dst, $src}",
546 [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst),
548 def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
549 "bis.w\t{$src, $dst|$dst, $src}",
550 [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst),
553 def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
554 "bis.b\t{$src, $dst|$dst, $src}",
555 [(store (or (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
557 def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
558 "bis.w\t{$src, $dst|$dst, $src}",
559 [(store (or (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
563 } // isTwoAddress = 1
565 //===----------------------------------------------------------------------===//
566 // Non-Instruction Patterns
569 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
572 def : Pat<(i8 (trunc GR16:$src)),
573 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;