1 //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the MSP430 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "MSP430InstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 //===----------------------------------------------------------------------===//
27 // MSP430 Specific Node Definitions.
28 //===----------------------------------------------------------------------===//
29 def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
30 [SDNPHasChain, SDNPOptInFlag]>;
32 def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
34 //===----------------------------------------------------------------------===//
35 // Pseudo Instructions
36 //===----------------------------------------------------------------------===//
38 let neverHasSideEffects = 1 in
39 def NOP : Pseudo<(outs), (ins), "nop", []>;
41 //===----------------------------------------------------------------------===//
43 //===----------------------------------------------------------------------===//
45 // FIXME: Provide proper encoding!
46 let isReturn = 1, isTerminator = 1 in {
47 def RETI : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
50 //===----------------------------------------------------------------------===//
53 // FIXME: Provide proper encoding!
54 let neverHasSideEffects = 1 in {
55 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
56 "mov.w\t{$src, $dst|$dst, $src}",
58 def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
59 "mov.b\t{$src, $dst|$dst, $src}",
63 // FIXME: Provide proper encoding!
64 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
65 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
66 "mov.w\t{$src, $dst|$dst, $src}",
67 [(set GR16:$dst, imm:$src)]>;
68 def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
69 "mov.b\t{$src, $dst|$dst, $src}",
70 [(set GR8:$dst, imm:$src)]>;
74 //===----------------------------------------------------------------------===//
75 // Arithmetic Instructions
77 let isTwoAddress = 1 in {
81 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
82 // FIXME: Provide proper encoding!
83 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
84 "add.w\t{$src2, $dst|$dst, $src2}",
85 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
88 def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
89 "add.b\t{$src2, $dst|$dst, $src2}",
90 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
94 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
95 "add.w\t{$src2, $dst|$dst, $src2}",
96 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
98 def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
99 "add.b\t{$src2, $dst|$dst, $src2}",
100 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
103 let Uses = [SRW] in {
105 let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
106 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
107 "addc.w\t{$src2, $dst|$dst, $src2}",
108 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
110 def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
111 "addc.b\t{$src2, $dst|$dst, $src2}",
112 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
116 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
117 "addc.w\t{$src2, $dst|$dst, $src2}",
118 [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
120 def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
121 "addc.b\t{$src2, $dst|$dst, $src2}",
122 [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
126 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
127 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
128 "and.w\t{$src2, $dst|$dst, $src2}",
129 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
131 def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
132 "and.b\t{$src2, $dst|$dst, $src2}",
133 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
137 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
138 "and.w\t{$src2, $dst|$dst, $src2}",
139 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
141 def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
142 "and.b\t{$src2, $dst|$dst, $src2}",
143 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
146 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
147 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
148 "xor.w\t{$src2, $dst|$dst, $src2}",
149 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
151 def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
152 "xor.b\t{$src2, $dst|$dst, $src2}",
153 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
157 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
158 "xor.w\t{$src2, $dst|$dst, $src2}",
159 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
161 def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
162 "xor.b\t{$src2, $dst|$dst, $src2}",
163 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
167 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
168 "sub.w\t{$src2, $dst|$dst, $src2}",
169 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
171 def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
172 "sub.b\t{$src2, $dst|$dst, $src2}",
173 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
176 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
177 "sub.w\t{$src2, $dst|$dst, $src2}",
178 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
180 def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
181 "sub.b\t{$src2, $dst|$dst, $src2}",
182 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
185 let Uses = [SRW] in {
186 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
187 "subc.w\t{$src2, $dst|$dst, $src2}",
188 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
190 def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
191 "subc.b\t{$src2, $dst|$dst, $src2}",
192 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
195 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
196 "subc.w\t{$src2, $dst|$dst, $src2}",
197 [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
199 def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
200 "subc.b\t{$src2, $dst|$dst, $src2}",
201 [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
205 // FIXME: Provide proper encoding!
206 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
208 [(set GR16:$dst, (MSP430rra GR16:$src)),
211 def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
213 [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
218 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
219 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
220 "bis.w\t{$src2, $dst|$dst, $src2}",
221 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
222 def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
223 "bis.b\t{$src2, $dst|$dst, $src2}",
224 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
227 def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
228 "bis.w\t{$src2, $dst|$dst, $src2}",
229 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
230 def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
231 "bis.b\t{$src2, $dst|$dst, $src2}",
232 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
234 } // isTwoAddress = 1