1 //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the MSP430 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "MSP430InstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
25 def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
27 def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
28 def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
29 def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
30 def SDT_MSP430BrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>,
32 def SDT_MSP430SelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
35 //===----------------------------------------------------------------------===//
36 // MSP430 Specific Node Definitions.
37 //===----------------------------------------------------------------------===//
38 def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
39 [SDNPHasChain, SDNPOptInFlag]>;
41 def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
42 def MSP430rla : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>;
43 def MSP430rrc : SDNode<"MSP430ISD::RRC", SDTIntUnaryOp, []>;
45 def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
46 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
47 def MSP430callseq_start :
48 SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart,
49 [SDNPHasChain, SDNPOutFlag]>;
50 def MSP430callseq_end :
51 SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd,
52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
53 def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>;
54 def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp, [SDNPOutFlag]>;
55 def MSP430brcc : SDNode<"MSP430ISD::BR_CC", SDT_MSP430BrCC, [SDNPHasChain, SDNPInFlag]>;
56 def MSP430selectcc: SDNode<"MSP430ISD::SELECT_CC", SDT_MSP430SelectCC, [SDNPInFlag]>;
58 //===----------------------------------------------------------------------===//
59 // MSP430 Operand Definitions.
60 //===----------------------------------------------------------------------===//
63 def memsrc : Operand<i16> {
64 let PrintMethod = "printSrcMemOperand";
65 let MIOperandInfo = (ops GR16, i16imm);
68 def memdst : Operand<i16> {
69 let PrintMethod = "printSrcMemOperand";
70 let MIOperandInfo = (ops GR16, i16imm);
73 // Branch targets have OtherVT type.
74 def brtarget : Operand<OtherVT>;
76 // Operand for printing out a condition code.
77 def cc : Operand<i8> {
78 let PrintMethod = "printCCOperand";
81 //===----------------------------------------------------------------------===//
82 // MSP430 Complex Pattern Definitions.
83 //===----------------------------------------------------------------------===//
85 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
87 //===----------------------------------------------------------------------===//
89 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
90 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
92 //===----------------------------------------------------------------------===//
95 // ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
96 // a stack adjustment and the codegen must know that they may modify the stack
97 // pointer before prolog-epilog rewriting occurs.
98 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
99 // sub / add which can clobber SRW.
100 let Defs = [SPW, SRW], Uses = [SPW] in {
101 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
103 [(MSP430callseq_start timm:$amt)]>;
104 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
106 [(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
109 let usesCustomDAGSchedInserter = 1 in {
110 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cc),
113 (MSP430selectcc GR8:$src1, GR8:$src2, imm:$cc))]>;
114 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cc),
117 (MSP430selectcc GR16:$src1, GR16:$src2, imm:$cc))]>;
120 let neverHasSideEffects = 1 in
121 def NOP : Pseudo<(outs), (ins), "nop", []>;
123 //===----------------------------------------------------------------------===//
124 // Control Flow Instructions...
127 // FIXME: Provide proper encoding!
128 let isReturn = 1, isTerminator = 1 in {
129 def RET : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
132 let isBranch = 1, isTerminator = 1 in {
136 def JMP : Pseudo<(outs), (ins brtarget:$dst),
140 // Conditional branches
142 def JCC : Pseudo<(outs), (ins brtarget:$dst, cc:$cc),
144 [(MSP430brcc bb:$dst, imm:$cc)]>;
145 } // isBranch, isTerminator
147 //===----------------------------------------------------------------------===//
148 // Call Instructions...
151 // All calls clobber the non-callee saved registers. SPW is marked as
152 // a use to prevent stack-pointer assignments that appear immediately
153 // before calls from potentially appearing dead. Uses for argument
154 // registers are added manually.
155 let Defs = [R12W, R13W, R14W, R15W, SRW],
157 def CALLi : Pseudo<(outs), (ins i16imm:$dst, variable_ops),
158 "call\t$dst", [(MSP430call imm:$dst)]>;
159 def CALLr : Pseudo<(outs), (ins GR16:$dst, variable_ops),
160 "call\t$dst", [(MSP430call GR16:$dst)]>;
161 def CALLm : Pseudo<(outs), (ins memsrc:$dst, variable_ops),
162 "call\t${dst:mem}", [(MSP430call (load addr:$dst))]>;
166 //===----------------------------------------------------------------------===//
167 // Miscellaneous Instructions...
169 let Defs = [SPW], Uses = [SPW], neverHasSideEffects=1 in {
171 def POP16r : Pseudo<(outs GR16:$reg), (ins), "pop.w\t$reg", []>;
174 def PUSH16r : Pseudo<(outs), (ins GR16:$reg), "push.w\t$reg",[]>;
177 //===----------------------------------------------------------------------===//
180 // FIXME: Provide proper encoding!
181 let neverHasSideEffects = 1 in {
182 def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
183 "mov.b\t{$src, $dst}",
185 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
186 "mov.w\t{$src, $dst}",
190 // FIXME: Provide proper encoding!
191 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
192 def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
193 "mov.b\t{$src, $dst}",
194 [(set GR8:$dst, imm:$src)]>;
195 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
196 "mov.w\t{$src, $dst}",
197 [(set GR16:$dst, imm:$src)]>;
200 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
201 def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
202 "mov.b\t{$src, $dst}",
203 [(set GR8:$dst, (load addr:$src))]>;
204 def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
205 "mov.w\t{$src, $dst}",
206 [(set GR16:$dst, (load addr:$src))]>;
209 def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
210 "mov.b\t{$src, $dst}",
211 [(set GR16:$dst, (zext GR8:$src))]>;
212 def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
213 "mov.b\t{$src, $dst}",
214 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
216 // Any instruction that defines a 8-bit result leaves the high half of the
217 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
218 // be copying from a truncate, but any other 8-bit operation will zero-extend
220 def def8 : PatLeaf<(i8 GR8:$src), [{
221 return N->getOpcode() != ISD::TRUNCATE &&
222 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
223 N->getOpcode() != ISD::CopyFromReg;
226 // In the case of a 8-bit def that is known to implicitly zero-extend,
227 // we can use a SUBREG_TO_REG.
228 def : Pat<(i16 (zext def8:$src)),
229 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;
232 def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
233 "mov.b\t{$src, $dst}",
234 [(store (i8 imm:$src), addr:$dst)]>;
235 def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
236 "mov.w\t{$src, $dst}",
237 [(store (i16 imm:$src), addr:$dst)]>;
239 def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
240 "mov.b\t{$src, $dst}",
241 [(store GR8:$src, addr:$dst)]>;
242 def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
243 "mov.w\t{$src, $dst}",
244 [(store GR16:$src, addr:$dst)]>;
246 def MOV8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
247 "mov.b\t{$src, $dst}",
248 [(store (i8 (load addr:$src)), addr:$dst)]>;
249 def MOV16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
250 "mov.w\t{$src, $dst}",
251 [(store (i16 (load addr:$src)), addr:$dst)]>;
253 //===----------------------------------------------------------------------===//
254 // Arithmetic Instructions
256 let isTwoAddress = 1 in {
258 let Defs = [SRW] in {
260 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
261 // FIXME: Provide proper encoding!
262 def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
263 "add.b\t{$src2, $dst}",
264 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
266 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
267 "add.w\t{$src2, $dst}",
268 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
272 def ADD8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
273 "add.b\t{$src2, $dst}",
274 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
276 def ADD16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
277 "add.w\t{$src2, $dst}",
278 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
281 def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
282 "add.b\t{$src2, $dst}",
283 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
285 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
286 "add.w\t{$src2, $dst}",
287 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
290 let isTwoAddress = 0 in {
291 def ADD8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
292 "add.b\t{$src, $dst}",
293 [(store (add (load addr:$dst), GR8:$src), addr:$dst),
295 def ADD16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
296 "add.w\t{$src, $dst}",
297 [(store (add (load addr:$dst), GR16:$src), addr:$dst),
300 def ADD8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
301 "add.b\t{$src, $dst}",
302 [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
304 def ADD16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
305 "add.w\t{$src, $dst}",
306 [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
309 def ADD8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
310 "add.b\t{$src, $dst}",
311 [(store (add (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
313 def ADD16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
314 "add.w\t{$src, $dst}",
315 [(store (add (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
319 let Uses = [SRW] in {
321 let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
322 def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
323 "addc.b\t{$src2, $dst}",
324 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
326 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
327 "addc.w\t{$src2, $dst}",
328 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
332 def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
333 "addc.b\t{$src2, $dst}",
334 [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
336 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
337 "addc.w\t{$src2, $dst}",
338 [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
341 def ADC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
342 "addc.b\t{$src2, $dst}",
343 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2))),
345 def ADC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
346 "addc.w\t{$src2, $dst}",
347 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2))),
350 let isTwoAddress = 0 in {
351 def ADC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
352 "addc.b\t{$src, $dst}",
353 [(store (adde (load addr:$dst), GR8:$src), addr:$dst),
355 def ADC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
356 "addc.w\t{$src, $dst}",
357 [(store (adde (load addr:$dst), GR16:$src), addr:$dst),
360 def ADC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
361 "addc.b\t{$src, $dst}",
362 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
364 def ADC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
365 "addc.w\t{$src, $dst}",
366 [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
369 def ADC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
370 "addc.b\t{$src, $dst}",
371 [(store (adde (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
373 def ADC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
374 "addc.w\t{$src, $dst}",
375 [(store (adde (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
381 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
382 def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
383 "and.b\t{$src2, $dst}",
384 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
386 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
387 "and.w\t{$src2, $dst}",
388 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
392 def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
393 "and.b\t{$src2, $dst}",
394 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
396 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
397 "and.w\t{$src2, $dst}",
398 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
401 def AND8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
402 "and.b\t{$src2, $dst}",
403 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
405 def AND16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
406 "and.w\t{$src2, $dst}",
407 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
410 let isTwoAddress = 0 in {
411 def AND8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
412 "and.b\t{$src, $dst}",
413 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
415 def AND16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
416 "and.w\t{$src, $dst}",
417 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
420 def AND8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
421 "and.b\t{$src, $dst}",
422 [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
424 def AND16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
425 "and.w\t{$src, $dst}",
426 [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
429 def AND8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
430 "and.b\t{$src, $dst}",
431 [(store (and (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
433 def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
434 "and.w\t{$src, $dst}",
435 [(store (and (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
440 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
441 def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
442 "xor.b\t{$src2, $dst}",
443 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
445 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
446 "xor.w\t{$src2, $dst}",
447 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
451 def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
452 "xor.b\t{$src2, $dst}",
453 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
455 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
456 "xor.w\t{$src2, $dst}",
457 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
460 def XOR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
461 "xor.b\t{$src2, $dst}",
462 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
464 def XOR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
465 "xor.w\t{$src2, $dst}",
466 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
469 let isTwoAddress = 0 in {
470 def XOR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
471 "xor.b\t{$src, $dst}",
472 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
474 def XOR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
475 "xor.w\t{$src, $dst}",
476 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
479 def XOR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
480 "xor.b\t{$src, $dst}",
481 [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
483 def XOR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
484 "xor.w\t{$src, $dst}",
485 [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
488 def XOR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
489 "xor.b\t{$src, $dst}",
490 [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
492 def XOR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
493 "xor.w\t{$src, $dst}",
494 [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
499 def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
500 "sub.b\t{$src2, $dst}",
501 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
503 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
504 "sub.w\t{$src2, $dst}",
505 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
508 def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
509 "sub.b\t{$src2, $dst}",
510 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
512 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
513 "sub.w\t{$src2, $dst}",
514 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
517 def SUB8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
518 "sub.b\t{$src2, $dst}",
519 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
521 def SUB16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
522 "sub.w\t{$src2, $dst}",
523 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
526 let isTwoAddress = 0 in {
527 def SUB8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
528 "sub.b\t{$src, $dst}",
529 [(store (sub (load addr:$dst), GR8:$src), addr:$dst),
531 def SUB16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
532 "sub.w\t{$src, $dst}",
533 [(store (sub (load addr:$dst), GR16:$src), addr:$dst),
536 def SUB8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
537 "sub.b\t{$src, $dst}",
538 [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
540 def SUB16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
541 "sub.w\t{$src, $dst}",
542 [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
545 def SUB8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
546 "sub.b\t{$src, $dst}",
547 [(store (sub (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
549 def SUB16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
550 "sub.w\t{$src, $dst}",
551 [(store (sub (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
555 let Uses = [SRW] in {
556 def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
557 "subc.b\t{$src2, $dst}",
558 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
560 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
561 "subc.w\t{$src2, $dst}",
562 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
565 def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
566 "subc.b\t{$src2, $dst}",
567 [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
569 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
570 "subc.w\t{$src2, $dst}",
571 [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
574 def SBC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
575 "subc.b\t{$src2, $dst}",
576 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2))),
578 def SBC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
579 "subc.w\t{$src2, $dst}",
580 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2))),
583 let isTwoAddress = 0 in {
584 def SBC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
585 "subc.b\t{$src, $dst}",
586 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
588 def SBC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
589 "subc.w\t{$src, $dst}",
590 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
593 def SBC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
594 "subc.b\t{$src, $dst}",
595 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
597 def SBC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
598 "subc.w\t{$src, $dst}",
599 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
602 def SBC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
603 "subc.b\t{$src, $dst}",
604 [(store (sube (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
606 def SBC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
607 "subc.w\t{$src, $dst}",
608 [(store (sube (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
614 // FIXME: Provide proper encoding!
615 def SAR8r1 : Pseudo<(outs GR8:$dst), (ins GR8:$src),
617 [(set GR8:$dst, (MSP430rra GR8:$src)),
619 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
621 [(set GR16:$dst, (MSP430rra GR16:$src)),
624 def SHL8r1 : Pseudo<(outs GR8:$dst), (ins GR8:$src),
626 [(set GR8:$dst, (MSP430rla GR8:$src)),
628 def SHL16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
630 [(set GR16:$dst, (MSP430rla GR16:$src)),
633 def SAR8r1c : Pseudo<(outs GR8:$dst), (ins GR8:$src),
636 [(set GR8:$dst, (MSP430rrc GR8:$src)),
638 def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src),
641 [(set GR16:$dst, (MSP430rrc GR16:$src)),
644 def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
646 [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
651 def SWPB16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
653 [(set GR16:$dst, (bswap GR16:$src))]>;
655 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
656 def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
657 "bis.b\t{$src2, $dst}",
658 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
659 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
660 "bis.w\t{$src2, $dst}",
661 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
664 def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
665 "bis.b\t{$src2, $dst}",
666 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
667 def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
668 "bis.w\t{$src2, $dst}",
669 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
671 def OR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
672 "bis.b\t{$src2, $dst}",
673 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
674 def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
675 "bis.w\t{$src2, $dst}",
676 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
678 let isTwoAddress = 0 in {
679 def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
680 "bis.b\t{$src, $dst}",
681 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
682 def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
683 "bis.w\t{$src, $dst}",
684 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>;
686 def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
687 "bis.b\t{$src, $dst}",
688 [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst)]>;
689 def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
690 "bis.w\t{$src, $dst}",
691 [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst)]>;
693 def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
694 "bis.b\t{$src, $dst}",
695 [(store (or (i8 (load addr:$dst)),
696 (i8 (load addr:$src))), addr:$dst)]>;
697 def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
698 "bis.w\t{$src, $dst}",
699 [(store (or (i16 (load addr:$dst)),
700 (i16 (load addr:$src))), addr:$dst)]>;
703 } // isTwoAddress = 1
705 // Integer comparisons
706 let Defs = [SRW] in {
707 def CMP8rr : Pseudo<(outs), (ins GR8:$src1, GR8:$src2),
708 "cmp.b\t{$src1, $src2}",
709 [(MSP430cmp GR8:$src1, GR8:$src2), (implicit SRW)]>;
710 def CMP16rr : Pseudo<(outs), (ins GR16:$src1, GR16:$src2),
711 "cmp.w\t{$src1, $src2}",
712 [(MSP430cmp GR16:$src1, GR16:$src2), (implicit SRW)]>;
714 def CMP8ir : Pseudo<(outs), (ins i8imm:$src1, GR8:$src2),
715 "cmp.b\t{$src1, $src2}",
716 [(MSP430cmp imm:$src1, GR8:$src2), (implicit SRW)]>;
717 def CMP16ir : Pseudo<(outs), (ins i16imm:$src1, GR16:$src2),
718 "cmp.w\t{$src1, $src2}",
719 [(MSP430cmp imm:$src1, GR16:$src2), (implicit SRW)]>;
721 def CMP8im : Pseudo<(outs), (ins i8imm:$src1, memsrc:$src2),
722 "cmp.b\t{$src1, $src2}",
723 [(MSP430cmp (i8 imm:$src1), (load addr:$src2)), (implicit SRW)]>;
724 def CMP16im : Pseudo<(outs), (ins i16imm:$src1, memsrc:$src2),
725 "cmp.w\t{$src1, $src2}",
726 [(MSP430cmp (i16 imm:$src1), (load addr:$src2)), (implicit SRW)]>;
728 def CMP8rm : Pseudo<(outs), (ins GR8:$src1, memsrc:$src2),
729 "cmp.b\t{$src1, $src2}",
730 [(MSP430cmp GR8:$src1, (load addr:$src2)), (implicit SRW)]>;
731 def CMP16rm : Pseudo<(outs), (ins GR16:$src1, memsrc:$src2),
732 "cmp.w\t{$src1, $src2}",
733 [(MSP430cmp GR16:$src1, (load addr:$src2)), (implicit SRW)]>;
735 def CMP8mr : Pseudo<(outs), (ins memsrc:$src1, GR8:$src2),
736 "cmp.b\t{$src1, $src2}",
737 [(MSP430cmp (load addr:$src1), GR8:$src2), (implicit SRW)]>;
738 def CMP16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2),
739 "cmp.w\t{$src1, $src2}",
740 [(MSP430cmp (load addr:$src1), GR16:$src2), (implicit SRW)]>;
742 def CMP8mi0 : Pseudo<(outs), (ins memsrc:$src1),
743 "cmp.b\t{$src1, #0}",
744 [(MSP430cmp (load addr:$src1), (i8 0)), (implicit SRW)]>;
745 def CMP16mi0: Pseudo<(outs), (ins memsrc:$src1),
746 "cmp.w\t{$src1, #0}",
747 [(MSP430cmp (load addr:$src1), (i16 0)), (implicit SRW)]>;
748 def CMP8mi1 : Pseudo<(outs), (ins memsrc:$src1),
749 "cmp.b\t{$src1, #1}",
750 [(MSP430cmp (load addr:$src1), (i8 1)), (implicit SRW)]>;
751 def CMP16mi1: Pseudo<(outs), (ins memsrc:$src1),
752 "cmp.w\t{$src1, #1}",
753 [(MSP430cmp (load addr:$src1), (i16 1)), (implicit SRW)]>;
754 def CMP8mi2 : Pseudo<(outs), (ins memsrc:$src1),
755 "cmp.b\t{$src1, #2}",
756 [(MSP430cmp (load addr:$src1), (i8 2)), (implicit SRW)]>;
757 def CMP16mi2: Pseudo<(outs), (ins memsrc:$src1),
758 "cmp.w\t{$src1, #2}",
759 [(MSP430cmp (load addr:$src1), (i16 2)), (implicit SRW)]>;
760 def CMP8mi4 : Pseudo<(outs), (ins memsrc:$src1),
761 "cmp.b\t{$src1, #4}",
762 [(MSP430cmp (load addr:$src1), (i8 4)), (implicit SRW)]>;
763 def CMP16mi4: Pseudo<(outs), (ins memsrc:$src1),
764 "cmp.w\t{$src1, #4}",
765 [(MSP430cmp (load addr:$src1), (i16 4)), (implicit SRW)]>;
766 def CMP8mi8 : Pseudo<(outs), (ins memsrc:$src1),
767 "cmp.b\t{$src1, #8}",
768 [(MSP430cmp (load addr:$src1), (i8 8)), (implicit SRW)]>;
769 def CMP16mi8: Pseudo<(outs), (ins memsrc:$src1),
770 "cmp.w\t{$src1, #8}",
771 [(MSP430cmp (load addr:$src1), (i16 8)), (implicit SRW)]>;
775 //===----------------------------------------------------------------------===//
776 // Non-Instruction Patterns
779 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
782 def : Pat<(anyext addr:$src), (MOVZX16rr8 GR8:$src)>;
785 def : Pat<(i8 (trunc GR16:$src)),
786 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
788 // GlobalAddress, ExternalSymbol
789 def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>;
790 def : Pat<(i16 (MSP430Wrapper texternalsym:$dst)), (MOV16ri texternalsym:$dst)>;
792 def : Pat<(add GR16:$src1, (MSP430Wrapper tglobaladdr :$src2)),
793 (ADD16ri GR16:$src1, tglobaladdr:$src2)>;
794 def : Pat<(add GR16:$src1, (MSP430Wrapper texternalsym:$src2)),
795 (ADD16ri GR16:$src1, texternalsym:$src2)>;
797 def : Pat<(store (i16 (MSP430Wrapper tglobaladdr:$src)), addr:$dst),
798 (MOV16mi addr:$dst, tglobaladdr:$src)>;
799 def : Pat<(store (i16 (MSP430Wrapper texternalsym:$src)), addr:$dst),
800 (MOV16mi addr:$dst, texternalsym:$src)>;
803 def : Pat<(MSP430call (i16 tglobaladdr:$dst)),
804 (CALLi tglobaladdr:$dst)>;
805 def : Pat<(MSP430call (i16 texternalsym:$dst)),
806 (CALLi texternalsym:$dst)>;
808 // add and sub always produce carry
809 def : Pat<(addc GR16:$src1, GR16:$src2),
810 (ADD16rr GR16:$src1, GR16:$src2)>;
811 def : Pat<(addc GR16:$src1, (load addr:$src2)),
812 (ADD16rm GR16:$src1, addr:$src2)>;
813 def : Pat<(addc GR16:$src1, imm:$src2),
814 (ADD16ri GR16:$src1, imm:$src2)>;
815 def : Pat<(store (addc (load addr:$dst), GR16:$src), addr:$dst),
816 (ADD16mr addr:$dst, GR16:$src)>;
817 def : Pat<(store (addc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
818 (ADD16mm addr:$dst, addr:$src)>;
820 def : Pat<(addc GR8:$src1, GR8:$src2),
821 (ADD8rr GR8:$src1, GR8:$src2)>;
822 def : Pat<(addc GR8:$src1, (load addr:$src2)),
823 (ADD8rm GR8:$src1, addr:$src2)>;
824 def : Pat<(addc GR8:$src1, imm:$src2),
825 (ADD8ri GR8:$src1, imm:$src2)>;
826 def : Pat<(store (addc (load addr:$dst), GR8:$src), addr:$dst),
827 (ADD8mr addr:$dst, GR8:$src)>;
828 def : Pat<(store (addc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
829 (ADD8mm addr:$dst, addr:$src)>;
831 def : Pat<(subc GR16:$src1, GR16:$src2),
832 (SUB16rr GR16:$src1, GR16:$src2)>;
833 def : Pat<(subc GR16:$src1, (load addr:$src2)),
834 (SUB16rm GR16:$src1, addr:$src2)>;
835 def : Pat<(subc GR16:$src1, imm:$src2),
836 (SUB16ri GR16:$src1, imm:$src2)>;
837 def : Pat<(store (subc (load addr:$dst), GR16:$src), addr:$dst),
838 (SUB16mr addr:$dst, GR16:$src)>;
839 def : Pat<(store (subc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
840 (SUB16mm addr:$dst, addr:$src)>;
842 def : Pat<(subc GR8:$src1, GR8:$src2),
843 (SUB8rr GR8:$src1, GR8:$src2)>;
844 def : Pat<(subc GR8:$src1, (load addr:$src2)),
845 (SUB8rm GR8:$src1, addr:$src2)>;
846 def : Pat<(subc GR8:$src1, imm:$src2),
847 (SUB8ri GR8:$src1, imm:$src2)>;
848 def : Pat<(store (subc (load addr:$dst), GR8:$src), addr:$dst),
849 (SUB8mr addr:$dst, GR8:$src)>;
850 def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
851 (SUB8mm addr:$dst, addr:$src)>;