1 //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the MSP430 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "MSP430InstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
25 def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
27 def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
28 def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
29 def SDT_MSP430SetCC : SDTypeProfile<1, 2, [SDTCisVT<0, i8>,
30 SDTCisVT<1, i8>, SDTCisVT<2, i16>]>;
31 def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
32 def SDT_MSP430BrCond : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>,
33 SDTCisVT<1, i8>, SDTCisVT<2, i16>]>;
34 def SDT_MSP430Select : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
35 SDTCisVT<3, i8>, SDTCisVT<4, i16>]>;
37 //===----------------------------------------------------------------------===//
38 // MSP430 Specific Node Definitions.
39 //===----------------------------------------------------------------------===//
40 def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
41 [SDNPHasChain, SDNPOptInFlag]>;
43 def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
44 def MSP430rla : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>;
45 def MSP430rrc : SDNode<"MSP430ISD::RRC", SDTIntUnaryOp, []>;
47 def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
48 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
49 def MSP430callseq_start :
50 SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart,
51 [SDNPHasChain, SDNPOutFlag]>;
52 def MSP430callseq_end :
53 SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd,
54 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
55 def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>;
56 def MSP430setcc : SDNode<"MSP430ISD::SETCC", SDT_MSP430SetCC>;
57 def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp>;
58 def MSP430brcond : SDNode<"MSP430ISD::BRCOND", SDT_MSP430BrCond, [SDNPHasChain]>;
59 def MSP430select : SDNode<"MSP430ISD::SELECT", SDT_MSP430Select>;
61 //===----------------------------------------------------------------------===//
62 // MSP430 Operand Definitions.
63 //===----------------------------------------------------------------------===//
66 def memsrc : Operand<i16> {
67 let PrintMethod = "printSrcMemOperand";
68 let MIOperandInfo = (ops GR16, i16imm);
71 def memdst : Operand<i16> {
72 let PrintMethod = "printSrcMemOperand";
73 let MIOperandInfo = (ops GR16, i16imm);
76 // Branch targets have OtherVT type.
77 def brtarget : Operand<OtherVT>;
79 // Operand for printing out a condition code.
80 def cc : Operand<i8> {
81 let PrintMethod = "printCCOperand";
84 //===----------------------------------------------------------------------===//
85 // MSP430 Complex Pattern Definitions.
86 //===----------------------------------------------------------------------===//
88 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
90 //===----------------------------------------------------------------------===//
92 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
93 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
95 //===----------------------------------------------------------------------===//
98 // ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
99 // a stack adjustment and the codegen must know that they may modify the stack
100 // pointer before prolog-epilog rewriting occurs.
101 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
102 // sub / add which can clobber SRW.
103 let Defs = [SPW, SRW], Uses = [SPW] in {
104 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
106 [(MSP430callseq_start timm:$amt)]>;
107 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
109 [(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
112 let usesCustomDAGSchedInserter = 1 in {
113 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cc),
116 (MSP430select GR16:$src1, GR16:$src2, imm:$cc, SRW))]>;
119 let neverHasSideEffects = 1 in
120 def NOP : Pseudo<(outs), (ins), "nop", []>;
122 //===----------------------------------------------------------------------===//
123 // Control Flow Instructions...
126 // FIXME: Provide proper encoding!
127 let isReturn = 1, isTerminator = 1 in {
128 def RET : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
131 let isBranch = 1, isTerminator = 1 in {
135 def JMP : Pseudo<(outs), (ins brtarget:$dst),
139 // Conditional branches
141 def JCC : Pseudo<(outs), (ins brtarget:$dst, cc:$cc),
143 [(MSP430brcond bb:$dst, imm:$cc, SRW)]>;
144 } // isBranch, isTerminator
146 //===----------------------------------------------------------------------===//
147 // Call Instructions...
150 // All calls clobber the non-callee saved registers. SPW is marked as
151 // a use to prevent stack-pointer assignments that appear immediately
152 // before calls from potentially appearing dead. Uses for argument
153 // registers are added manually.
154 let Defs = [R12W, R13W, R14W, R15W, SRW],
156 def CALLi : Pseudo<(outs), (ins i16imm:$dst, variable_ops),
157 "call\t${dst:call}", [(MSP430call imm:$dst)]>;
158 def CALLr : Pseudo<(outs), (ins GR16:$dst, variable_ops),
159 "call\t$dst", [(MSP430call GR16:$dst)]>;
160 def CALLm : Pseudo<(outs), (ins memsrc:$dst, variable_ops),
161 "call\t${dst:mem}", [(MSP430call (load addr:$dst))]>;
165 //===----------------------------------------------------------------------===//
166 // Miscellaneous Instructions...
168 let Defs = [SPW], Uses = [SPW], neverHasSideEffects=1 in {
170 def POP16r : Pseudo<(outs GR16:$reg), (ins), "pop.w\t$reg", []>;
173 def PUSH16r : Pseudo<(outs), (ins GR16:$reg), "push.w\t$reg",[]>;
176 //===----------------------------------------------------------------------===//
179 // FIXME: Provide proper encoding!
180 let neverHasSideEffects = 1 in {
181 def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
182 "mov.b\t{$src, $dst}",
184 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
185 "mov.w\t{$src, $dst}",
189 // FIXME: Provide proper encoding!
190 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
191 def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
192 "mov.b\t{$src, $dst}",
193 [(set GR8:$dst, imm:$src)]>;
194 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
195 "mov.w\t{$src, $dst}",
196 [(set GR16:$dst, imm:$src)]>;
199 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
200 def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
201 "mov.b\t{$src, $dst}",
202 [(set GR8:$dst, (load addr:$src))]>;
203 def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
204 "mov.w\t{$src, $dst}",
205 [(set GR16:$dst, (load addr:$src))]>;
208 def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
209 "mov.b\t{$src, $dst}",
210 [(set GR16:$dst, (zext GR8:$src))]>;
211 def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
212 "mov.b\t{$src, $dst}",
213 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
215 def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
216 "mov.b\t{$src, $dst}",
217 [(store (i8 imm:$src), addr:$dst)]>;
218 def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
219 "mov.w\t{$src, $dst}",
220 [(store (i16 imm:$src), addr:$dst)]>;
222 def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
223 "mov.b\t{$src, $dst}",
224 [(store GR8:$src, addr:$dst)]>;
225 def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
226 "mov.w\t{$src, $dst}",
227 [(store GR16:$src, addr:$dst)]>;
229 //===----------------------------------------------------------------------===//
230 // Arithmetic Instructions
232 let isTwoAddress = 1 in {
234 let Defs = [SRW] in {
236 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
237 // FIXME: Provide proper encoding!
238 def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
239 "add.b\t{$src2, $dst}",
240 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
242 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
243 "add.w\t{$src2, $dst}",
244 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
248 def ADD8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
249 "add.b\t{$src2, $dst}",
250 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
252 def ADD16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
253 "add.w\t{$src2, $dst}",
254 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
257 def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
258 "add.b\t{$src2, $dst}",
259 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
261 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
262 "add.w\t{$src2, $dst}",
263 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
266 let isTwoAddress = 0 in {
267 def ADD8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
268 "add.b\t{$src, $dst}",
269 [(store (add (load addr:$dst), GR8:$src), addr:$dst),
271 def ADD16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
272 "add.w\t{$src, $dst}",
273 [(store (add (load addr:$dst), GR16:$src), addr:$dst),
276 def ADD8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
277 "add.b\t{$src, $dst}",
278 [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
280 def ADD16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
281 "add.w\t{$src, $dst}",
282 [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
285 def ADD8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
286 "add.b\t{$src, $dst}",
287 [(store (add (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
289 def ADD16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
290 "add.w\t{$src, $dst}",
291 [(store (add (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
295 let Uses = [SRW] in {
297 let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
298 def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
299 "addc.b\t{$src2, $dst}",
300 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
302 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
303 "addc.w\t{$src2, $dst}",
304 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
308 def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
309 "addc.b\t{$src2, $dst}",
310 [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
312 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
313 "addc.w\t{$src2, $dst}",
314 [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
317 def ADC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
318 "addc.b\t{$src2, $dst}",
319 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2))),
321 def ADC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
322 "addc.w\t{$src2, $dst}",
323 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2))),
326 let isTwoAddress = 0 in {
327 def ADC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
328 "addc.b\t{$src, $dst}",
329 [(store (adde (load addr:$dst), GR8:$src), addr:$dst),
331 def ADC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
332 "addc.w\t{$src, $dst}",
333 [(store (adde (load addr:$dst), GR16:$src), addr:$dst),
336 def ADC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
337 "addc.b\t{$src, $dst}",
338 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
340 def ADC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
341 "addc.w\t{$src, $dst}",
342 [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
345 def ADC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
346 "addc.b\t{$src, $dst}",
347 [(store (adde (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
349 def ADC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
350 "addc.w\t{$src, $dst}",
351 [(store (adde (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
357 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
358 def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
359 "and.b\t{$src2, $dst}",
360 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
362 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
363 "and.w\t{$src2, $dst}",
364 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
368 def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
369 "and.b\t{$src2, $dst}",
370 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
372 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
373 "and.w\t{$src2, $dst}",
374 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
377 def AND8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
378 "and.b\t{$src2, $dst}",
379 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
381 def AND16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
382 "and.w\t{$src2, $dst}",
383 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
386 let isTwoAddress = 0 in {
387 def AND8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
388 "and.b\t{$src, $dst}",
389 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
391 def AND16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
392 "and.w\t{$src, $dst}",
393 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
396 def AND8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
397 "and.b\t{$src, $dst}",
398 [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
400 def AND16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
401 "and.w\t{$src, $dst}",
402 [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
405 def AND8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
406 "and.b\t{$src, $dst}",
407 [(store (and (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
409 def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
410 "and.w\t{$src, $dst}",
411 [(store (and (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
416 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
417 def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
418 "xor.b\t{$src2, $dst}",
419 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
421 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
422 "xor.w\t{$src2, $dst}",
423 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
427 def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
428 "xor.b\t{$src2, $dst}",
429 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
431 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
432 "xor.w\t{$src2, $dst}",
433 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
436 def XOR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
437 "xor.b\t{$src2, $dst}",
438 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
440 def XOR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
441 "xor.w\t{$src2, $dst}",
442 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
445 let isTwoAddress = 0 in {
446 def XOR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
447 "xor.b\t{$src, $dst}",
448 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
450 def XOR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
451 "xor.w\t{$src, $dst}",
452 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
455 def XOR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
456 "xor.b\t{$src, $dst}",
457 [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
459 def XOR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
460 "xor.w\t{$src, $dst}",
461 [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
464 def XOR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
465 "xor.b\t{$src, $dst}",
466 [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
468 def XOR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
469 "xor.w\t{$src, $dst}",
470 [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
475 def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
476 "sub.b\t{$src2, $dst}",
477 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
479 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
480 "sub.w\t{$src2, $dst}",
481 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
484 def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
485 "sub.b\t{$src2, $dst}",
486 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
488 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
489 "sub.w\t{$src2, $dst}",
490 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
493 def SUB8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
494 "sub.b\t{$src2, $dst}",
495 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
497 def SUB16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
498 "sub.w\t{$src2, $dst}",
499 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
502 let isTwoAddress = 0 in {
503 def SUB8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
504 "sub.b\t{$src, $dst}",
505 [(store (sub (load addr:$dst), GR8:$src), addr:$dst),
507 def SUB16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
508 "sub.w\t{$src, $dst}",
509 [(store (sub (load addr:$dst), GR16:$src), addr:$dst),
512 def SUB8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
513 "sub.b\t{$src, $dst}",
514 [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
516 def SUB16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
517 "sub.w\t{$src, $dst}",
518 [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
521 def SUB8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
522 "sub.b\t{$src, $dst}",
523 [(store (sub (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
525 def SUB16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
526 "sub.w\t{$src, $dst}",
527 [(store (sub (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
531 let Uses = [SRW] in {
532 def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
533 "subc.b\t{$src2, $dst}",
534 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
536 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
537 "subc.w\t{$src2, $dst}",
538 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
541 def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
542 "subc.b\t{$src2, $dst}",
543 [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
545 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
546 "subc.w\t{$src2, $dst}",
547 [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
550 def SBC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
551 "subc.b\t{$src2, $dst}",
552 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2))),
554 def SBC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
555 "subc.w\t{$src2, $dst}",
556 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2))),
559 let isTwoAddress = 0 in {
560 def SBC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
561 "subc.b\t{$src, $dst}",
562 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
564 def SBC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
565 "subc.w\t{$src, $dst}",
566 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
569 def SBC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
570 "subc.b\t{$src, $dst}",
571 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
573 def SBC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
574 "subc.w\t{$src, $dst}",
575 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
578 def SBC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
579 "subc.b\t{$src, $dst}",
580 [(store (sube (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
582 def SBC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
583 "subc.w\t{$src, $dst}",
584 [(store (sube (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
590 // FIXME: Provide proper encoding!
591 def SAR8r1 : Pseudo<(outs GR8:$dst), (ins GR8:$src),
593 [(set GR8:$dst, (MSP430rra GR8:$src)),
595 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
597 [(set GR16:$dst, (MSP430rra GR16:$src)),
600 def SHL8r1 : Pseudo<(outs GR8:$dst), (ins GR8:$src),
602 [(set GR8:$dst, (MSP430rla GR8:$src)),
604 def SHL16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
606 [(set GR16:$dst, (MSP430rla GR16:$src)),
609 def SAR8r1c : Pseudo<(outs GR8:$dst), (ins GR8:$src),
612 [(set GR8:$dst, (MSP430rrc GR8:$src)),
614 def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src),
617 [(set GR16:$dst, (MSP430rrc GR16:$src)),
620 def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
622 [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
627 def SWPB16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
629 [(set GR16:$dst, (bswap GR16:$src))]>;
631 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
632 def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
633 "bis.b\t{$src2, $dst}",
634 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
635 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
636 "bis.w\t{$src2, $dst}",
637 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
640 def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
641 "bis.b\t{$src2, $dst}",
642 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
643 def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
644 "bis.w\t{$src2, $dst}",
645 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
647 def OR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
648 "bis.b\t{$src2, $dst}",
649 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
650 def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
651 "bis.w\t{$src2, $dst}",
652 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
654 let isTwoAddress = 0 in {
655 def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
656 "bis.b\t{$src, $dst}",
657 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
659 def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
660 "bis.w\t{$src, $dst}",
661 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
664 def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
665 "bis.b\t{$src, $dst}",
666 [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst),
668 def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
669 "bis.w\t{$src, $dst}",
670 [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst),
673 def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
674 "bis.b\t{$src, $dst}",
675 [(store (or (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
677 def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
678 "bis.w\t{$src, $dst}",
679 [(store (or (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
683 } // isTwoAddress = 1
685 // Integer comparisons
686 let Defs = [SRW] in {
687 def CMP8rr : Pseudo<(outs), (ins GR8:$src1, GR8:$src2),
688 "cmp.b\t{$src1, $src2}",
689 [(MSP430cmp GR8:$src1, GR8:$src2), (implicit SRW)]>;
690 def CMP16rr : Pseudo<(outs), (ins GR16:$src1, GR16:$src2),
691 "cmp.w\t{$src1, $src2}",
692 [(MSP430cmp GR16:$src1, GR16:$src2), (implicit SRW)]>;
694 // FIXME: imm is allowed only on src operand, not on dst.
696 //def CMP8ri : Pseudo<(outs), (ins GR8:$src1, i8imm:$src2),
697 // "cmp.b\t{$src1, $src2}",
698 // [(MSP430cmp GR8:$src1, imm:$src2), (implicit SRW)]>;
699 //def CMP16ri : Pseudo<(outs), (ins GR16:$src1, i16imm:$src2),
700 // "cmp.w\t{$src1, $src2}",
701 // [(MSP430cmp GR16:$src1, imm:$src2), (implicit SRW)]>;
703 //def CMP8mi : Pseudo<(outs), (ins memsrc:$src1, i8imm:$src2),
704 // "cmp.b\t{$src1, $src2}",
705 // [(MSP430cmp (load addr:$src1), (i8 imm:$src2)), (implicit SRW)]>;
706 //def CMP16mi : Pseudo<(outs), (ins memsrc:$src1, i16imm:$src2),
707 // "cmp.w\t{$src1, $src2}",
708 // [(MSP430cmp (load addr:$src1), (i16 imm:$src2)), (implicit SRW)]>;
711 // Imm 0, +1, +2, +4, +8 are encoded via constant generator registers.
712 // That's why we can use them as dest operands.
713 // We don't define new class for them, since they would need special encoding
716 def CMP8ri0 : Pseudo<(outs), (ins GR8:$src1),
717 "cmp.b\t{$src1, #0}",
718 [(MSP430cmp GR8:$src1, 0), (implicit SRW)]>;
719 def CMP16ri0: Pseudo<(outs), (ins GR16:$src1),
720 "cmp.w\t{$src1, #0}",
721 [(MSP430cmp GR16:$src1, 0), (implicit SRW)]>;
722 def CMP8ri1 : Pseudo<(outs), (ins GR8:$src1),
723 "cmp.b\t{$src1, #1}",
724 [(MSP430cmp GR8:$src1, 1), (implicit SRW)]>;
725 def CMP16ri1: Pseudo<(outs), (ins GR16:$src1),
726 "cmp.w\t{$src1, #1}",
727 [(MSP430cmp GR16:$src1, 1), (implicit SRW)]>;
728 def CMP8ri2 : Pseudo<(outs), (ins GR8:$src1),
729 "cmp.b\t{$src1, #2}",
730 [(MSP430cmp GR8:$src1, 2), (implicit SRW)]>;
731 def CMP16ri2: Pseudo<(outs), (ins GR16:$src1),
732 "cmp.w\t{$src1, #2}",
733 [(MSP430cmp GR16:$src1, 2), (implicit SRW)]>;
734 def CMP8ri4 : Pseudo<(outs), (ins GR8:$src1),
735 "cmp.b\t{$src1, #4}",
736 [(MSP430cmp GR8:$src1, 4), (implicit SRW)]>;
737 def CMP16ri4: Pseudo<(outs), (ins GR16:$src1),
738 "cmp.w\t{$src1, #4}",
739 [(MSP430cmp GR16:$src1, 4), (implicit SRW)]>;
740 def CMP8ri8 : Pseudo<(outs), (ins GR8:$src1),
741 "cmp.b\t{$src1, #8}",
742 [(MSP430cmp GR8:$src1, 8), (implicit SRW)]>;
743 def CMP16ri8: Pseudo<(outs), (ins GR16:$src1),
744 "cmp.w\t{$src1, #8}",
745 [(MSP430cmp GR16:$src1, 8), (implicit SRW)]>;
747 def CMP8rm : Pseudo<(outs), (ins GR8:$src1, memsrc:$src2),
748 "cmp.b\t{$src1, $src2}",
749 [(MSP430cmp GR8:$src1, (load addr:$src2)), (implicit SRW)]>;
750 def CMP16rm : Pseudo<(outs), (ins GR16:$src1, memsrc:$src2),
751 "cmp.w\t{$src1, $src2}",
752 [(MSP430cmp GR16:$src1, (load addr:$src2)), (implicit SRW)]>;
754 def CMP8mr : Pseudo<(outs), (ins memsrc:$src1, GR8:$src2),
755 "cmp.b\t{$src1, $src2}",
756 [(MSP430cmp (load addr:$src1), GR8:$src2), (implicit SRW)]>;
757 def CMP16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2),
758 "cmp.w\t{$src1, $src2}",
759 [(MSP430cmp (load addr:$src1), GR16:$src2), (implicit SRW)]>;
761 def CMP8mi0 : Pseudo<(outs), (ins memsrc:$src1),
762 "cmp.b\t{$src1, #0}",
763 [(MSP430cmp (load addr:$src1), (i8 0)), (implicit SRW)]>;
764 def CMP16mi0: Pseudo<(outs), (ins memsrc:$src1),
765 "cmp.w\t{$src1, #0}",
766 [(MSP430cmp (load addr:$src1), (i16 0)), (implicit SRW)]>;
767 def CMP8mi1 : Pseudo<(outs), (ins memsrc:$src1),
768 "cmp.b\t{$src1, #1}",
769 [(MSP430cmp (load addr:$src1), (i8 1)), (implicit SRW)]>;
770 def CMP16mi1: Pseudo<(outs), (ins memsrc:$src1),
771 "cmp.w\t{$src1, #1}",
772 [(MSP430cmp (load addr:$src1), (i16 1)), (implicit SRW)]>;
773 def CMP8mi2 : Pseudo<(outs), (ins memsrc:$src1),
774 "cmp.b\t{$src1, #2}",
775 [(MSP430cmp (load addr:$src1), (i8 2)), (implicit SRW)]>;
776 def CMP16mi2: Pseudo<(outs), (ins memsrc:$src1),
777 "cmp.w\t{$src1, #2}",
778 [(MSP430cmp (load addr:$src1), (i16 2)), (implicit SRW)]>;
779 def CMP8mi4 : Pseudo<(outs), (ins memsrc:$src1),
780 "cmp.b\t{$src1, #4}",
781 [(MSP430cmp (load addr:$src1), (i8 4)), (implicit SRW)]>;
782 def CMP16mi4: Pseudo<(outs), (ins memsrc:$src1),
783 "cmp.w\t{$src1, #4}",
784 [(MSP430cmp (load addr:$src1), (i16 4)), (implicit SRW)]>;
785 def CMP8mi8 : Pseudo<(outs), (ins memsrc:$src1),
786 "cmp.b\t{$src1, #8}",
787 [(MSP430cmp (load addr:$src1), (i8 8)), (implicit SRW)]>;
788 def CMP16mi8: Pseudo<(outs), (ins memsrc:$src1),
789 "cmp.w\t{$src1, #8}",
790 [(MSP430cmp (load addr:$src1), (i16 8)), (implicit SRW)]>;
794 //===----------------------------------------------------------------------===//
795 // Non-Instruction Patterns
798 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
801 def : Pat<(anyext addr:$src), (MOVZX16rr8 GR8:$src)>;
804 def : Pat<(i8 (trunc GR16:$src)),
805 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
807 // GlobalAddress, ExternalSymbol
808 def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>;
809 def : Pat<(i16 (MSP430Wrapper texternalsym:$dst)), (MOV16ri texternalsym:$dst)>;
811 def : Pat<(add GR16:$src1, (MSP430Wrapper tglobaladdr :$src2)),
812 (ADD16ri GR16:$src1, tglobaladdr:$src2)>;
813 def : Pat<(add GR16:$src1, (MSP430Wrapper texternalsym:$src2)),
814 (ADD16ri GR16:$src1, texternalsym:$src2)>;
816 def : Pat<(store (i16 (MSP430Wrapper tglobaladdr:$src)), addr:$dst),
817 (MOV16mi addr:$dst, tglobaladdr:$src)>;
818 def : Pat<(store (i16 (MSP430Wrapper texternalsym:$src)), addr:$dst),
819 (MOV16mi addr:$dst, texternalsym:$src)>;
822 def : Pat<(MSP430call (i16 tglobaladdr:$dst)),
823 (CALLi tglobaladdr:$dst)>;
824 def : Pat<(MSP430call (i16 texternalsym:$dst)),
825 (CALLi texternalsym:$dst)>;
827 // add and sub always produce carry
828 def : Pat<(addc GR16:$src1, GR16:$src2),
829 (ADD16rr GR16:$src1, GR16:$src2)>;
830 def : Pat<(addc GR16:$src1, (load addr:$src2)),
831 (ADD16rm GR16:$src1, addr:$src2)>;
832 def : Pat<(addc GR16:$src1, imm:$src2),
833 (ADD16ri GR16:$src1, imm:$src2)>;
834 def : Pat<(store (addc (load addr:$dst), GR16:$src), addr:$dst),
835 (ADD16mr addr:$dst, GR16:$src)>;
836 def : Pat<(store (addc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
837 (ADD16mm addr:$dst, addr:$src)>;
839 def : Pat<(addc GR8:$src1, GR8:$src2),
840 (ADD8rr GR8:$src1, GR8:$src2)>;
841 def : Pat<(addc GR8:$src1, (load addr:$src2)),
842 (ADD8rm GR8:$src1, addr:$src2)>;
843 def : Pat<(addc GR8:$src1, imm:$src2),
844 (ADD8ri GR8:$src1, imm:$src2)>;
845 def : Pat<(store (addc (load addr:$dst), GR8:$src), addr:$dst),
846 (ADD8mr addr:$dst, GR8:$src)>;
847 def : Pat<(store (addc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
848 (ADD8mm addr:$dst, addr:$src)>;
850 def : Pat<(subc GR16:$src1, GR16:$src2),
851 (SUB16rr GR16:$src1, GR16:$src2)>;
852 def : Pat<(subc GR16:$src1, (load addr:$src2)),
853 (SUB16rm GR16:$src1, addr:$src2)>;
854 def : Pat<(subc GR16:$src1, imm:$src2),
855 (SUB16ri GR16:$src1, imm:$src2)>;
856 def : Pat<(store (subc (load addr:$dst), GR16:$src), addr:$dst),
857 (SUB16mr addr:$dst, GR16:$src)>;
858 def : Pat<(store (subc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
859 (SUB16mm addr:$dst, addr:$src)>;
861 def : Pat<(subc GR8:$src1, GR8:$src2),
862 (SUB8rr GR8:$src1, GR8:$src2)>;
863 def : Pat<(subc GR8:$src1, (load addr:$src2)),
864 (SUB8rm GR8:$src1, addr:$src2)>;
865 def : Pat<(subc GR8:$src1, imm:$src2),
866 (SUB8ri GR8:$src1, imm:$src2)>;
867 def : Pat<(store (subc (load addr:$dst), GR8:$src), addr:$dst),
868 (SUB8mr addr:$dst, GR8:$src)>;
869 def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
870 (SUB8mm addr:$dst, addr:$src)>;