1 //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the MSP430 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "MSP430InstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
25 def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
27 def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
28 def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
29 def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
30 def SDT_MSP430BrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>,
32 def SDT_MSP430SelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
35 //===----------------------------------------------------------------------===//
36 // MSP430 Specific Node Definitions.
37 //===----------------------------------------------------------------------===//
38 def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
39 [SDNPHasChain, SDNPOptInFlag]>;
41 def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
42 def MSP430rla : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>;
43 def MSP430rrc : SDNode<"MSP430ISD::RRC", SDTIntUnaryOp, []>;
45 def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
46 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
47 def MSP430callseq_start :
48 SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart,
49 [SDNPHasChain, SDNPOutFlag]>;
50 def MSP430callseq_end :
51 SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd,
52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
53 def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>;
54 def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp, [SDNPOutFlag]>;
55 def MSP430brcc : SDNode<"MSP430ISD::BR_CC", SDT_MSP430BrCC, [SDNPHasChain, SDNPInFlag]>;
56 def MSP430selectcc: SDNode<"MSP430ISD::SELECT_CC", SDT_MSP430SelectCC, [SDNPInFlag]>;
58 //===----------------------------------------------------------------------===//
59 // MSP430 Operand Definitions.
60 //===----------------------------------------------------------------------===//
63 def memsrc : Operand<i16> {
64 let PrintMethod = "printSrcMemOperand";
65 let MIOperandInfo = (ops GR16, i16imm);
68 def memdst : Operand<i16> {
69 let PrintMethod = "printSrcMemOperand";
70 let MIOperandInfo = (ops GR16, i16imm);
73 // Branch targets have OtherVT type.
74 def brtarget : Operand<OtherVT> {
75 let PrintMethod = "printPCRelImmOperand";
78 // Operand for printing out a condition code.
79 def cc : Operand<i8> {
80 let PrintMethod = "printCCOperand";
83 //===----------------------------------------------------------------------===//
84 // MSP430 Complex Pattern Definitions.
85 //===----------------------------------------------------------------------===//
87 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
89 //===----------------------------------------------------------------------===//
91 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
92 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
94 //===----------------------------------------------------------------------===//
97 // ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
98 // a stack adjustment and the codegen must know that they may modify the stack
99 // pointer before prolog-epilog rewriting occurs.
100 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
101 // sub / add which can clobber SRW.
102 let Defs = [SPW, SRW], Uses = [SPW] in {
103 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
105 [(MSP430callseq_start timm:$amt)]>;
106 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
108 [(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
111 let usesCustomInserter = 1 in {
112 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cc),
115 (MSP430selectcc GR8:$src1, GR8:$src2, imm:$cc))]>;
116 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cc),
119 (MSP430selectcc GR16:$src1, GR16:$src2, imm:$cc))]>;
122 let neverHasSideEffects = 1 in
123 def NOP : Pseudo<(outs), (ins), "nop", []>;
125 //===----------------------------------------------------------------------===//
126 // Control Flow Instructions...
129 // FIXME: Provide proper encoding!
130 let isReturn = 1, isTerminator = 1 in {
131 def RET : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
134 let isBranch = 1, isTerminator = 1 in {
138 def JMP : Pseudo<(outs), (ins brtarget:$dst),
142 // Conditional branches
144 def JCC : Pseudo<(outs), (ins brtarget:$dst, cc:$cc),
146 [(MSP430brcc bb:$dst, imm:$cc)]>;
147 } // isBranch, isTerminator
149 //===----------------------------------------------------------------------===//
150 // Call Instructions...
153 // All calls clobber the non-callee saved registers. SPW is marked as
154 // a use to prevent stack-pointer assignments that appear immediately
155 // before calls from potentially appearing dead. Uses for argument
156 // registers are added manually.
157 let Defs = [R12W, R13W, R14W, R15W, SRW],
159 def CALLi : Pseudo<(outs), (ins i16imm:$dst, variable_ops),
160 "call\t$dst", [(MSP430call imm:$dst)]>;
161 def CALLr : Pseudo<(outs), (ins GR16:$dst, variable_ops),
162 "call\t$dst", [(MSP430call GR16:$dst)]>;
163 def CALLm : Pseudo<(outs), (ins memsrc:$dst, variable_ops),
164 "call\t${dst:mem}", [(MSP430call (load addr:$dst))]>;
168 //===----------------------------------------------------------------------===//
169 // Miscellaneous Instructions...
171 let Defs = [SPW], Uses = [SPW], neverHasSideEffects=1 in {
173 def POP16r : Pseudo<(outs GR16:$reg), (ins), "pop.w\t$reg", []>;
176 def PUSH16r : Pseudo<(outs), (ins GR16:$reg), "push.w\t$reg",[]>;
179 //===----------------------------------------------------------------------===//
182 // FIXME: Provide proper encoding!
183 let neverHasSideEffects = 1 in {
184 def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
185 "mov.b\t{$src, $dst}",
187 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
188 "mov.w\t{$src, $dst}",
192 // FIXME: Provide proper encoding!
193 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
194 def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
195 "mov.b\t{$src, $dst}",
196 [(set GR8:$dst, imm:$src)]>;
197 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
198 "mov.w\t{$src, $dst}",
199 [(set GR16:$dst, imm:$src)]>;
202 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
203 def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
204 "mov.b\t{$src, $dst}",
205 [(set GR8:$dst, (load addr:$src))]>;
206 def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
207 "mov.w\t{$src, $dst}",
208 [(set GR16:$dst, (load addr:$src))]>;
211 def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
212 "mov.b\t{$src, $dst}",
213 [(set GR16:$dst, (zext GR8:$src))]>;
214 def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
215 "mov.b\t{$src, $dst}",
216 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
218 let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$base = $base_wb" in {
219 def MOV8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR16:$base),
220 "mov.b\t{@$base+, $dst}", []>;
221 def MOV16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$base),
222 "mov.w\t{@$base+, $dst}", []>;
225 // Any instruction that defines a 8-bit result leaves the high half of the
226 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
227 // be copying from a truncate, but any other 8-bit operation will zero-extend
229 def def8 : PatLeaf<(i8 GR8:$src), [{
230 return N->getOpcode() != ISD::TRUNCATE &&
231 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
232 N->getOpcode() != ISD::CopyFromReg;
235 // In the case of a 8-bit def that is known to implicitly zero-extend,
236 // we can use a SUBREG_TO_REG.
237 def : Pat<(i16 (zext def8:$src)),
238 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;
241 def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
242 "mov.b\t{$src, $dst}",
243 [(store (i8 imm:$src), addr:$dst)]>;
244 def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
245 "mov.w\t{$src, $dst}",
246 [(store (i16 imm:$src), addr:$dst)]>;
248 def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
249 "mov.b\t{$src, $dst}",
250 [(store GR8:$src, addr:$dst)]>;
251 def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
252 "mov.w\t{$src, $dst}",
253 [(store GR16:$src, addr:$dst)]>;
255 def MOV8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
256 "mov.b\t{$src, $dst}",
257 [(store (i8 (load addr:$src)), addr:$dst)]>;
258 def MOV16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
259 "mov.w\t{$src, $dst}",
260 [(store (i16 (load addr:$src)), addr:$dst)]>;
262 //===----------------------------------------------------------------------===//
263 // Arithmetic Instructions
265 let isTwoAddress = 1 in {
267 let Defs = [SRW] in {
269 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
270 // FIXME: Provide proper encoding!
271 def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
272 "add.b\t{$src2, $dst}",
273 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
275 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
276 "add.w\t{$src2, $dst}",
277 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
281 def ADD8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
282 "add.b\t{$src2, $dst}",
283 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
285 def ADD16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
286 "add.w\t{$src2, $dst}",
287 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
290 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
291 Constraints = "$base = $base_wb, $src1 = $dst" in {
292 def ADD8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
293 "add.b\t{@$base+, $dst}", []>;
294 def ADD16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
295 "add.w\t{@$base+, $dst}", []>;
299 def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
300 "add.b\t{$src2, $dst}",
301 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
303 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
304 "add.w\t{$src2, $dst}",
305 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
308 let isTwoAddress = 0 in {
309 def ADD8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
310 "add.b\t{$src, $dst}",
311 [(store (add (load addr:$dst), GR8:$src), addr:$dst),
313 def ADD16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
314 "add.w\t{$src, $dst}",
315 [(store (add (load addr:$dst), GR16:$src), addr:$dst),
318 def ADD8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
319 "add.b\t{$src, $dst}",
320 [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
322 def ADD16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
323 "add.w\t{$src, $dst}",
324 [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
327 def ADD8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
328 "add.b\t{$src, $dst}",
329 [(store (add (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
331 def ADD16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
332 "add.w\t{$src, $dst}",
333 [(store (add (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
337 let Uses = [SRW] in {
339 let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
340 def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
341 "addc.b\t{$src2, $dst}",
342 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
344 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
345 "addc.w\t{$src2, $dst}",
346 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
350 def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
351 "addc.b\t{$src2, $dst}",
352 [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
354 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
355 "addc.w\t{$src2, $dst}",
356 [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
359 def ADC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
360 "addc.b\t{$src2, $dst}",
361 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2))),
363 def ADC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
364 "addc.w\t{$src2, $dst}",
365 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2))),
368 let isTwoAddress = 0 in {
369 def ADC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
370 "addc.b\t{$src, $dst}",
371 [(store (adde (load addr:$dst), GR8:$src), addr:$dst),
373 def ADC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
374 "addc.w\t{$src, $dst}",
375 [(store (adde (load addr:$dst), GR16:$src), addr:$dst),
378 def ADC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
379 "addc.b\t{$src, $dst}",
380 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
382 def ADC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
383 "addc.w\t{$src, $dst}",
384 [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
387 def ADC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
388 "addc.b\t{$src, $dst}",
389 [(store (adde (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
391 def ADC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
392 "addc.w\t{$src, $dst}",
393 [(store (adde (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
399 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
400 def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
401 "and.b\t{$src2, $dst}",
402 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
404 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
405 "and.w\t{$src2, $dst}",
406 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
410 def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
411 "and.b\t{$src2, $dst}",
412 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
414 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
415 "and.w\t{$src2, $dst}",
416 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
419 def AND8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
420 "and.b\t{$src2, $dst}",
421 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
423 def AND16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
424 "and.w\t{$src2, $dst}",
425 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
428 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
429 Constraints = "$base = $base_wb, $src1 = $dst" in {
430 def AND8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
431 "and.b\t{@$base+, $dst}", []>;
432 def AND16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
433 "and.w\t{@$base+, $dst}", []>;
436 let isTwoAddress = 0 in {
437 def AND8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
438 "and.b\t{$src, $dst}",
439 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
441 def AND16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
442 "and.w\t{$src, $dst}",
443 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
446 def AND8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
447 "and.b\t{$src, $dst}",
448 [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
450 def AND16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
451 "and.w\t{$src, $dst}",
452 [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
455 def AND8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
456 "and.b\t{$src, $dst}",
457 [(store (and (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
459 def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
460 "and.w\t{$src, $dst}",
461 [(store (and (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
466 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
467 def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
468 "xor.b\t{$src2, $dst}",
469 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
471 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
472 "xor.w\t{$src2, $dst}",
473 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
477 def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
478 "xor.b\t{$src2, $dst}",
479 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
481 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
482 "xor.w\t{$src2, $dst}",
483 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
486 def XOR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
487 "xor.b\t{$src2, $dst}",
488 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
490 def XOR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
491 "xor.w\t{$src2, $dst}",
492 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
495 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
496 Constraints = "$base = $base_wb, $src1 = $dst" in {
497 def XOR8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
498 "xor.b\t{@$base+, $dst}", []>;
499 def XOR16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
500 "xor.w\t{@$base+, $dst}", []>;
503 let isTwoAddress = 0 in {
504 def XOR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
505 "xor.b\t{$src, $dst}",
506 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
508 def XOR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
509 "xor.w\t{$src, $dst}",
510 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
513 def XOR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
514 "xor.b\t{$src, $dst}",
515 [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
517 def XOR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
518 "xor.w\t{$src, $dst}",
519 [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
522 def XOR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
523 "xor.b\t{$src, $dst}",
524 [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
526 def XOR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
527 "xor.w\t{$src, $dst}",
528 [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
533 def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
534 "sub.b\t{$src2, $dst}",
535 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
537 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
538 "sub.w\t{$src2, $dst}",
539 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
542 def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
543 "sub.b\t{$src2, $dst}",
544 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
546 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
547 "sub.w\t{$src2, $dst}",
548 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
551 def SUB8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
552 "sub.b\t{$src2, $dst}",
553 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
555 def SUB16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
556 "sub.w\t{$src2, $dst}",
557 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
560 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
561 Constraints = "$base = $base_wb, $src1 = $dst" in {
562 def SUB8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
563 "sub.b\t{@$base+, $dst}", []>;
564 def SUB16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
565 "sub.w\t{@$base+, $dst}", []>;
568 let isTwoAddress = 0 in {
569 def SUB8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
570 "sub.b\t{$src, $dst}",
571 [(store (sub (load addr:$dst), GR8:$src), addr:$dst),
573 def SUB16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
574 "sub.w\t{$src, $dst}",
575 [(store (sub (load addr:$dst), GR16:$src), addr:$dst),
578 def SUB8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
579 "sub.b\t{$src, $dst}",
580 [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
582 def SUB16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
583 "sub.w\t{$src, $dst}",
584 [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
587 def SUB8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
588 "sub.b\t{$src, $dst}",
589 [(store (sub (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
591 def SUB16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
592 "sub.w\t{$src, $dst}",
593 [(store (sub (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
597 let Uses = [SRW] in {
598 def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
599 "subc.b\t{$src2, $dst}",
600 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
602 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
603 "subc.w\t{$src2, $dst}",
604 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
607 def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
608 "subc.b\t{$src2, $dst}",
609 [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
611 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
612 "subc.w\t{$src2, $dst}",
613 [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
616 def SBC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
617 "subc.b\t{$src2, $dst}",
618 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2))),
620 def SBC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
621 "subc.w\t{$src2, $dst}",
622 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2))),
625 let isTwoAddress = 0 in {
626 def SBC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
627 "subc.b\t{$src, $dst}",
628 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
630 def SBC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
631 "subc.w\t{$src, $dst}",
632 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
635 def SBC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
636 "subc.b\t{$src, $dst}",
637 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
639 def SBC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
640 "subc.w\t{$src, $dst}",
641 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
644 def SBC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
645 "subc.b\t{$src, $dst}",
646 [(store (sube (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
648 def SBC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
649 "subc.w\t{$src, $dst}",
650 [(store (sube (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
656 // FIXME: Provide proper encoding!
657 def SAR8r1 : Pseudo<(outs GR8:$dst), (ins GR8:$src),
659 [(set GR8:$dst, (MSP430rra GR8:$src)),
661 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
663 [(set GR16:$dst, (MSP430rra GR16:$src)),
666 def SHL8r1 : Pseudo<(outs GR8:$dst), (ins GR8:$src),
668 [(set GR8:$dst, (MSP430rla GR8:$src)),
670 def SHL16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
672 [(set GR16:$dst, (MSP430rla GR16:$src)),
675 def SAR8r1c : Pseudo<(outs GR8:$dst), (ins GR8:$src),
678 [(set GR8:$dst, (MSP430rrc GR8:$src)),
680 def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src),
683 [(set GR16:$dst, (MSP430rrc GR16:$src)),
686 def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
688 [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
693 def SWPB16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
695 [(set GR16:$dst, (bswap GR16:$src))]>;
697 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
698 def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
699 "bis.b\t{$src2, $dst}",
700 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
701 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
702 "bis.w\t{$src2, $dst}",
703 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
706 def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
707 "bis.b\t{$src2, $dst}",
708 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
709 def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
710 "bis.w\t{$src2, $dst}",
711 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
713 def OR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
714 "bis.b\t{$src2, $dst}",
715 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
716 def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
717 "bis.w\t{$src2, $dst}",
718 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
720 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
721 Constraints = "$base = $base_wb, $src1 = $dst" in {
722 def OR8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
723 "bis.b\t{@$base+, $dst}", []>;
724 def OR16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
725 "bis.w\t{@$base+, $dst}", []>;
728 let isTwoAddress = 0 in {
729 def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
730 "bis.b\t{$src, $dst}",
731 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
732 def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
733 "bis.w\t{$src, $dst}",
734 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>;
736 def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
737 "bis.b\t{$src, $dst}",
738 [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst)]>;
739 def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
740 "bis.w\t{$src, $dst}",
741 [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst)]>;
743 def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
744 "bis.b\t{$src, $dst}",
745 [(store (or (i8 (load addr:$dst)),
746 (i8 (load addr:$src))), addr:$dst)]>;
747 def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
748 "bis.w\t{$src, $dst}",
749 [(store (or (i16 (load addr:$dst)),
750 (i16 (load addr:$src))), addr:$dst)]>;
753 } // isTwoAddress = 1
755 // Integer comparisons
756 let Defs = [SRW] in {
757 def CMP8rr : Pseudo<(outs), (ins GR8:$src1, GR8:$src2),
758 "cmp.b\t{$src1, $src2}",
759 [(MSP430cmp GR8:$src1, GR8:$src2), (implicit SRW)]>;
760 def CMP16rr : Pseudo<(outs), (ins GR16:$src1, GR16:$src2),
761 "cmp.w\t{$src1, $src2}",
762 [(MSP430cmp GR16:$src1, GR16:$src2), (implicit SRW)]>;
764 def CMP8ir : Pseudo<(outs), (ins i8imm:$src1, GR8:$src2),
765 "cmp.b\t{$src1, $src2}",
766 [(MSP430cmp imm:$src1, GR8:$src2), (implicit SRW)]>;
767 def CMP16ir : Pseudo<(outs), (ins i16imm:$src1, GR16:$src2),
768 "cmp.w\t{$src1, $src2}",
769 [(MSP430cmp imm:$src1, GR16:$src2), (implicit SRW)]>;
771 def CMP8im : Pseudo<(outs), (ins i8imm:$src1, memsrc:$src2),
772 "cmp.b\t{$src1, $src2}",
773 [(MSP430cmp (i8 imm:$src1), (load addr:$src2)), (implicit SRW)]>;
774 def CMP16im : Pseudo<(outs), (ins i16imm:$src1, memsrc:$src2),
775 "cmp.w\t{$src1, $src2}",
776 [(MSP430cmp (i16 imm:$src1), (load addr:$src2)), (implicit SRW)]>;
778 def CMP8rm : Pseudo<(outs), (ins GR8:$src1, memsrc:$src2),
779 "cmp.b\t{$src1, $src2}",
780 [(MSP430cmp GR8:$src1, (load addr:$src2)), (implicit SRW)]>;
781 def CMP16rm : Pseudo<(outs), (ins GR16:$src1, memsrc:$src2),
782 "cmp.w\t{$src1, $src2}",
783 [(MSP430cmp GR16:$src1, (load addr:$src2)), (implicit SRW)]>;
785 def CMP8mr : Pseudo<(outs), (ins memsrc:$src1, GR8:$src2),
786 "cmp.b\t{$src1, $src2}",
787 [(MSP430cmp (load addr:$src1), GR8:$src2), (implicit SRW)]>;
788 def CMP16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2),
789 "cmp.w\t{$src1, $src2}",
790 [(MSP430cmp (load addr:$src1), GR16:$src2), (implicit SRW)]>;
792 def CMP8mi0 : Pseudo<(outs), (ins memsrc:$src1),
793 "cmp.b\t{$src1, #0}",
794 [(MSP430cmp (load addr:$src1), (i8 0)), (implicit SRW)]>;
795 def CMP16mi0: Pseudo<(outs), (ins memsrc:$src1),
796 "cmp.w\t{$src1, #0}",
797 [(MSP430cmp (load addr:$src1), (i16 0)), (implicit SRW)]>;
798 def CMP8mi1 : Pseudo<(outs), (ins memsrc:$src1),
799 "cmp.b\t{$src1, #1}",
800 [(MSP430cmp (load addr:$src1), (i8 1)), (implicit SRW)]>;
801 def CMP16mi1: Pseudo<(outs), (ins memsrc:$src1),
802 "cmp.w\t{$src1, #1}",
803 [(MSP430cmp (load addr:$src1), (i16 1)), (implicit SRW)]>;
804 def CMP8mi2 : Pseudo<(outs), (ins memsrc:$src1),
805 "cmp.b\t{$src1, #2}",
806 [(MSP430cmp (load addr:$src1), (i8 2)), (implicit SRW)]>;
807 def CMP16mi2: Pseudo<(outs), (ins memsrc:$src1),
808 "cmp.w\t{$src1, #2}",
809 [(MSP430cmp (load addr:$src1), (i16 2)), (implicit SRW)]>;
810 def CMP8mi4 : Pseudo<(outs), (ins memsrc:$src1),
811 "cmp.b\t{$src1, #4}",
812 [(MSP430cmp (load addr:$src1), (i8 4)), (implicit SRW)]>;
813 def CMP16mi4: Pseudo<(outs), (ins memsrc:$src1),
814 "cmp.w\t{$src1, #4}",
815 [(MSP430cmp (load addr:$src1), (i16 4)), (implicit SRW)]>;
816 def CMP8mi8 : Pseudo<(outs), (ins memsrc:$src1),
817 "cmp.b\t{$src1, #8}",
818 [(MSP430cmp (load addr:$src1), (i8 8)), (implicit SRW)]>;
819 def CMP16mi8: Pseudo<(outs), (ins memsrc:$src1),
820 "cmp.w\t{$src1, #8}",
821 [(MSP430cmp (load addr:$src1), (i16 8)), (implicit SRW)]>;
825 //===----------------------------------------------------------------------===//
826 // Non-Instruction Patterns
829 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
832 def : Pat<(anyext addr:$src), (MOVZX16rr8 GR8:$src)>;
835 def : Pat<(i8 (trunc GR16:$src)),
836 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
838 // GlobalAddress, ExternalSymbol
839 def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>;
840 def : Pat<(i16 (MSP430Wrapper texternalsym:$dst)), (MOV16ri texternalsym:$dst)>;
842 def : Pat<(add GR16:$src1, (MSP430Wrapper tglobaladdr :$src2)),
843 (ADD16ri GR16:$src1, tglobaladdr:$src2)>;
844 def : Pat<(add GR16:$src1, (MSP430Wrapper texternalsym:$src2)),
845 (ADD16ri GR16:$src1, texternalsym:$src2)>;
847 def : Pat<(store (i16 (MSP430Wrapper tglobaladdr:$src)), addr:$dst),
848 (MOV16mi addr:$dst, tglobaladdr:$src)>;
849 def : Pat<(store (i16 (MSP430Wrapper texternalsym:$src)), addr:$dst),
850 (MOV16mi addr:$dst, texternalsym:$src)>;
853 def : Pat<(MSP430call (i16 tglobaladdr:$dst)),
854 (CALLi tglobaladdr:$dst)>;
855 def : Pat<(MSP430call (i16 texternalsym:$dst)),
856 (CALLi texternalsym:$dst)>;
858 // add and sub always produce carry
859 def : Pat<(addc GR16:$src1, GR16:$src2),
860 (ADD16rr GR16:$src1, GR16:$src2)>;
861 def : Pat<(addc GR16:$src1, (load addr:$src2)),
862 (ADD16rm GR16:$src1, addr:$src2)>;
863 def : Pat<(addc GR16:$src1, imm:$src2),
864 (ADD16ri GR16:$src1, imm:$src2)>;
865 def : Pat<(store (addc (load addr:$dst), GR16:$src), addr:$dst),
866 (ADD16mr addr:$dst, GR16:$src)>;
867 def : Pat<(store (addc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
868 (ADD16mm addr:$dst, addr:$src)>;
870 def : Pat<(addc GR8:$src1, GR8:$src2),
871 (ADD8rr GR8:$src1, GR8:$src2)>;
872 def : Pat<(addc GR8:$src1, (load addr:$src2)),
873 (ADD8rm GR8:$src1, addr:$src2)>;
874 def : Pat<(addc GR8:$src1, imm:$src2),
875 (ADD8ri GR8:$src1, imm:$src2)>;
876 def : Pat<(store (addc (load addr:$dst), GR8:$src), addr:$dst),
877 (ADD8mr addr:$dst, GR8:$src)>;
878 def : Pat<(store (addc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
879 (ADD8mm addr:$dst, addr:$src)>;
881 def : Pat<(subc GR16:$src1, GR16:$src2),
882 (SUB16rr GR16:$src1, GR16:$src2)>;
883 def : Pat<(subc GR16:$src1, (load addr:$src2)),
884 (SUB16rm GR16:$src1, addr:$src2)>;
885 def : Pat<(subc GR16:$src1, imm:$src2),
886 (SUB16ri GR16:$src1, imm:$src2)>;
887 def : Pat<(store (subc (load addr:$dst), GR16:$src), addr:$dst),
888 (SUB16mr addr:$dst, GR16:$src)>;
889 def : Pat<(store (subc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
890 (SUB16mm addr:$dst, addr:$src)>;
892 def : Pat<(subc GR8:$src1, GR8:$src2),
893 (SUB8rr GR8:$src1, GR8:$src2)>;
894 def : Pat<(subc GR8:$src1, (load addr:$src2)),
895 (SUB8rm GR8:$src1, addr:$src2)>;
896 def : Pat<(subc GR8:$src1, imm:$src2),
897 (SUB8ri GR8:$src1, imm:$src2)>;
898 def : Pat<(store (subc (load addr:$dst), GR8:$src), addr:$dst),
899 (SUB8mr addr:$dst, GR8:$src)>;
900 def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
901 (SUB8mm addr:$dst, addr:$src)>;