1 //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the MSP430 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "MSP430InstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
25 def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
27 def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
28 def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
29 def SDT_MSP430SetCC : SDTypeProfile<1, 2, [SDTCisVT<0, i8>,
30 SDTCisVT<1, i8>, SDTCisVT<2, i16>]>;
31 def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
32 def SDT_MSP430BrCond : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>,
33 SDTCisVT<1, i8>, SDTCisVT<2, i16>]>;
35 //===----------------------------------------------------------------------===//
36 // MSP430 Specific Node Definitions.
37 //===----------------------------------------------------------------------===//
38 def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
39 [SDNPHasChain, SDNPOptInFlag]>;
41 def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
43 def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
44 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
45 def MSP430callseq_start :
46 SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart,
47 [SDNPHasChain, SDNPOutFlag]>;
48 def MSP430callseq_end :
49 SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd,
50 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
51 def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>;
52 def MSP430setcc : SDNode<"MSP430ISD::SETCC", SDT_MSP430SetCC>;
53 def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp>;
54 def MSP430brcond : SDNode<"MSP430ISD::BRCOND", SDT_MSP430BrCond, [SDNPHasChain]>;
56 //===----------------------------------------------------------------------===//
57 // MSP430 Operand Definitions.
58 //===----------------------------------------------------------------------===//
61 def memsrc : Operand<i16> {
62 let PrintMethod = "printSrcMemOperand";
63 let MIOperandInfo = (ops GR16, i16imm);
66 def memdst : Operand<i16> {
67 let PrintMethod = "printSrcMemOperand";
68 let MIOperandInfo = (ops GR16, i16imm);
71 // Branch targets have OtherVT type.
72 def brtarget : Operand<OtherVT>;
74 //===----------------------------------------------------------------------===//
75 // MSP430 Complex Pattern Definitions.
76 //===----------------------------------------------------------------------===//
78 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
80 //===----------------------------------------------------------------------===//
82 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
83 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
85 // MSP430 specific condition code. These correspond to CondCode in
86 // MSP430InstrInfo.h. They must be kept in synch.
87 def MSP430_COND_E : PatLeaf<(i8 0)>; // aka COND_Z
88 def MSP430_COND_NE : PatLeaf<(i8 1)>; // aka COND_NZ
89 def MSP430_COND_HS : PatLeaf<(i8 2)>; // aka COND_C
90 def MSP430_COND_LO : PatLeaf<(i8 3)>; // aka COND_NC
91 def MSP430_COND_GE : PatLeaf<(i8 4)>;
92 def MSP430_COND_L : PatLeaf<(i8 5)>;
94 //===----------------------------------------------------------------------===//
97 // ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
98 // a stack adjustment and the codegen must know that they may modify the stack
99 // pointer before prolog-epilog rewriting occurs.
100 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
101 // sub / add which can clobber SRW.
102 let Defs = [SPW, SRW], Uses = [SPW] in {
103 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
105 [(MSP430callseq_start timm:$amt)]>;
106 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
108 [(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
112 let neverHasSideEffects = 1 in
113 def NOP : Pseudo<(outs), (ins), "nop", []>;
115 //===----------------------------------------------------------------------===//
116 // Control Flow Instructions...
119 // FIXME: Provide proper encoding!
120 let isReturn = 1, isTerminator = 1 in {
121 def RET : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
124 // Conditional branches
125 let isBranch = 1, isTerminator = 1, Uses = [SRW] in {
126 def JE : Pseudo<(outs), (ins brtarget:$dst), "je\t$dst",
127 [(MSP430brcond bb:$dst, MSP430_COND_E, SRW)]>;
128 def JNE : Pseudo<(outs), (ins brtarget:$dst), "jne\t$dst",
129 [(MSP430brcond bb:$dst, MSP430_COND_NE, SRW)]>;
130 def JHS : Pseudo<(outs), (ins brtarget:$dst), "jhs\t$dst",
131 [(MSP430brcond bb:$dst, MSP430_COND_HS, SRW)]>;
132 def JLO : Pseudo<(outs), (ins brtarget:$dst), "jlo\t$dst",
133 [(MSP430brcond bb:$dst, MSP430_COND_LO, SRW)]>;
134 def JGE : Pseudo<(outs), (ins brtarget:$dst), "jge\t$dst",
135 [(MSP430brcond bb:$dst, MSP430_COND_GE, SRW)]>;
136 def JL : Pseudo<(outs), (ins brtarget:$dst), "jl\t$dst",
137 [(MSP430brcond bb:$dst, MSP430_COND_L, SRW)]>;
140 //===----------------------------------------------------------------------===//
141 // Call Instructions...
144 // All calls clobber the non-callee saved registers. SPW is marked as
145 // a use to prevent stack-pointer assignments that appear immediately
146 // before calls from potentially appearing dead. Uses for argument
147 // registers are added manually.
148 let Defs = [R12W, R13W, R14W, R15W, SRW],
150 def CALLi : Pseudo<(outs), (ins i16imm:$dst, variable_ops),
151 "call\t${dst:call}", [(MSP430call imm:$dst)]>;
152 def CALLr : Pseudo<(outs), (ins GR16:$dst, variable_ops),
153 "call\t$dst", [(MSP430call GR16:$dst)]>;
154 def CALLm : Pseudo<(outs), (ins memsrc:$dst, variable_ops),
155 "call\t${dst:mem}", [(MSP430call (load addr:$dst))]>;
159 //===----------------------------------------------------------------------===//
160 // Miscellaneous Instructions...
162 let Defs = [SPW], Uses = [SPW], neverHasSideEffects=1 in {
164 def POP16r : Pseudo<(outs GR16:$reg), (ins), "pop.w\t$reg", []>;
167 def PUSH16r : Pseudo<(outs), (ins GR16:$reg), "push.w\t$reg",[]>;
170 //===----------------------------------------------------------------------===//
173 // FIXME: Provide proper encoding!
174 let neverHasSideEffects = 1 in {
175 def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
176 "mov.b\t{$src, $dst|$dst, $src}",
178 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
179 "mov.w\t{$src, $dst|$dst, $src}",
183 // FIXME: Provide proper encoding!
184 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
185 def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
186 "mov.b\t{$src, $dst|$dst, $src}",
187 [(set GR8:$dst, imm:$src)]>;
188 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
189 "mov.w\t{$src, $dst|$dst, $src}",
190 [(set GR16:$dst, imm:$src)]>;
193 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
194 def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
195 "mov.b\t{$src, $dst|$dst, $src}",
196 [(set GR8:$dst, (load addr:$src))]>;
197 def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
198 "mov.w\t{$src, $dst|$dst, $src}",
199 [(set GR16:$dst, (load addr:$src))]>;
202 def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
203 "mov.b\t{$src, $dst|$dst, $src}",
204 [(set GR16:$dst, (zext GR8:$src))]>;
205 def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
206 "mov.b\t{$src, $dst|$dst, $src}",
207 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
209 def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
210 "mov.b\t{$src, $dst|$dst, $src}",
211 [(store (i8 imm:$src), addr:$dst)]>;
212 def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
213 "mov.w\t{$src, $dst|$dst, $src}",
214 [(store (i16 imm:$src), addr:$dst)]>;
216 def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
217 "mov.b\t{$src, $dst|$dst, $src}",
218 [(store GR8:$src, addr:$dst)]>;
219 def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
220 "mov.w\t{$src, $dst|$dst, $src}",
221 [(store GR16:$src, addr:$dst)]>;
223 //===----------------------------------------------------------------------===//
224 // Arithmetic Instructions
226 let isTwoAddress = 1 in {
228 let Defs = [SRW] in {
230 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
231 // FIXME: Provide proper encoding!
232 def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
233 "add.b\t{$src2, $dst|$dst, $src2}",
234 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
236 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
237 "add.w\t{$src2, $dst|$dst, $src2}",
238 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
242 def ADD8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
243 "add.b\t{$src2, $dst|$dst, $src2}",
244 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
246 def ADD16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
247 "add.w\t{$src2, $dst|$dst, $src2}",
248 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
251 def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
252 "add.b\t{$src2, $dst|$dst, $src2}",
253 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
255 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
256 "add.w\t{$src2, $dst|$dst, $src2}",
257 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
260 let isTwoAddress = 0 in {
261 def ADD8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
262 "add.b\t{$src, $dst|$dst, $src}",
263 [(store (add (load addr:$dst), GR8:$src), addr:$dst),
265 def ADD16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
266 "add.w\t{$src, $dst|$dst, $src}",
267 [(store (add (load addr:$dst), GR16:$src), addr:$dst),
270 def ADD8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
271 "add.b\t{$src, $dst|$dst, $src}",
272 [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
274 def ADD16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
275 "add.w\t{$src, $dst|$dst, $src}",
276 [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
279 def ADD8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
280 "add.b\t{$src, $dst|$dst, $src}",
281 [(store (add (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
283 def ADD16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
284 "add.w\t{$src, $dst|$dst, $src}",
285 [(store (add (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
289 let Uses = [SRW] in {
291 let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
292 def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
293 "addc.b\t{$src2, $dst|$dst, $src2}",
294 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
296 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
297 "addc.w\t{$src2, $dst|$dst, $src2}",
298 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
302 def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
303 "addc.b\t{$src2, $dst|$dst, $src2}",
304 [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
306 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
307 "addc.w\t{$src2, $dst|$dst, $src2}",
308 [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
311 def ADC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
312 "addc.b\t{$src2, $dst|$dst, $src2}",
313 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2))),
315 def ADC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
316 "addc.w\t{$src2, $dst|$dst, $src2}",
317 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2))),
320 let isTwoAddress = 0 in {
321 def ADC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
322 "addc.b\t{$src, $dst|$dst, $src}",
323 [(store (adde (load addr:$dst), GR8:$src), addr:$dst),
325 def ADC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
326 "addc.w\t{$src, $dst|$dst, $src}",
327 [(store (adde (load addr:$dst), GR16:$src), addr:$dst),
330 def ADC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
331 "addc.b\t{$src, $dst|$dst, $src}",
332 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
334 def ADC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
335 "addc.w\t{$src, $dst|$dst, $src}",
336 [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
339 def ADC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
340 "addc.b\t{$src, $dst|$dst, $src}",
341 [(store (adde (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
343 def ADC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
344 "addc.w\t{$src, $dst|$dst, $src}",
345 [(store (adde (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
351 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
352 def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
353 "and.b\t{$src2, $dst|$dst, $src2}",
354 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
356 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
357 "and.w\t{$src2, $dst|$dst, $src2}",
358 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
362 def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
363 "and.b\t{$src2, $dst|$dst, $src2}",
364 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
366 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
367 "and.w\t{$src2, $dst|$dst, $src2}",
368 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
371 def AND8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
372 "and.b\t{$src2, $dst|$dst, $src2}",
373 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
375 def AND16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
376 "and.w\t{$src2, $dst|$dst, $src2}",
377 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
380 let isTwoAddress = 0 in {
381 def AND8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
382 "and.b\t{$src, $dst|$dst, $src}",
383 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
385 def AND16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
386 "and.w\t{$src, $dst|$dst, $src}",
387 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
390 def AND8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
391 "and.b\t{$src, $dst|$dst, $src}",
392 [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
394 def AND16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
395 "and.w\t{$src, $dst|$dst, $src}",
396 [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
399 def AND8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
400 "and.b\t{$src, $dst|$dst, $src}",
401 [(store (and (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
403 def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
404 "and.w\t{$src, $dst|$dst, $src}",
405 [(store (and (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
410 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
411 def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
412 "xor.b\t{$src2, $dst|$dst, $src2}",
413 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
415 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
416 "xor.w\t{$src2, $dst|$dst, $src2}",
417 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
421 def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
422 "xor.b\t{$src2, $dst|$dst, $src2}",
423 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
425 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
426 "xor.w\t{$src2, $dst|$dst, $src2}",
427 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
430 def XOR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
431 "xor.b\t{$src2, $dst|$dst, $src2}",
432 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
434 def XOR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
435 "xor.w\t{$src2, $dst|$dst, $src2}",
436 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
439 let isTwoAddress = 0 in {
440 def XOR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
441 "xor.b\t{$src, $dst|$dst, $src}",
442 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
444 def XOR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
445 "xor.w\t{$src, $dst|$dst, $src}",
446 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
449 def XOR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
450 "xor.b\t{$src, $dst|$dst, $src}",
451 [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
453 def XOR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
454 "xor.w\t{$src, $dst|$dst, $src}",
455 [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
458 def XOR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
459 "xor.b\t{$src, $dst|$dst, $src}",
460 [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
462 def XOR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
463 "xor.w\t{$src, $dst|$dst, $src}",
464 [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
469 def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
470 "sub.b\t{$src2, $dst|$dst, $src2}",
471 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
473 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
474 "sub.w\t{$src2, $dst|$dst, $src2}",
475 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
478 def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
479 "sub.b\t{$src2, $dst|$dst, $src2}",
480 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
482 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
483 "sub.w\t{$src2, $dst|$dst, $src2}",
484 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
487 def SUB8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
488 "sub.b\t{$src2, $dst|$dst, $src2}",
489 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
491 def SUB16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
492 "sub.w\t{$src2, $dst|$dst, $src2}",
493 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
496 let isTwoAddress = 0 in {
497 def SUB8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
498 "sub.b\t{$src, $dst|$dst, $src}",
499 [(store (sub (load addr:$dst), GR8:$src), addr:$dst),
501 def SUB16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
502 "sub.w\t{$src, $dst|$dst, $src}",
503 [(store (sub (load addr:$dst), GR16:$src), addr:$dst),
506 def SUB8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
507 "sub.b\t{$src, $dst|$dst, $src}",
508 [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
510 def SUB16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
511 "sub.w\t{$src, $dst|$dst, $src}",
512 [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
515 def SUB8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
516 "sub.b\t{$src, $dst|$dst, $src}",
517 [(store (sub (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
519 def SUB16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
520 "sub.w\t{$src, $dst|$dst, $src}",
521 [(store (sub (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
525 let Uses = [SRW] in {
526 def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
527 "subc.b\t{$src2, $dst|$dst, $src2}",
528 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
530 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
531 "subc.w\t{$src2, $dst|$dst, $src2}",
532 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
535 def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
536 "subc.b\t{$src2, $dst|$dst, $src2}",
537 [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
539 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
540 "subc.w\t{$src2, $dst|$dst, $src2}",
541 [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
544 def SBC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
545 "subc.b\t{$src2, $dst|$dst, $src2}",
546 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2))),
548 def SBC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
549 "subc.w\t{$src2, $dst|$dst, $src2}",
550 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2))),
553 let isTwoAddress = 0 in {
554 def SBC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
555 "subc.b\t{$src, $dst|$dst, $src}",
556 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
558 def SBC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
559 "subc.w\t{$src, $dst|$dst, $src}",
560 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
563 def SBC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
564 "subc.b\t{$src, $dst|$dst, $src}",
565 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
567 def SBC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
568 "subc.w\t{$src, $dst|$dst, $src}",
569 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
572 def SBC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
573 "subc.b\t{$src, $dst|$dst, $src}",
574 [(store (sube (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
576 def SBC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
577 "subc.w\t{$src, $dst|$dst, $src}",
578 [(store (sube (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
584 // FIXME: Provide proper encoding!
585 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
587 [(set GR16:$dst, (MSP430rra GR16:$src)),
590 def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
592 [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
595 //def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
597 // [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
602 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
603 def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
604 "bis.b\t{$src2, $dst|$dst, $src2}",
605 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
606 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
607 "bis.w\t{$src2, $dst|$dst, $src2}",
608 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
611 def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
612 "bis.b\t{$src2, $dst|$dst, $src2}",
613 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
614 def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
615 "bis.w\t{$src2, $dst|$dst, $src2}",
616 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
618 def OR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
619 "bis.b\t{$src2, $dst|$dst, $src2}",
620 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
621 def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
622 "bis.w\t{$src2, $dst|$dst, $src2}",
623 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
625 let isTwoAddress = 0 in {
626 def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
627 "bis.b\t{$src, $dst|$dst, $src}",
628 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
630 def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
631 "bis.w\t{$src, $dst|$dst, $src}",
632 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
635 def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
636 "bis.b\t{$src, $dst|$dst, $src}",
637 [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst),
639 def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
640 "bis.w\t{$src, $dst|$dst, $src}",
641 [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst),
644 def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
645 "bis.b\t{$src, $dst|$dst, $src}",
646 [(store (or (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
648 def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
649 "bis.w\t{$src, $dst|$dst, $src}",
650 [(store (or (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
654 } // isTwoAddress = 1
656 // Integer comparisons
657 let Defs = [SRW] in {
658 def CMP8rr : Pseudo<(outs), (ins GR8:$src1, GR8:$src2),
659 "cmp.b\t{$src2, $src1|$src1, $src2}",
660 [(MSP430cmp GR8:$src1, GR8:$src2), (implicit SRW)]>;
661 def CMP16rr : Pseudo<(outs), (ins GR16:$src1, GR16:$src2),
662 "cmp.w\t{$src2, $src1|$src1, $src2}",
663 [(MSP430cmp GR16:$src1, GR16:$src2), (implicit SRW)]>;
665 def CMP8ri : Pseudo<(outs), (ins GR8:$src1, i8imm:$src2),
666 "cmp.b\t{$src2, $src1|$src1, $src2}",
667 [(MSP430cmp GR8:$src1, imm:$src2), (implicit SRW)]>;
668 def CMP16ri : Pseudo<(outs), (ins GR16:$src1, i16imm:$src2),
669 "cmp.w\t{$src2, $src1|$src1, $src2}",
670 [(MSP430cmp GR16:$src1, imm:$src2), (implicit SRW)]>;
672 def CMP8rm : Pseudo<(outs), (ins GR8:$src1, memsrc:$src2),
673 "cmp.b\t{$src2, $src1|$src1, $src2}",
674 [(MSP430cmp GR8:$src1, (load addr:$src2)), (implicit SRW)]>;
675 def CMP16rm : Pseudo<(outs), (ins GR16:$src1, memsrc:$src2),
676 "cmp.w\t{$src2, $src1|$src1, $src2}",
677 [(MSP430cmp GR16:$src1, (load addr:$src2)), (implicit SRW)]>;
679 def CMP8mr : Pseudo<(outs), (ins memsrc:$src1, GR8:$src2),
680 "cmp.b\t{$src2, $src1|$src1, $src2}",
681 [(MSP430cmp (load addr:$src1), GR8:$src2), (implicit SRW)]>;
682 def CMP16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2),
683 "cmp.w\t{$src2, $src1|$src1, $src2}",
684 [(MSP430cmp (load addr:$src1), GR16:$src2), (implicit SRW)]>;
686 def CMP8mi : Pseudo<(outs), (ins memsrc:$src1, i8imm:$src2),
687 "cmp.b\t{$src2, $src1|$src1, $src2}",
688 [(MSP430cmp (load addr:$src1), (i8 imm:$src2)), (implicit SRW)]>;
689 def CMP16mi : Pseudo<(outs), (ins memsrc:$src1, i16imm:$src2),
690 "cmp.w\t{$src2, $src1|$src1, $src2}",
691 [(MSP430cmp (load addr:$src1), (i16 imm:$src2)), (implicit SRW)]>;
693 def CMP8mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2),
694 "cmp.b\t{$src2, $src1|$src1, $src2}",
695 [(MSP430cmp (load addr:$src1), (i8 (load addr:$src2))), (implicit SRW)]>;
696 def CMP16mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2),
697 "cmp.w\t{$src2, $src1|$src1, $src2}",
698 [(MSP430cmp (load addr:$src1), (i16 (load addr:$src2))), (implicit SRW)]>;
701 //===----------------------------------------------------------------------===//
702 // Non-Instruction Patterns
705 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
708 def : Pat<(i8 (trunc GR16:$src)),
709 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
712 def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>;
714 def : Pat<(add GR16:$src1, (MSP430Wrapper tglobaladdr :$src2)),
715 (ADD16ri GR16:$src1, tglobaladdr:$src2)>;
718 def : Pat<(MSP430call (i16 tglobaladdr:$dst)),
719 (CALLi tglobaladdr:$dst)>;