1 //===- MSP430RegisterInfo.cpp - MSP430 Register Information ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MSP430 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "msp430-reg-info"
17 #include "MSP430MachineFunctionInfo.h"
18 #include "MSP430RegisterInfo.h"
19 #include "MSP430TargetMachine.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/Support/ErrorHandling.h"
31 // FIXME: Provide proper call frame setup / destroy opcodes.
32 MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
33 const TargetInstrInfo &tii)
34 : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
36 StackAlign = TM.getFrameInfo()->getStackAlignment();
40 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
41 const Function* F = MF->getFunction();
42 static const unsigned CalleeSavedRegs[] = {
43 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
44 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
47 static const unsigned CalleeSavedRegsFP[] = {
48 MSP430::R5W, MSP430::R6W, MSP430::R7W,
49 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
52 static const unsigned CalleeSavedRegsIntr[] = {
53 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
54 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
55 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
58 static const unsigned CalleeSavedRegsIntrFP[] = {
59 MSP430::R5W, MSP430::R6W, MSP430::R7W,
60 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
61 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
66 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
67 CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
69 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
70 CalleeSavedRegsIntr : CalleeSavedRegs);
74 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
75 BitVector Reserved(getNumRegs());
77 // Mark 4 special registers as reserved.
78 Reserved.set(MSP430::PCW);
79 Reserved.set(MSP430::SPW);
80 Reserved.set(MSP430::SRW);
81 Reserved.set(MSP430::CGW);
83 // Mark frame pointer as reserved if needed.
85 Reserved.set(MSP430::FPW);
90 const TargetRegisterClass *
91 MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
92 return &MSP430::GR16RegClass;
96 bool MSP430RegisterInfo::hasFP(const MachineFunction &MF) const {
97 const MachineFrameInfo *MFI = MF.getFrameInfo();
99 return (DisableFramePointerElim(MF) ||
100 MF.getFrameInfo()->hasVarSizedObjects() ||
101 MFI->isFrameAddressTaken());
104 bool MSP430RegisterInfo::hasReservedCallFrame(const MachineFunction &MF) const {
105 return !MF.getFrameInfo()->hasVarSizedObjects();
108 void MSP430RegisterInfo::
109 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator I) const {
111 if (!hasReservedCallFrame(MF)) {
112 // If the stack pointer can be changed after prologue, turn the
113 // adjcallstackup instruction into a 'sub SPW, <amt>' and the
114 // adjcallstackdown instruction into 'add SPW, <amt>'
115 // TODO: consider using push / pop instead of sub + store / add
116 MachineInstr *Old = I;
117 uint64_t Amount = Old->getOperand(0).getImm();
119 // We need to keep the stack aligned properly. To do this, we round the
120 // amount of space needed for the outgoing arguments up to the next
121 // alignment boundary.
122 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
124 MachineInstr *New = 0;
125 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
126 New = BuildMI(MF, Old->getDebugLoc(),
127 TII.get(MSP430::SUB16ri), MSP430::SPW)
128 .addReg(MSP430::SPW).addImm(Amount);
130 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
131 // factor out the amount the callee already popped.
132 uint64_t CalleeAmt = Old->getOperand(1).getImm();
135 New = BuildMI(MF, Old->getDebugLoc(),
136 TII.get(MSP430::ADD16ri), MSP430::SPW)
137 .addReg(MSP430::SPW).addImm(Amount);
141 // The SRW implicit def is dead.
142 New->getOperand(3).setIsDead();
144 // Replace the pseudo instruction with a new instruction...
148 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
149 // If we are performing frame pointer elimination and if the callee pops
150 // something off the stack pointer, add it back.
151 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
152 MachineInstr *Old = I;
154 BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
155 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
156 // The SRW implicit def is dead.
157 New->getOperand(3).setIsDead();
167 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
168 int SPAdj, RegScavenger *RS) const {
169 assert(SPAdj == 0 && "Unexpected");
172 MachineInstr &MI = *II;
173 MachineBasicBlock &MBB = *MI.getParent();
174 MachineFunction &MF = *MBB.getParent();
175 DebugLoc dl = MI.getDebugLoc();
176 while (!MI.getOperand(i).isFI()) {
178 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
181 int FrameIndex = MI.getOperand(i).getIndex();
183 unsigned BasePtr = (hasFP(MF) ? MSP430::FPW : MSP430::SPW);
184 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
190 Offset += MF.getFrameInfo()->getStackSize();
192 Offset += 2; // Skip the saved FPW
194 // Fold imm into offset
195 Offset += MI.getOperand(i+1).getImm();
197 if (MI.getOpcode() == MSP430::ADD16ri) {
198 // This is actually "load effective address" of the stack slot
199 // instruction. We have only two-address instructions, thus we need to
200 // expand it into mov + add
202 MI.setDesc(TII.get(MSP430::MOV16rr));
203 MI.getOperand(i).ChangeToRegister(BasePtr, false);
208 // We need to materialize the offset via add instruction.
209 unsigned DstReg = MI.getOperand(0).getReg();
211 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
212 .addReg(DstReg).addImm(-Offset);
214 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
215 .addReg(DstReg).addImm(Offset);
220 MI.getOperand(i).ChangeToRegister(BasePtr, false);
221 MI.getOperand(i+1).ChangeToImmediate(Offset);
225 MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
227 // Create a frame entry for the FPW register that must be saved.
229 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4, true);
231 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
232 "Slot for FPW register must be last in order to be found!");
236 unsigned MSP430RegisterInfo::getRARegister() const {
240 unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
241 return hasFP(MF) ? MSP430::FPW : MSP430::SPW;
244 int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
245 llvm_unreachable("Not implemented yet!");
249 #include "MSP430GenRegisterInfo.inc"