1 //===- MSP430RegisterInfo.cpp - MSP430 Register Information ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MSP430 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "msp430-reg-info"
17 #include "MSP430MachineFunctionInfo.h"
18 #include "MSP430RegisterInfo.h"
19 #include "MSP430TargetMachine.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/Support/ErrorHandling.h"
31 // FIXME: Provide proper call frame setup / destroy opcodes.
32 MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
33 const TargetInstrInfo &tii)
34 : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
36 StackAlign = TM.getFrameInfo()->getStackAlignment();
40 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
41 const Function* F = MF->getFunction();
42 static const unsigned CalleeSavedRegs[] = {
43 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
44 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
47 static const unsigned CalleeSavedRegsFP[] = {
48 MSP430::R5W, MSP430::R6W, MSP430::R7W,
49 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
52 static const unsigned CalleeSavedRegsIntr[] = {
53 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
54 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
55 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
58 static const unsigned CalleeSavedRegsIntrFP[] = {
59 MSP430::R5W, MSP430::R6W, MSP430::R7W,
60 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
61 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
66 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
67 CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
69 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
70 CalleeSavedRegsIntr : CalleeSavedRegs);
74 const TargetRegisterClass *const *
75 MSP430RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
76 const Function* F = MF->getFunction();
77 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
78 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
79 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
80 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
81 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
84 static const TargetRegisterClass * const CalleeSavedRegClassesFP[] = {
85 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
86 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
87 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
88 &MSP430::GR16RegClass, 0
90 static const TargetRegisterClass * const CalleeSavedRegClassesIntr[] = {
91 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
92 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
93 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
94 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
95 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
96 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
99 static const TargetRegisterClass * const CalleeSavedRegClassesIntrFP[] = {
100 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
101 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
102 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
103 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
104 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
105 &MSP430::GR16RegClass, 0
109 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
110 CalleeSavedRegClassesIntrFP : CalleeSavedRegClassesFP);
112 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
113 CalleeSavedRegClassesIntr : CalleeSavedRegClasses);
116 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
117 BitVector Reserved(getNumRegs());
119 // Mark 4 special registers as reserved.
120 Reserved.set(MSP430::PCW);
121 Reserved.set(MSP430::SPW);
122 Reserved.set(MSP430::SRW);
123 Reserved.set(MSP430::CGW);
125 // Mark frame pointer as reserved if needed.
127 Reserved.set(MSP430::FPW);
132 const TargetRegisterClass *
133 MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
134 return &MSP430::GR16RegClass;
138 bool MSP430RegisterInfo::hasFP(const MachineFunction &MF) const {
139 const MachineFrameInfo *MFI = MF.getFrameInfo();
141 return (NoFramePointerElim ||
142 MF.getFrameInfo()->hasVarSizedObjects() ||
143 MFI->isFrameAddressTaken());
146 bool MSP430RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
147 return !MF.getFrameInfo()->hasVarSizedObjects();
150 void MSP430RegisterInfo::
151 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
152 MachineBasicBlock::iterator I) const {
153 if (!hasReservedCallFrame(MF)) {
154 // If the stack pointer can be changed after prologue, turn the
155 // adjcallstackup instruction into a 'sub SPW, <amt>' and the
156 // adjcallstackdown instruction into 'add SPW, <amt>'
157 // TODO: consider using push / pop instead of sub + store / add
158 MachineInstr *Old = I;
159 uint64_t Amount = Old->getOperand(0).getImm();
161 // We need to keep the stack aligned properly. To do this, we round the
162 // amount of space needed for the outgoing arguments up to the next
163 // alignment boundary.
164 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
166 MachineInstr *New = 0;
167 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
168 New = BuildMI(MF, Old->getDebugLoc(),
169 TII.get(MSP430::SUB16ri), MSP430::SPW)
170 .addReg(MSP430::SPW).addImm(Amount);
172 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
173 // factor out the amount the callee already popped.
174 uint64_t CalleeAmt = Old->getOperand(1).getImm();
177 New = BuildMI(MF, Old->getDebugLoc(),
178 TII.get(MSP430::ADD16ri), MSP430::SPW)
179 .addReg(MSP430::SPW).addImm(Amount);
183 // The SRW implicit def is dead.
184 New->getOperand(3).setIsDead();
186 // Replace the pseudo instruction with a new instruction...
190 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
191 // If we are performing frame pointer elimination and if the callee pops
192 // something off the stack pointer, add it back.
193 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
194 MachineInstr *Old = I;
196 BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
197 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
198 // The SRW implicit def is dead.
199 New->getOperand(3).setIsDead();
209 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
210 int SPAdj, FrameIndexValue *Value,
211 RegScavenger *RS) const {
212 assert(SPAdj == 0 && "Unexpected");
215 MachineInstr &MI = *II;
216 MachineBasicBlock &MBB = *MI.getParent();
217 MachineFunction &MF = *MBB.getParent();
218 DebugLoc dl = MI.getDebugLoc();
219 while (!MI.getOperand(i).isFI()) {
221 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
224 int FrameIndex = MI.getOperand(i).getIndex();
226 unsigned BasePtr = (hasFP(MF) ? MSP430::FPW : MSP430::SPW);
227 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
233 Offset += MF.getFrameInfo()->getStackSize();
235 Offset += 2; // Skip the saved FPW
237 // Fold imm into offset
238 Offset += MI.getOperand(i+1).getImm();
240 if (MI.getOpcode() == MSP430::ADD16ri) {
241 // This is actually "load effective address" of the stack slot
242 // instruction. We have only two-address instructions, thus we need to
243 // expand it into mov + add
245 MI.setDesc(TII.get(MSP430::MOV16rr));
246 MI.getOperand(i).ChangeToRegister(BasePtr, false);
251 // We need to materialize the offset via add instruction.
252 unsigned DstReg = MI.getOperand(0).getReg();
254 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
255 .addReg(DstReg).addImm(-Offset);
257 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
258 .addReg(DstReg).addImm(Offset);
263 MI.getOperand(i).ChangeToRegister(BasePtr, false);
264 MI.getOperand(i+1).ChangeToImmediate(Offset);
269 MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
271 // Create a frame entry for the FPW register that must be saved.
273 int ATTRIBUTE_UNUSED FrameIdx =
274 MF.getFrameInfo()->CreateFixedObject(2, -4, true, false);
275 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
276 "Slot for FPW register must be last in order to be found!");
281 void MSP430RegisterInfo::emitPrologue(MachineFunction &MF) const {
282 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
283 MachineFrameInfo *MFI = MF.getFrameInfo();
284 MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
285 MachineBasicBlock::iterator MBBI = MBB.begin();
286 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
288 // Get the number of bytes to allocate from the FrameInfo.
289 uint64_t StackSize = MFI->getStackSize();
291 uint64_t NumBytes = 0;
293 // Calculate required stack adjustment
294 uint64_t FrameSize = StackSize - 2;
295 NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize();
297 // Get the offset of the stack slot for the EBP register... which is
298 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
299 // Update the frame offset adjustment.
300 MFI->setOffsetAdjustment(-NumBytes);
302 // Save FPW into the appropriate stack slot...
303 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
304 .addReg(MSP430::FPW, RegState::Kill);
306 // Update FPW with the new base value...
307 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
308 .addReg(MSP430::SPW);
310 // Mark the FramePtr as live-in in every block except the entry.
311 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
313 I->addLiveIn(MSP430::FPW);
316 NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize();
318 // Skip the callee-saved push instructions.
319 while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
322 if (MBBI != MBB.end())
323 DL = MBBI->getDebugLoc();
325 if (NumBytes) { // adjust stack pointer: SPW -= numbytes
326 // If there is an SUB16ri of SPW immediately before this instruction, merge
328 //NumBytes -= mergeSPUpdates(MBB, MBBI, true);
329 // If there is an ADD16ri or SUB16ri of SPW immediately after this
330 // instruction, merge the two instructions.
331 // mergeSPUpdatesDown(MBB, MBBI, &NumBytes);
335 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
336 .addReg(MSP430::SPW).addImm(NumBytes);
337 // The SRW implicit def is dead.
338 MI->getOperand(3).setIsDead();
343 void MSP430RegisterInfo::emitEpilogue(MachineFunction &MF,
344 MachineBasicBlock &MBB) const {
345 const MachineFrameInfo *MFI = MF.getFrameInfo();
346 MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
347 MachineBasicBlock::iterator MBBI = prior(MBB.end());
348 unsigned RetOpcode = MBBI->getOpcode();
349 DebugLoc DL = MBBI->getDebugLoc();
353 case MSP430::RETI: break; // These are ok
355 llvm_unreachable("Can only insert epilog into returning blocks");
358 // Get the number of bytes to allocate from the FrameInfo
359 uint64_t StackSize = MFI->getStackSize();
360 unsigned CSSize = MSP430FI->getCalleeSavedFrameSize();
361 uint64_t NumBytes = 0;
364 // Calculate required stack adjustment
365 uint64_t FrameSize = StackSize - 2;
366 NumBytes = FrameSize - CSSize;
369 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
371 NumBytes = StackSize - CSSize;
373 // Skip the callee-saved pop instructions.
374 while (MBBI != MBB.begin()) {
375 MachineBasicBlock::iterator PI = prior(MBBI);
376 unsigned Opc = PI->getOpcode();
377 if (Opc != MSP430::POP16r && !PI->getDesc().isTerminator())
382 DL = MBBI->getDebugLoc();
384 // If there is an ADD16ri or SUB16ri of SPW immediately before this
385 // instruction, merge the two instructions.
386 //if (NumBytes || MFI->hasVarSizedObjects())
387 // mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
389 if (MFI->hasVarSizedObjects()) {
390 BuildMI(MBB, MBBI, DL,
391 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
394 BuildMI(MBB, MBBI, DL,
395 TII.get(MSP430::SUB16ri), MSP430::SPW)
396 .addReg(MSP430::SPW).addImm(CSSize);
397 // The SRW implicit def is dead.
398 MI->getOperand(3).setIsDead();
401 // adjust stack pointer back: SPW += numbytes
404 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
405 .addReg(MSP430::SPW).addImm(NumBytes);
406 // The SRW implicit def is dead.
407 MI->getOperand(3).setIsDead();
412 unsigned MSP430RegisterInfo::getRARegister() const {
416 unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
417 return hasFP(MF) ? MSP430::FPW : MSP430::SPW;
420 int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
421 llvm_unreachable("Not implemented yet!");
425 #include "MSP430GenRegisterInfo.inc"