1 //===- MSP430RegisterInfo.cpp - MSP430 Register Information ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MSP430 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "msp430-reg-info"
17 #include "MSP430MachineFunctionInfo.h"
18 #include "MSP430RegisterInfo.h"
19 #include "MSP430TargetMachine.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/BitVector.h"
29 // FIXME: Provide proper call frame setup / destroy opcodes.
30 MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
31 const TargetInstrInfo &tii)
32 : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
34 StackAlign = TM.getFrameInfo()->getStackAlignment();
38 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
39 static const unsigned CalleeSavedRegs[] = {
40 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
41 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
45 return CalleeSavedRegs;
48 const TargetRegisterClass* const*
49 MSP430RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
50 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
51 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
52 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
53 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
54 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
58 return CalleeSavedRegClasses;
62 MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
63 BitVector Reserved(getNumRegs());
65 // Mark 4 special registers as reserved.
66 Reserved.set(MSP430::PCW);
67 Reserved.set(MSP430::SPW);
68 Reserved.set(MSP430::SRW);
69 Reserved.set(MSP430::CGW);
71 // Mark frame pointer as reserved if needed.
73 Reserved.set(MSP430::FPW);
78 const TargetRegisterClass* MSP430RegisterInfo::getPointerRegClass() const {
79 return &MSP430::GR16RegClass;
83 bool MSP430RegisterInfo::hasFP(const MachineFunction &MF) const {
84 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
87 bool MSP430RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
88 return !MF.getFrameInfo()->hasVarSizedObjects();
91 void MSP430RegisterInfo::
92 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
93 MachineBasicBlock::iterator I) const {
94 if (!hasReservedCallFrame(MF)) {
95 // If the stack pointer can be changed after prologue, turn the
96 // adjcallstackup instruction into a 'sub SPW, <amt>' and the
97 // adjcallstackdown instruction into 'add SPW, <amt>'
98 // TODO: consider using push / pop instead of sub + store / add
99 MachineInstr *Old = I;
100 uint64_t Amount = Old->getOperand(0).getImm();
102 // We need to keep the stack aligned properly. To do this, we round the
103 // amount of space needed for the outgoing arguments up to the next
104 // alignment boundary.
105 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
107 MachineInstr *New = 0;
108 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
109 New = BuildMI(MF, Old->getDebugLoc(),
110 TII.get(MSP430::SUB16ri), MSP430::SPW)
111 .addReg(MSP430::SPW).addImm(Amount);
113 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
114 // factor out the amount the callee already popped.
115 uint64_t CalleeAmt = Old->getOperand(1).getImm();
118 New = BuildMI(MF, Old->getDebugLoc(),
119 TII.get(MSP430::ADD16ri), MSP430::SPW)
120 .addReg(MSP430::SPW).addImm(Amount);
124 // The SRW implicit def is dead.
125 New->getOperand(3).setIsDead();
127 // Replace the pseudo instruction with a new instruction...
131 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
132 // If we are performing frame pointer elimination and if the callee pops
133 // something off the stack pointer, add it back.
134 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
135 MachineInstr *Old = I;
137 BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
138 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
139 // The SRW implicit def is dead.
140 New->getOperand(3).setIsDead();
150 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
151 int SPAdj, RegScavenger *RS) const {
152 assert(SPAdj == 0 && "Unexpected");
155 MachineInstr &MI = *II;
156 MachineBasicBlock &MBB = *MI.getParent();
157 MachineFunction &MF = *MBB.getParent();
158 DebugLoc dl = MI.getDebugLoc();
159 while (!MI.getOperand(i).isFI()) {
161 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
164 int FrameIndex = MI.getOperand(i).getIndex();
166 unsigned BasePtr = (hasFP(MF) ? MSP430::FPW : MSP430::SPW);
167 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
173 Offset += MF.getFrameInfo()->getStackSize();
175 Offset += 2; // Skip the saved FPW
177 // Fold imm into offset
178 Offset += MI.getOperand(i+1).getImm();
180 if (MI.getOpcode() == MSP430::ADD16ri) {
181 // This is actually "load effective address" of the stack slot
182 // instruction. We have only two-address instructions, thus we need to
183 // expand it into mov + add
185 MI.setDesc(TII.get(MSP430::MOV16rr));
186 MI.getOperand(i).ChangeToRegister(BasePtr, false);
191 // We need to materialize the offset via add instruction.
192 unsigned DstReg = MI.getOperand(0).getReg();
194 BuildMI(MBB, next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
195 .addReg(DstReg).addImm(-Offset);
197 BuildMI(MBB, next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
198 .addReg(DstReg).addImm(Offset);
203 MI.getOperand(i).ChangeToRegister(BasePtr, false);
204 MI.getOperand(i+1).ChangeToImmediate(Offset);
208 MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
210 // Create a frame entry for the FPW register that must be saved.
212 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4);
213 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
214 "Slot for FPW register must be last in order to be found!");
220 void MSP430RegisterInfo::emitPrologue(MachineFunction &MF) const {
221 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
222 MachineFrameInfo *MFI = MF.getFrameInfo();
223 MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
224 MachineBasicBlock::iterator MBBI = MBB.begin();
225 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
226 DebugLoc::getUnknownLoc());
228 // Get the number of bytes to allocate from the FrameInfo.
229 uint64_t StackSize = MFI->getStackSize();
231 uint64_t NumBytes = 0;
233 // Calculate required stack adjustment
234 uint64_t FrameSize = StackSize - 2;
235 NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize();
237 // Get the offset of the stack slot for the EBP register... which is
238 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
239 // Update the frame offset adjustment.
240 MFI->setOffsetAdjustment(-NumBytes);
242 // Save FPW into the appropriate stack slot...
243 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
244 .addReg(MSP430::FPW, RegState::Kill);
246 // Update FPW with the new base value...
247 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
248 .addReg(MSP430::SPW);
250 // Mark the FramePtr as live-in in every block except the entry.
251 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
253 I->addLiveIn(MSP430::FPW);
256 NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize();
258 // Skip the callee-saved push instructions.
259 while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
262 if (MBBI != MBB.end())
263 DL = MBBI->getDebugLoc();
265 if (NumBytes) { // adjust stack pointer: SPW -= numbytes
266 // If there is an SUB16ri of SPW immediately before this instruction, merge
268 //NumBytes -= mergeSPUpdates(MBB, MBBI, true);
269 // If there is an ADD16ri or SUB16ri of SPW immediately after this
270 // instruction, merge the two instructions.
271 // mergeSPUpdatesDown(MBB, MBBI, &NumBytes);
275 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
276 .addReg(MSP430::SPW).addImm(NumBytes);
277 // The SRW implicit def is dead.
278 MI->getOperand(3).setIsDead();
283 void MSP430RegisterInfo::emitEpilogue(MachineFunction &MF,
284 MachineBasicBlock &MBB) const {
285 const MachineFrameInfo *MFI = MF.getFrameInfo();
286 MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
287 MachineBasicBlock::iterator MBBI = prior(MBB.end());
288 unsigned RetOpcode = MBBI->getOpcode();
289 DebugLoc DL = MBBI->getDebugLoc();
292 case MSP430::RET: break; // These are ok
294 assert(0 && "Can only insert epilog into returning blocks");
297 // Get the number of bytes to allocate from the FrameInfo
298 uint64_t StackSize = MFI->getStackSize();
299 unsigned CSSize = MSP430FI->getCalleeSavedFrameSize();
300 uint64_t NumBytes = 0;
303 // Calculate required stack adjustment
304 uint64_t FrameSize = StackSize - 2;
305 NumBytes = FrameSize - CSSize;
308 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
310 NumBytes = StackSize - CSSize;
312 // Skip the callee-saved pop instructions.
313 MachineBasicBlock::iterator LastCSPop = MBBI;
314 while (MBBI != MBB.begin()) {
315 MachineBasicBlock::iterator PI = prior(MBBI);
316 unsigned Opc = PI->getOpcode();
317 if (Opc != MSP430::POP16r && !PI->getDesc().isTerminator())
322 DL = MBBI->getDebugLoc();
324 // If there is an ADD16ri or SUB16ri of SPW immediately before this
325 // instruction, merge the two instructions.
326 //if (NumBytes || MFI->hasVarSizedObjects())
327 // mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
329 if (MFI->hasVarSizedObjects()) {
330 assert(0 && "Not implemented yet!");
332 // adjust stack pointer back: SPW += numbytes
335 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
336 .addReg(MSP430::SPW).addImm(NumBytes);
337 // The SRW implicit def is dead.
338 MI->getOperand(3).setIsDead();
343 unsigned MSP430RegisterInfo::getRARegister() const {
347 unsigned MSP430RegisterInfo::getFrameRegister(MachineFunction &MF) const {
348 return hasFP(MF) ? MSP430::FPW : MSP430::SPW;
351 int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
352 assert(0 && "Not implemented yet!");
356 #include "MSP430GenRegisterInfo.inc"