1 //===- MSP430RegisterInfo.td - MSP430 Register defs ----------*- tblgen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the MSP430 register file
12 //===----------------------------------------------------------------------===//
14 class MSP430Reg<bits<4> num, string n> : Register<n> {
15 field bits<4> Num = num;
16 let Namespace = "MSP430";
19 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
23 def PC : MSP430Reg<0, "r0">;
24 def SP : MSP430Reg<1, "r1">;
25 def SR : MSP430Reg<2, "r2">;
26 def CG : MSP430Reg<3, "r3">;
27 def FP : MSP430Reg<4, "r4">;
28 def R5 : MSP430Reg<5, "r5">;
29 def R6 : MSP430Reg<6, "r6">;
30 def R7 : MSP430Reg<7, "r7">;
31 def R8 : MSP430Reg<8, "r8">;
32 def R9 : MSP430Reg<9, "r9">;
33 def R10 : MSP430Reg<10, "r10">;
34 def R11 : MSP430Reg<11, "r11">;
35 def R12 : MSP430Reg<12, "r12">;
36 def R13 : MSP430Reg<13, "r13">;
37 def R14 : MSP430Reg<14, "r14">;
38 def R15 : MSP430Reg<15, "r15">;
40 // FIXME: we need subregs & special handling for 8 bit stuff
42 def GR16 : RegisterClass<"MSP430", [i16], 16,
44 [R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
45 // Frame pointer, sometimes allocable
47 // Volatile, but not allocable
51 iterator allocation_order_end(const MachineFunction &MF) const;
55 GR16Class::allocation_order_end(const MachineFunction &MF) const {
56 const TargetMachine &TM = MF.getTarget();
57 const TargetRegisterInfo *RI = TM.getRegisterInfo();
58 // Depending on whether the function uses frame pointer or not, last 5 or 4
59 // registers on the list above are reserved