1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCExpr.h"
11 #include "MCTargetDesc/MipsMCTargetDesc.h"
12 #include "MipsRegisterInfo.h"
13 #include "MipsTargetStreamer.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstBuilder.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/MC/MCTargetAsmParser.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/TargetRegistry.h"
36 class MipsAssemblerOptions {
38 MipsAssemblerOptions() : aTReg(1), reorder(true), macro(true) {}
40 unsigned getATRegNum() { return aTReg; }
41 bool setATReg(unsigned Reg);
43 bool isReorder() { return reorder; }
44 void setReorder() { reorder = true; }
45 void setNoreorder() { reorder = false; }
47 bool isMacro() { return macro; }
48 void setMacro() { macro = true; }
49 void setNomacro() { macro = false; }
59 class MipsAsmParser : public MCTargetAsmParser {
61 MipsTargetStreamer &getTargetStreamer() {
62 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
63 return static_cast<MipsTargetStreamer &>(TS);
68 MipsAssemblerOptions Options;
69 bool hasConsumedDollar;
71 #define GET_ASSEMBLER_HEADER
72 #include "MipsGenAsmMatcher.inc"
74 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
75 SmallVectorImpl<MCParsedAsmOperand *> &Operands,
76 MCStreamer &Out, unsigned &ErrorInfo,
77 bool MatchingInlineAsm);
79 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
81 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
83 SmallVectorImpl<MCParsedAsmOperand *> &Operands);
85 bool ParseDirective(AsmToken DirectiveID);
87 MipsAsmParser::OperandMatchResultTy
88 parseRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands, int RegKind);
90 MipsAsmParser::OperandMatchResultTy
91 parseMSARegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands, int RegKind);
93 MipsAsmParser::OperandMatchResultTy
94 parseMSACtrlRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
97 MipsAsmParser::OperandMatchResultTy
98 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
100 bool parsePtrReg(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
103 MipsAsmParser::OperandMatchResultTy
104 parsePtrReg(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
106 MipsAsmParser::OperandMatchResultTy
107 parseGPR32(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
109 MipsAsmParser::OperandMatchResultTy
110 parseGPR64(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
112 MipsAsmParser::OperandMatchResultTy
113 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
115 MipsAsmParser::OperandMatchResultTy
116 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
118 MipsAsmParser::OperandMatchResultTy
119 parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
121 MipsAsmParser::OperandMatchResultTy
122 parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
124 MipsAsmParser::OperandMatchResultTy
125 parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
127 MipsAsmParser::OperandMatchResultTy
128 parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
130 MipsAsmParser::OperandMatchResultTy
131 parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
133 MipsAsmParser::OperandMatchResultTy
134 parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
136 MipsAsmParser::OperandMatchResultTy
137 parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
139 MipsAsmParser::OperandMatchResultTy
140 parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
142 MipsAsmParser::OperandMatchResultTy
143 parseCOP2(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
145 MipsAsmParser::OperandMatchResultTy
146 parseMSA128BRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
148 MipsAsmParser::OperandMatchResultTy
149 parseMSA128HRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
151 MipsAsmParser::OperandMatchResultTy
152 parseMSA128WRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
154 MipsAsmParser::OperandMatchResultTy
155 parseMSA128DRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
157 MipsAsmParser::OperandMatchResultTy
158 parseMSA128CtrlRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
160 MipsAsmParser::OperandMatchResultTy
161 parseInvNum(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
163 MipsAsmParser::OperandMatchResultTy
164 parseLSAImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
166 bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
169 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand *> &,
172 int tryParseRegister(bool is64BitReg);
174 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
177 bool needsExpansion(MCInst &Inst);
179 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
180 SmallVectorImpl<MCInst> &Instructions);
181 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
182 SmallVectorImpl<MCInst> &Instructions);
183 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
184 SmallVectorImpl<MCInst> &Instructions);
185 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
186 SmallVectorImpl<MCInst> &Instructions);
187 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
188 SmallVectorImpl<MCInst> &Instructions, bool isLoad,
190 bool reportParseError(StringRef ErrorMsg);
192 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
193 bool parseRelocOperand(const MCExpr *&Res);
195 const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
197 bool isEvaluated(const MCExpr *Expr);
198 bool parseSetFeature(uint64_t Feature);
199 bool parseDirectiveCPSetup();
200 bool parseDirectiveSet();
201 bool parseDirectiveOption();
203 bool parseSetAtDirective();
204 bool parseSetNoAtDirective();
205 bool parseSetMacroDirective();
206 bool parseSetNoMacroDirective();
207 bool parseSetReorderDirective();
208 bool parseSetNoReorderDirective();
209 bool parseSetNoMips16Directive();
211 bool parseSetAssignment();
213 bool parseDataDirective(unsigned Size, SMLoc L);
214 bool parseDirectiveGpWord();
215 bool parseDirectiveGpDWord();
217 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
219 bool isGP64() const {
220 return (STI.getFeatureBits() & Mips::FeatureGP64Bit) != 0;
223 bool isFP64() const {
224 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
227 bool isN32() const { return STI.getFeatureBits() & Mips::FeatureN32; }
228 bool isN64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
230 bool isMicroMips() const {
231 return STI.getFeatureBits() & Mips::FeatureMicroMips;
234 bool parseRegister(unsigned &RegNum);
236 bool eatComma(StringRef ErrorStr);
238 int matchRegisterName(StringRef Symbol, bool is64BitReg);
240 int matchCPURegisterName(StringRef Symbol);
242 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
244 int matchFPURegisterName(StringRef Name);
246 int matchFCCRegisterName(StringRef Name);
248 int matchACRegisterName(StringRef Name);
250 int matchMSA128RegisterName(StringRef Name);
252 int matchMSA128CtrlRegisterName(StringRef Name);
254 int regKindToRegClass(int RegKind);
256 unsigned getReg(int RC, int RegNo);
258 unsigned getGPR(int RegNo);
262 // Warn if RegNo is the current assembler temporary.
263 void warnIfAssemblerTemporary(int RegNo);
265 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
266 SmallVectorImpl<MCInst> &Instructions);
268 // Helper function that checks if the value of a vector index is within the
269 // boundaries of accepted values for each RegisterKind
270 // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
271 bool validateMSAIndex(int Val, int RegKind);
273 void setFeatureBits(unsigned Feature, StringRef FeatureString) {
274 if (!(STI.getFeatureBits() & Feature)) {
275 setAvailableFeatures(ComputeAvailableFeatures(
276 STI.ToggleFeature(FeatureString)));
280 void clearFeatureBits(unsigned Feature, StringRef FeatureString) {
281 if (STI.getFeatureBits() & Feature) {
282 setAvailableFeatures(ComputeAvailableFeatures(
283 STI.ToggleFeature(FeatureString)));
288 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
289 const MCInstrInfo &MII)
290 : MCTargetAsmParser(), STI(sti), Parser(parser),
291 hasConsumedDollar(false) {
292 // Initialize the set of available features.
293 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
295 // Assert exactly one ABI was chosen.
296 assert((((STI.getFeatureBits() & Mips::FeatureO32) != 0) +
297 ((STI.getFeatureBits() & Mips::FeatureEABI) != 0) +
298 ((STI.getFeatureBits() & Mips::FeatureN32) != 0) +
299 ((STI.getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
302 MCAsmParser &getParser() const { return Parser; }
303 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
309 /// MipsOperand - Instances of this class represent a parsed Mips machine
311 class MipsOperand : public MCParsedAsmOperand {
349 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
377 SMLoc StartLoc, EndLoc;
380 void addRegOperands(MCInst &Inst, unsigned N) const {
381 assert(N == 1 && "Invalid number of operands!");
382 Inst.addOperand(MCOperand::CreateReg(getReg()));
385 void addPtrRegOperands(MCInst &Inst, unsigned N) const {
386 assert(N == 1 && "Invalid number of operands!");
387 Inst.addOperand(MCOperand::CreateReg(getPtrReg()));
390 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
391 // Add as immediate when possible. Null MCExpr = 0.
393 Inst.addOperand(MCOperand::CreateImm(0));
394 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
395 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
397 Inst.addOperand(MCOperand::CreateExpr(Expr));
400 void addImmOperands(MCInst &Inst, unsigned N) const {
401 assert(N == 1 && "Invalid number of operands!");
402 const MCExpr *Expr = getImm();
406 void addMemOperands(MCInst &Inst, unsigned N) const {
407 assert(N == 2 && "Invalid number of operands!");
409 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
411 const MCExpr *Expr = getMemOff();
415 bool isReg() const { return Kind == k_Register; }
416 bool isImm() const { return Kind == k_Immediate; }
417 bool isToken() const { return Kind == k_Token; }
418 bool isMem() const { return Kind == k_Memory; }
419 bool isPtrReg() const { return Kind == k_PtrReg; }
420 bool isInvNum() const { return Kind == k_Immediate; }
421 bool isLSAImm() const { return Kind == k_LSAImm; }
423 StringRef getToken() const {
424 assert(Kind == k_Token && "Invalid access!");
425 return StringRef(Tok.Data, Tok.Length);
428 unsigned getReg() const {
429 assert((Kind == k_Register) && "Invalid access!");
433 unsigned getPtrReg() const {
434 assert((Kind == k_PtrReg) && "Invalid access!");
438 void setRegKind(RegisterKind RegKind) {
439 assert((Kind == k_Register || Kind == k_PtrReg) && "Invalid access!");
443 const MCExpr *getImm() const {
444 assert((Kind == k_Immediate || Kind == k_LSAImm) && "Invalid access!");
448 unsigned getMemBase() const {
449 assert((Kind == k_Memory) && "Invalid access!");
453 const MCExpr *getMemOff() const {
454 assert((Kind == k_Memory) && "Invalid access!");
458 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
459 MipsOperand *Op = new MipsOperand(k_Token);
460 Op->Tok.Data = Str.data();
461 Op->Tok.Length = Str.size();
467 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
468 MipsOperand *Op = new MipsOperand(k_Register);
469 Op->Reg.RegNum = RegNum;
470 Op->Reg.Kind = Kind_None;
476 static MipsOperand *CreatePtrReg(unsigned RegNum, SMLoc S, SMLoc E) {
477 MipsOperand *Op = new MipsOperand(k_PtrReg);
478 Op->Reg.RegNum = RegNum;
479 Op->Reg.Kind = Kind_None;
485 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
486 MipsOperand *Op = new MipsOperand(k_Immediate);
493 static MipsOperand *CreateLSAImm(const MCExpr *Val, SMLoc S, SMLoc E) {
494 MipsOperand *Op = new MipsOperand(k_LSAImm);
501 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off, SMLoc S,
503 MipsOperand *Op = new MipsOperand(k_Memory);
511 bool isGPR32Asm() const {
512 return Kind == k_Register && Reg.Kind == Kind_GPR32;
514 void addRegAsmOperands(MCInst &Inst, unsigned N) const {
515 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
518 bool isGPR64Asm() const {
519 return Kind == k_Register && Reg.Kind == Kind_GPR64;
522 bool isHWRegsAsm() const {
523 assert((Kind == k_Register) && "Invalid access!");
524 return Reg.Kind == Kind_HWRegs;
527 bool isCCRAsm() const {
528 assert((Kind == k_Register) && "Invalid access!");
529 return Reg.Kind == Kind_CCRRegs;
532 bool isAFGR64Asm() const {
533 return Kind == k_Register && Reg.Kind == Kind_AFGR64Regs;
536 bool isFGR64Asm() const {
537 return Kind == k_Register && Reg.Kind == Kind_FGR64Regs;
540 bool isFGR32Asm() const {
541 return (Kind == k_Register) && Reg.Kind == Kind_FGR32Regs;
544 bool isFGRH32Asm() const {
545 return (Kind == k_Register) && Reg.Kind == Kind_FGRH32Regs;
548 bool isFCCRegsAsm() const {
549 return (Kind == k_Register) && Reg.Kind == Kind_FCCRegs;
552 bool isACC64DSPAsm() const {
553 return Kind == k_Register && Reg.Kind == Kind_ACC64DSP;
556 bool isLO32DSPAsm() const {
557 return Kind == k_Register && Reg.Kind == Kind_LO32DSP;
560 bool isHI32DSPAsm() const {
561 return Kind == k_Register && Reg.Kind == Kind_HI32DSP;
564 bool isCOP2Asm() const { return Kind == k_Register && Reg.Kind == Kind_COP2; }
566 bool isMSA128BAsm() const {
567 return Kind == k_Register && Reg.Kind == Kind_MSA128BRegs;
570 bool isMSA128HAsm() const {
571 return Kind == k_Register && Reg.Kind == Kind_MSA128HRegs;
574 bool isMSA128WAsm() const {
575 return Kind == k_Register && Reg.Kind == Kind_MSA128WRegs;
578 bool isMSA128DAsm() const {
579 return Kind == k_Register && Reg.Kind == Kind_MSA128DRegs;
582 bool isMSA128CRAsm() const {
583 return Kind == k_Register && Reg.Kind == Kind_MSA128CtrlRegs;
586 /// getStartLoc - Get the location of the first token of this operand.
587 SMLoc getStartLoc() const { return StartLoc; }
588 /// getEndLoc - Get the location of the last token of this operand.
589 SMLoc getEndLoc() const { return EndLoc; }
591 virtual void print(raw_ostream &OS) const {
592 llvm_unreachable("unimplemented!");
594 }; // class MipsOperand
598 extern const MCInstrDesc MipsInsts[];
600 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
601 return MipsInsts[Opcode];
604 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
605 SmallVectorImpl<MCInst> &Instructions) {
606 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
610 if (MCID.isBranch() || MCID.isCall()) {
611 const unsigned Opcode = Inst.getOpcode();
619 assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
620 Offset = Inst.getOperand(2);
622 break; // We'll deal with this situation later on when applying fixups.
623 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
624 return Error(IDLoc, "branch target out of range");
625 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
626 return Error(IDLoc, "branch to misaligned address");
636 assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
637 Offset = Inst.getOperand(1);
639 break; // We'll deal with this situation later on when applying fixups.
640 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
641 return Error(IDLoc, "branch target out of range");
642 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
643 return Error(IDLoc, "branch to misaligned address");
648 if (MCID.hasDelaySlot() && Options.isReorder()) {
649 // If this instruction has a delay slot and .set reorder is active,
650 // emit a NOP after it.
651 Instructions.push_back(Inst);
653 NopInst.setOpcode(Mips::SLL);
654 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
655 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
656 NopInst.addOperand(MCOperand::CreateImm(0));
657 Instructions.push_back(NopInst);
661 if (MCID.mayLoad() || MCID.mayStore()) {
662 // Check the offset of memory operand, if it is a symbol
663 // reference or immediate we may have to expand instructions.
664 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
665 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
666 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
667 (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
668 MCOperand &Op = Inst.getOperand(i);
670 int MemOffset = Op.getImm();
671 if (MemOffset < -32768 || MemOffset > 32767) {
672 // Offset can't exceed 16bit value.
673 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
676 } else if (Op.isExpr()) {
677 const MCExpr *Expr = Op.getExpr();
678 if (Expr->getKind() == MCExpr::SymbolRef) {
679 const MCSymbolRefExpr *SR =
680 static_cast<const MCSymbolRefExpr *>(Expr);
681 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
683 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
686 } else if (!isEvaluated(Expr)) {
687 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
695 if (needsExpansion(Inst))
696 expandInstruction(Inst, IDLoc, Instructions);
698 Instructions.push_back(Inst);
703 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
705 switch (Inst.getOpcode()) {
706 case Mips::LoadImm32Reg:
707 case Mips::LoadAddr32Imm:
708 case Mips::LoadAddr32Reg:
719 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
720 SmallVectorImpl<MCInst> &Instructions) {
721 switch (Inst.getOpcode()) {
722 case Mips::LoadImm32Reg:
723 return expandLoadImm(Inst, IDLoc, Instructions);
724 case Mips::LoadAddr32Imm:
725 return expandLoadAddressImm(Inst, IDLoc, Instructions);
726 case Mips::LoadAddr32Reg:
727 return expandLoadAddressReg(Inst, IDLoc, Instructions);
729 Instructions.push_back(MCInstBuilder(Mips::ADDi)
730 .addReg(Inst.getOperand(0).getReg())
731 .addReg(Inst.getOperand(1).getReg())
732 .addImm(-Inst.getOperand(2).getImm()));
735 Instructions.push_back(MCInstBuilder(Mips::ADDiu)
736 .addReg(Inst.getOperand(0).getReg())
737 .addReg(Inst.getOperand(1).getReg())
738 .addImm(-Inst.getOperand(2).getImm()));
741 Instructions.push_back(MCInstBuilder(Mips::DADDi)
742 .addReg(Inst.getOperand(0).getReg())
743 .addReg(Inst.getOperand(1).getReg())
744 .addImm(-Inst.getOperand(2).getImm()));
747 Instructions.push_back(MCInstBuilder(Mips::DADDiu)
748 .addReg(Inst.getOperand(0).getReg())
749 .addReg(Inst.getOperand(1).getReg())
750 .addImm(-Inst.getOperand(2).getImm()));
755 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
756 SmallVectorImpl<MCInst> &Instructions) {
758 const MCOperand &ImmOp = Inst.getOperand(1);
759 assert(ImmOp.isImm() && "expected immediate operand kind");
760 const MCOperand &RegOp = Inst.getOperand(0);
761 assert(RegOp.isReg() && "expected register operand kind");
763 int ImmValue = ImmOp.getImm();
764 tmpInst.setLoc(IDLoc);
765 if (0 <= ImmValue && ImmValue <= 65535) {
766 // For 0 <= j <= 65535.
767 // li d,j => ori d,$zero,j
768 tmpInst.setOpcode(Mips::ORi);
769 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
770 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
771 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
772 Instructions.push_back(tmpInst);
773 } else if (ImmValue < 0 && ImmValue >= -32768) {
774 // For -32768 <= j < 0.
775 // li d,j => addiu d,$zero,j
776 tmpInst.setOpcode(Mips::ADDiu);
777 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
778 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
779 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
780 Instructions.push_back(tmpInst);
782 // For any other value of j that is representable as a 32-bit integer.
783 // li d,j => lui d,hi16(j)
785 tmpInst.setOpcode(Mips::LUi);
786 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
787 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
788 Instructions.push_back(tmpInst);
790 tmpInst.setOpcode(Mips::ORi);
791 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
792 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
793 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
794 tmpInst.setLoc(IDLoc);
795 Instructions.push_back(tmpInst);
800 MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
801 SmallVectorImpl<MCInst> &Instructions) {
803 const MCOperand &ImmOp = Inst.getOperand(2);
804 assert(ImmOp.isImm() && "expected immediate operand kind");
805 const MCOperand &SrcRegOp = Inst.getOperand(1);
806 assert(SrcRegOp.isReg() && "expected register operand kind");
807 const MCOperand &DstRegOp = Inst.getOperand(0);
808 assert(DstRegOp.isReg() && "expected register operand kind");
809 int ImmValue = ImmOp.getImm();
810 if (-32768 <= ImmValue && ImmValue <= 65535) {
811 // For -32768 <= j <= 65535.
812 // la d,j(s) => addiu d,s,j
813 tmpInst.setOpcode(Mips::ADDiu);
814 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
815 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
816 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
817 Instructions.push_back(tmpInst);
819 // For any other value of j that is representable as a 32-bit integer.
820 // la d,j(s) => lui d,hi16(j)
823 tmpInst.setOpcode(Mips::LUi);
824 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
825 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
826 Instructions.push_back(tmpInst);
828 tmpInst.setOpcode(Mips::ORi);
829 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
830 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
831 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
832 Instructions.push_back(tmpInst);
834 tmpInst.setOpcode(Mips::ADDu);
835 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
836 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
837 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
838 Instructions.push_back(tmpInst);
843 MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
844 SmallVectorImpl<MCInst> &Instructions) {
846 const MCOperand &ImmOp = Inst.getOperand(1);
847 assert(ImmOp.isImm() && "expected immediate operand kind");
848 const MCOperand &RegOp = Inst.getOperand(0);
849 assert(RegOp.isReg() && "expected register operand kind");
850 int ImmValue = ImmOp.getImm();
851 if (-32768 <= ImmValue && ImmValue <= 65535) {
852 // For -32768 <= j <= 65535.
853 // la d,j => addiu d,$zero,j
854 tmpInst.setOpcode(Mips::ADDiu);
855 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
856 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
857 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
858 Instructions.push_back(tmpInst);
860 // For any other value of j that is representable as a 32-bit integer.
861 // la d,j => lui d,hi16(j)
863 tmpInst.setOpcode(Mips::LUi);
864 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
865 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
866 Instructions.push_back(tmpInst);
868 tmpInst.setOpcode(Mips::ORi);
869 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
870 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
871 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
872 Instructions.push_back(tmpInst);
876 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
877 SmallVectorImpl<MCInst> &Instructions,
878 bool isLoad, bool isImmOpnd) {
879 const MCSymbolRefExpr *SR;
881 unsigned ImmOffset, HiOffset, LoOffset;
882 const MCExpr *ExprOffset;
884 unsigned AtRegNum = getReg(
885 (isGP64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, getATReg());
886 // 1st operand is either the source or destination register.
887 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
888 unsigned RegOpNum = Inst.getOperand(0).getReg();
889 // 2nd operand is the base register.
890 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
891 unsigned BaseRegNum = Inst.getOperand(1).getReg();
892 // 3rd operand is either an immediate or expression.
894 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
895 ImmOffset = Inst.getOperand(2).getImm();
896 LoOffset = ImmOffset & 0x0000ffff;
897 HiOffset = (ImmOffset & 0xffff0000) >> 16;
898 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
899 if (LoOffset & 0x8000)
902 ExprOffset = Inst.getOperand(2).getExpr();
903 // All instructions will have the same location.
904 TempInst.setLoc(IDLoc);
905 // 1st instruction in expansion is LUi. For load instruction we can use
906 // the dst register as a temporary if base and dst are different,
907 // but for stores we must use $at.
908 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
909 TempInst.setOpcode(Mips::LUi);
910 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
912 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
914 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
915 SR = static_cast<const MCSymbolRefExpr *>(ExprOffset);
916 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
917 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
919 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
921 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
922 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
925 // Add the instruction to the list.
926 Instructions.push_back(TempInst);
927 // Prepare TempInst for next instruction.
929 // Add temp register to base.
930 TempInst.setOpcode(Mips::ADDu);
931 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
932 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
933 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
934 Instructions.push_back(TempInst);
936 // And finally, create original instruction with low part
937 // of offset and new base.
938 TempInst.setOpcode(Inst.getOpcode());
939 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
940 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
942 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
944 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
945 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
946 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
948 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
950 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
951 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
954 Instructions.push_back(TempInst);
958 bool MipsAsmParser::MatchAndEmitInstruction(
959 SMLoc IDLoc, unsigned &Opcode,
960 SmallVectorImpl<MCParsedAsmOperand *> &Operands, MCStreamer &Out,
961 unsigned &ErrorInfo, bool MatchingInlineAsm) {
963 SmallVector<MCInst, 8> Instructions;
964 unsigned MatchResult =
965 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
967 switch (MatchResult) {
970 case Match_Success: {
971 if (processInstruction(Inst, IDLoc, Instructions))
973 for (unsigned i = 0; i < Instructions.size(); i++)
974 Out.EmitInstruction(Instructions[i], STI);
977 case Match_MissingFeature:
978 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
980 case Match_InvalidOperand: {
981 SMLoc ErrorLoc = IDLoc;
982 if (ErrorInfo != ~0U) {
983 if (ErrorInfo >= Operands.size())
984 return Error(IDLoc, "too few operands for instruction");
986 ErrorLoc = ((MipsOperand *)Operands[ErrorInfo])->getStartLoc();
987 if (ErrorLoc == SMLoc())
991 return Error(ErrorLoc, "invalid operand for instruction");
993 case Match_MnemonicFail:
994 return Error(IDLoc, "invalid instruction");
999 void MipsAsmParser::warnIfAssemblerTemporary(int RegNo) {
1000 if ((RegNo != 0) && ((int)Options.getATRegNum() == RegNo)) {
1002 Warning(getLexer().getLoc(), "Used $at without \".set noat\"");
1004 Warning(getLexer().getLoc(), Twine("Used $") + Twine(RegNo) +
1005 " with \".set at=$" + Twine(RegNo) +
1010 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
1013 CC = StringSwitch<unsigned>(Name)
1049 if (isN32() || isN64()) {
1050 // Although SGI documentation just cuts out t0-t3 for n32/n64,
1051 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
1052 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
1053 if (8 <= CC && CC <= 11)
1057 CC = StringSwitch<unsigned>(Name)
1067 warnIfAssemblerTemporary(CC);
1072 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
1074 if (Name[0] == 'f') {
1075 StringRef NumString = Name.substr(1);
1077 if (NumString.getAsInteger(10, IntVal))
1078 return -1; // This is not an integer.
1079 if (IntVal > 31) // Maximum index for fpu register.
1086 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
1088 if (Name.startswith("fcc")) {
1089 StringRef NumString = Name.substr(3);
1091 if (NumString.getAsInteger(10, IntVal))
1092 return -1; // This is not an integer.
1093 if (IntVal > 7) // There are only 8 fcc registers.
1100 int MipsAsmParser::matchACRegisterName(StringRef Name) {
1102 if (Name.startswith("ac")) {
1103 StringRef NumString = Name.substr(2);
1105 if (NumString.getAsInteger(10, IntVal))
1106 return -1; // This is not an integer.
1107 if (IntVal > 3) // There are only 3 acc registers.
1114 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
1117 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal))
1126 int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) {
1129 CC = StringSwitch<unsigned>(Name)
1132 .Case("msaaccess", 2)
1134 .Case("msamodify", 4)
1135 .Case("msarequest", 5)
1137 .Case("msaunmap", 7)
1143 int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
1146 CC = matchCPURegisterName(Name);
1148 return matchRegisterByNumber(CC, is64BitReg ? Mips::GPR64RegClassID
1149 : Mips::GPR32RegClassID);
1150 CC = matchFPURegisterName(Name);
1151 // TODO: decide about fpu register class
1153 return matchRegisterByNumber(CC, isFP64() ? Mips::FGR64RegClassID
1154 : Mips::FGR32RegClassID);
1155 return matchMSA128RegisterName(Name);
1158 int MipsAsmParser::regKindToRegClass(int RegKind) {
1161 case MipsOperand::Kind_GPR32:
1162 return Mips::GPR32RegClassID;
1163 case MipsOperand::Kind_GPR64:
1164 return Mips::GPR64RegClassID;
1165 case MipsOperand::Kind_HWRegs:
1166 return Mips::HWRegsRegClassID;
1167 case MipsOperand::Kind_FGR32Regs:
1168 return Mips::FGR32RegClassID;
1169 case MipsOperand::Kind_FGRH32Regs:
1170 return Mips::FGRH32RegClassID;
1171 case MipsOperand::Kind_FGR64Regs:
1172 return Mips::FGR64RegClassID;
1173 case MipsOperand::Kind_AFGR64Regs:
1174 return Mips::AFGR64RegClassID;
1175 case MipsOperand::Kind_CCRRegs:
1176 return Mips::CCRRegClassID;
1177 case MipsOperand::Kind_ACC64DSP:
1178 return Mips::ACC64DSPRegClassID;
1179 case MipsOperand::Kind_FCCRegs:
1180 return Mips::FCCRegClassID;
1181 case MipsOperand::Kind_MSA128BRegs:
1182 return Mips::MSA128BRegClassID;
1183 case MipsOperand::Kind_MSA128HRegs:
1184 return Mips::MSA128HRegClassID;
1185 case MipsOperand::Kind_MSA128WRegs:
1186 return Mips::MSA128WRegClassID;
1187 case MipsOperand::Kind_MSA128DRegs:
1188 return Mips::MSA128DRegClassID;
1189 case MipsOperand::Kind_MSA128CtrlRegs:
1190 return Mips::MSACtrlRegClassID;
1196 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
1204 int MipsAsmParser::getATReg() {
1205 int AT = Options.getATRegNum();
1207 TokError("Pseudo instruction requires $at, which is not available");
1211 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
1212 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1215 unsigned MipsAsmParser::getGPR(int RegNo) {
1216 return getReg(isGP64() ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
1220 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
1222 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs() - 1)
1225 if (RegClass == Mips::GPR32RegClassID || RegClass == Mips::GPR64RegClassID)
1226 warnIfAssemblerTemporary(RegNum);
1228 return getReg(RegClass, RegNum);
1231 int MipsAsmParser::tryParseRegister(bool is64BitReg) {
1232 const AsmToken &Tok = Parser.getTok();
1235 if (Tok.is(AsmToken::Identifier)) {
1236 std::string lowerCase = Tok.getString().lower();
1237 RegNum = matchRegisterName(lowerCase, is64BitReg);
1238 } else if (Tok.is(AsmToken::Integer))
1239 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
1240 is64BitReg ? Mips::GPR64RegClassID
1241 : Mips::GPR32RegClassID);
1245 bool MipsAsmParser::tryParseRegisterOperand(
1246 SmallVectorImpl<MCParsedAsmOperand *> &Operands, bool is64BitReg) {
1248 SMLoc S = Parser.getTok().getLoc();
1251 RegNo = tryParseRegister(is64BitReg);
1256 MipsOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1257 Parser.Lex(); // Eat register token.
1262 MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1263 StringRef Mnemonic) {
1264 // Check if the current operand has a custom associated parser, if so, try to
1265 // custom parse the operand, or fallback to the general approach.
1266 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1267 if (ResTy == MatchOperand_Success)
1269 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1270 // there was a match, but an error occurred, in which case, just return that
1271 // the operand parsing failed.
1272 if (ResTy == MatchOperand_ParseFail)
1275 switch (getLexer().getKind()) {
1277 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1279 case AsmToken::Dollar: {
1280 // Parse the register.
1281 SMLoc S = Parser.getTok().getLoc();
1282 Parser.Lex(); // Eat dollar token.
1283 // Parse the register operand.
1284 if (!tryParseRegisterOperand(Operands, isGP64())) {
1285 if (getLexer().is(AsmToken::LParen)) {
1286 // Check if it is indexed addressing operand.
1287 Operands.push_back(MipsOperand::CreateToken("(", S));
1288 Parser.Lex(); // Eat the parenthesis.
1289 if (getLexer().isNot(AsmToken::Dollar))
1292 Parser.Lex(); // Eat the dollar
1293 if (tryParseRegisterOperand(Operands, isGP64()))
1296 if (!getLexer().is(AsmToken::RParen))
1299 S = Parser.getTok().getLoc();
1300 Operands.push_back(MipsOperand::CreateToken(")", S));
1305 // Maybe it is a symbol reference.
1306 StringRef Identifier;
1307 if (Parser.parseIdentifier(Identifier))
1310 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1311 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1312 // Otherwise create a symbol reference.
1314 MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
1316 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
1319 case AsmToken::Identifier:
1320 // For instruction aliases like "bc1f $Label" dedicated parser will
1321 // eat the '$' sign before failing. So in order to look for appropriate
1322 // label we must check first if we have already consumed '$'.
1323 if (hasConsumedDollar) {
1324 hasConsumedDollar = false;
1325 SMLoc S = Parser.getTok().getLoc();
1326 StringRef Identifier;
1327 if (Parser.parseIdentifier(Identifier))
1330 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1331 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1332 // Create a symbol reference.
1334 MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
1336 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
1339 // Look for the existing symbol, we should check if
1340 // we need to assign the proper RegisterKind.
1341 if (searchSymbolAlias(Operands, MipsOperand::Kind_None))
1343 // Else drop to expression parsing.
1344 case AsmToken::LParen:
1345 case AsmToken::Minus:
1346 case AsmToken::Plus:
1347 case AsmToken::Integer:
1348 case AsmToken::String: {
1349 // Quoted label names.
1350 const MCExpr *IdVal;
1351 SMLoc S = Parser.getTok().getLoc();
1352 if (getParser().parseExpression(IdVal))
1354 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1355 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1358 case AsmToken::Percent: {
1359 // It is a symbol reference or constant expression.
1360 const MCExpr *IdVal;
1361 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1362 if (parseRelocOperand(IdVal))
1365 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1367 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1369 } // case AsmToken::Percent
1370 } // switch(getLexer().getKind())
1374 const MCExpr *MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1375 StringRef RelocStr) {
1377 // Check the type of the expression.
1378 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1379 // It's a constant, evaluate lo or hi value.
1380 if (RelocStr == "lo") {
1381 short Val = MCE->getValue();
1382 Res = MCConstantExpr::Create(Val, getContext());
1383 } else if (RelocStr == "hi") {
1384 int Val = MCE->getValue();
1385 int LoSign = Val & 0x8000;
1386 Val = (Val & 0xffff0000) >> 16;
1387 // Lower part is treated as a signed int, so if it is negative
1388 // we must add 1 to the hi part to compensate.
1391 Res = MCConstantExpr::Create(Val, getContext());
1393 llvm_unreachable("Invalid RelocStr value");
1398 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1399 // It's a symbol, create a symbolic expression from the symbol.
1400 StringRef Symbol = MSRE->getSymbol().getName();
1401 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1402 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1406 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1407 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1409 // Check for %hi(sym1-sym2) and %lo(sym1-sym2) expressions.
1410 if (isa<MCSymbolRefExpr>(BE->getLHS()) && isa<MCSymbolRefExpr>(BE->getRHS())
1411 && (VK == MCSymbolRefExpr::VK_Mips_ABS_HI
1412 || VK == MCSymbolRefExpr::VK_Mips_ABS_LO)) {
1413 // Create target expression for %hi(sym1-sym2) and %lo(sym1-sym2).
1414 if (VK == MCSymbolRefExpr::VK_Mips_ABS_HI)
1415 return MipsMCExpr::CreateHi(Expr, getContext());
1416 return MipsMCExpr::CreateLo(Expr, getContext());
1419 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1420 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1421 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1425 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1426 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1427 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1430 // Just return the original expression.
1434 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1436 switch (Expr->getKind()) {
1437 case MCExpr::Constant:
1439 case MCExpr::SymbolRef:
1440 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1441 case MCExpr::Binary:
1442 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1443 if (!isEvaluated(BE->getLHS()))
1445 return isEvaluated(BE->getRHS());
1448 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1449 case MCExpr::Target:
1455 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1456 Parser.Lex(); // Eat the % token.
1457 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1458 if (Tok.isNot(AsmToken::Identifier))
1461 std::string Str = Tok.getIdentifier().str();
1463 Parser.Lex(); // Eat the identifier.
1464 // Now make an expression from the rest of the operand.
1465 const MCExpr *IdVal;
1468 if (getLexer().getKind() == AsmToken::LParen) {
1470 Parser.Lex(); // Eat the '(' token.
1471 if (getLexer().getKind() == AsmToken::Percent) {
1472 Parser.Lex(); // Eat the % token.
1473 const AsmToken &nextTok = Parser.getTok();
1474 if (nextTok.isNot(AsmToken::Identifier))
1477 Str += nextTok.getIdentifier();
1478 Parser.Lex(); // Eat the identifier.
1479 if (getLexer().getKind() != AsmToken::LParen)
1484 if (getParser().parseParenExpression(IdVal, EndLoc))
1487 while (getLexer().getKind() == AsmToken::RParen)
1488 Parser.Lex(); // Eat the ')' token.
1491 return true; // Parenthesis must follow the relocation operand.
1493 Res = evaluateRelocExpr(IdVal, Str);
1497 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1499 StartLoc = Parser.getTok().getLoc();
1500 RegNo = tryParseRegister(isGP64());
1501 EndLoc = Parser.getTok().getLoc();
1502 return (RegNo == (unsigned)-1);
1505 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1509 while (getLexer().getKind() == AsmToken::LParen)
1512 switch (getLexer().getKind()) {
1515 case AsmToken::Identifier:
1516 case AsmToken::LParen:
1517 case AsmToken::Integer:
1518 case AsmToken::Minus:
1519 case AsmToken::Plus:
1521 Result = getParser().parseParenExpression(Res, S);
1523 Result = (getParser().parseExpression(Res));
1524 while (getLexer().getKind() == AsmToken::RParen)
1527 case AsmToken::Percent:
1528 Result = parseRelocOperand(Res);
1533 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1534 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1536 const MCExpr *IdVal = 0;
1538 bool isParenExpr = false;
1539 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1540 // First operand is the offset.
1541 S = Parser.getTok().getLoc();
1543 if (getLexer().getKind() == AsmToken::LParen) {
1548 if (getLexer().getKind() != AsmToken::Dollar) {
1549 if (parseMemOffset(IdVal, isParenExpr))
1550 return MatchOperand_ParseFail;
1552 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1553 if (Tok.isNot(AsmToken::LParen)) {
1554 MipsOperand *Mnemonic = static_cast<MipsOperand *>(Operands[0]);
1555 if (Mnemonic->getToken() == "la") {
1557 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1558 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1559 return MatchOperand_Success;
1561 if (Tok.is(AsmToken::EndOfStatement)) {
1563 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1565 // Zero register assumed, add a memory operand with ZERO as its base.
1566 Operands.push_back(MipsOperand::CreateMem(
1567 isGP64() ? Mips::ZERO_64 : Mips::ZERO, IdVal, S, E));
1568 return MatchOperand_Success;
1570 Error(Parser.getTok().getLoc(), "'(' expected");
1571 return MatchOperand_ParseFail;
1574 Parser.Lex(); // Eat the '(' token.
1577 Res = parseRegs(Operands, isGP64() ? (int)MipsOperand::Kind_GPR64
1578 : (int)MipsOperand::Kind_GPR32);
1579 if (Res != MatchOperand_Success)
1582 if (Parser.getTok().isNot(AsmToken::RParen)) {
1583 Error(Parser.getTok().getLoc(), "')' expected");
1584 return MatchOperand_ParseFail;
1587 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1589 Parser.Lex(); // Eat the ')' token.
1592 IdVal = MCConstantExpr::Create(0, getContext());
1594 // Replace the register operand with the memory operand.
1595 MipsOperand *op = static_cast<MipsOperand *>(Operands.back());
1596 int RegNo = op->getReg();
1597 // Remove the register from the operands.
1598 Operands.pop_back();
1599 // Add the memory operand.
1600 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1602 if (IdVal->EvaluateAsAbsolute(Imm))
1603 IdVal = MCConstantExpr::Create(Imm, getContext());
1604 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1605 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1609 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
1611 return MatchOperand_Success;
1614 bool MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1616 // If the first token is not '$' we have an error.
1617 if (Parser.getTok().isNot(AsmToken::Dollar))
1620 SMLoc S = Parser.getTok().getLoc();
1622 AsmToken::TokenKind TkKind = getLexer().getKind();
1625 if (TkKind == AsmToken::Integer) {
1626 Reg = matchRegisterByNumber(Parser.getTok().getIntVal(),
1627 regKindToRegClass(RegKind));
1630 } else if (TkKind == AsmToken::Identifier) {
1631 if ((Reg = matchCPURegisterName(Parser.getTok().getString().lower())) == -1)
1633 Reg = getReg(regKindToRegClass(RegKind), Reg);
1638 MipsOperand *Op = MipsOperand::CreatePtrReg(Reg, S, Parser.getTok().getLoc());
1639 Op->setRegKind((MipsOperand::RegisterKind)RegKind);
1640 Operands.push_back(Op);
1645 MipsAsmParser::OperandMatchResultTy
1646 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1647 MipsOperand::RegisterKind RegKind =
1648 isN64() ? MipsOperand::Kind_GPR64 : MipsOperand::Kind_GPR32;
1650 // Parse index register.
1651 if (!parsePtrReg(Operands, RegKind))
1652 return MatchOperand_NoMatch;
1655 if (Parser.getTok().isNot(AsmToken::LParen))
1656 return MatchOperand_NoMatch;
1658 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1661 // Parse base register.
1662 if (!parsePtrReg(Operands, RegKind))
1663 return MatchOperand_NoMatch;
1666 if (Parser.getTok().isNot(AsmToken::RParen))
1667 return MatchOperand_NoMatch;
1669 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1672 return MatchOperand_Success;
1675 MipsAsmParser::OperandMatchResultTy
1676 MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1678 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1679 if (getLexer().getKind() == AsmToken::Identifier && !hasConsumedDollar) {
1680 if (searchSymbolAlias(Operands, Kind))
1681 return MatchOperand_Success;
1682 return MatchOperand_NoMatch;
1684 SMLoc S = Parser.getTok().getLoc();
1685 // If the first token is not '$', we have an error.
1686 if (Parser.getTok().isNot(AsmToken::Dollar) && !hasConsumedDollar)
1687 return MatchOperand_NoMatch;
1688 if (!hasConsumedDollar) {
1689 Parser.Lex(); // Eat the '$'
1690 hasConsumedDollar = true;
1692 if (getLexer().getKind() == AsmToken::Identifier) {
1694 std::string RegName = Parser.getTok().getString().lower();
1695 // Match register by name
1697 case MipsOperand::Kind_GPR32:
1698 case MipsOperand::Kind_GPR64:
1699 RegNum = matchCPURegisterName(RegName);
1701 case MipsOperand::Kind_AFGR64Regs:
1702 case MipsOperand::Kind_FGR64Regs:
1703 case MipsOperand::Kind_FGR32Regs:
1704 case MipsOperand::Kind_FGRH32Regs:
1705 RegNum = matchFPURegisterName(RegName);
1706 if (RegKind == MipsOperand::Kind_AFGR64Regs)
1708 else if (RegKind == MipsOperand::Kind_FGRH32Regs && !isFP64())
1709 if (RegNum != -1 && RegNum % 2 != 0)
1710 Warning(S, "Float register should be even.");
1712 case MipsOperand::Kind_FCCRegs:
1713 RegNum = matchFCCRegisterName(RegName);
1715 case MipsOperand::Kind_ACC64DSP:
1716 RegNum = matchACRegisterName(RegName);
1719 break; // No match, value is set to -1.
1721 // No match found, return _NoMatch to give a chance to other round.
1723 return MatchOperand_NoMatch;
1725 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1727 return MatchOperand_NoMatch;
1730 MipsOperand::CreateReg(RegVal, S, Parser.getTok().getLoc());
1731 Op->setRegKind(Kind);
1732 Operands.push_back(Op);
1733 hasConsumedDollar = false;
1734 Parser.Lex(); // Eat the register name.
1735 return MatchOperand_Success;
1736 } else if (getLexer().getKind() == AsmToken::Integer) {
1737 unsigned RegNum = Parser.getTok().getIntVal();
1738 if (Kind == MipsOperand::Kind_HWRegs) {
1740 return MatchOperand_NoMatch;
1741 // Only hwreg 29 is supported, found at index 0.
1744 int Reg = matchRegisterByNumber(RegNum, regKindToRegClass(Kind));
1746 return MatchOperand_NoMatch;
1747 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1748 Op->setRegKind(Kind);
1749 Operands.push_back(Op);
1750 hasConsumedDollar = false;
1751 Parser.Lex(); // Eat the register number.
1752 if ((RegKind == MipsOperand::Kind_GPR32) &&
1753 (getLexer().is(AsmToken::LParen))) {
1754 // Check if it is indexed addressing operand.
1755 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1756 Parser.Lex(); // Eat the parenthesis.
1757 if (parseRegs(Operands, RegKind) != MatchOperand_Success)
1758 return MatchOperand_NoMatch;
1759 if (getLexer().isNot(AsmToken::RParen))
1760 return MatchOperand_NoMatch;
1761 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1764 return MatchOperand_Success;
1766 return MatchOperand_NoMatch;
1769 bool MipsAsmParser::validateMSAIndex(int Val, int RegKind) {
1770 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1778 case MipsOperand::Kind_MSA128BRegs:
1780 case MipsOperand::Kind_MSA128HRegs:
1782 case MipsOperand::Kind_MSA128WRegs:
1784 case MipsOperand::Kind_MSA128DRegs:
1789 MipsAsmParser::OperandMatchResultTy
1790 MipsAsmParser::parseMSARegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1792 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1793 SMLoc S = Parser.getTok().getLoc();
1794 std::string RegName;
1796 if (Parser.getTok().isNot(AsmToken::Dollar))
1797 return MatchOperand_NoMatch;
1801 return MatchOperand_ParseFail;
1802 case MipsOperand::Kind_MSA128BRegs:
1803 case MipsOperand::Kind_MSA128HRegs:
1804 case MipsOperand::Kind_MSA128WRegs:
1805 case MipsOperand::Kind_MSA128DRegs:
1809 Parser.Lex(); // Eat the '$'.
1810 if (getLexer().getKind() == AsmToken::Identifier)
1811 RegName = Parser.getTok().getString().lower();
1813 return MatchOperand_ParseFail;
1815 int RegNum = matchMSA128RegisterName(RegName);
1817 if (RegNum < 0 || RegNum > 31)
1818 return MatchOperand_ParseFail;
1820 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1822 return MatchOperand_ParseFail;
1824 MipsOperand *Op = MipsOperand::CreateReg(RegVal, S, Parser.getTok().getLoc());
1825 Op->setRegKind(Kind);
1826 Operands.push_back(Op);
1828 Parser.Lex(); // Eat the register identifier.
1830 // MSA registers may be suffixed with an index in the form of:
1831 // 1) Immediate expression.
1832 // 2) General Purpose Register.
1834 // 1) copy_s.b $29,$w0[0]
1835 // 2) sld.b $w0,$w1[$1]
1837 if (Parser.getTok().isNot(AsmToken::LBrac))
1838 return MatchOperand_Success;
1840 MipsOperand *Mnemonic = static_cast<MipsOperand *>(Operands[0]);
1842 Operands.push_back(MipsOperand::CreateToken("[", Parser.getTok().getLoc()));
1843 Parser.Lex(); // Parse the '[' token.
1845 if (Parser.getTok().is(AsmToken::Dollar)) {
1846 // This must be a GPR.
1848 SMLoc VIdx = Parser.getTok().getLoc();
1849 Parser.Lex(); // Parse the '$' token.
1851 // GPR have aliases and we must account for that. Example: $30 == $fp
1852 if (getLexer().getKind() == AsmToken::Integer) {
1853 unsigned RegNum = Parser.getTok().getIntVal();
1854 int Reg = matchRegisterByNumber(
1855 RegNum, regKindToRegClass(MipsOperand::Kind_GPR32));
1857 Error(VIdx, "invalid general purpose register");
1858 return MatchOperand_ParseFail;
1861 RegOp = MipsOperand::CreateReg(Reg, VIdx, Parser.getTok().getLoc());
1862 } else if (getLexer().getKind() == AsmToken::Identifier) {
1864 std::string RegName = Parser.getTok().getString().lower();
1866 RegNum = matchCPURegisterName(RegName);
1868 Error(VIdx, "general purpose register expected");
1869 return MatchOperand_ParseFail;
1871 RegNum = getReg(regKindToRegClass(MipsOperand::Kind_GPR32), RegNum);
1872 RegOp = MipsOperand::CreateReg(RegNum, VIdx, Parser.getTok().getLoc());
1874 return MatchOperand_ParseFail;
1876 RegOp->setRegKind(MipsOperand::Kind_GPR32);
1877 Operands.push_back(RegOp);
1878 Parser.Lex(); // Eat the register identifier.
1880 if (Parser.getTok().isNot(AsmToken::RBrac))
1881 return MatchOperand_ParseFail;
1883 Operands.push_back(MipsOperand::CreateToken("]", Parser.getTok().getLoc()));
1884 Parser.Lex(); // Parse the ']' token.
1886 return MatchOperand_Success;
1889 // The index must be a constant expression then.
1890 SMLoc VIdx = Parser.getTok().getLoc();
1891 const MCExpr *ImmVal;
1893 if (getParser().parseExpression(ImmVal))
1894 return MatchOperand_ParseFail;
1896 const MCConstantExpr *expr = dyn_cast<MCConstantExpr>(ImmVal);
1897 if (!expr || !validateMSAIndex((int)expr->getValue(), Kind)) {
1898 Error(VIdx, "invalid immediate value");
1899 return MatchOperand_ParseFail;
1902 SMLoc E = Parser.getTok().getEndLoc();
1904 if (Parser.getTok().isNot(AsmToken::RBrac))
1905 return MatchOperand_ParseFail;
1908 Mnemonic->getToken() == "insve.b" || Mnemonic->getToken() == "insve.h" ||
1909 Mnemonic->getToken() == "insve.w" || Mnemonic->getToken() == "insve.d";
1911 // The second vector index of insve instructions is always 0.
1912 if (insve && Operands.size() > 6) {
1913 if (expr->getValue() != 0) {
1914 Error(VIdx, "immediate value must be 0");
1915 return MatchOperand_ParseFail;
1917 Operands.push_back(MipsOperand::CreateToken("0", VIdx));
1919 Operands.push_back(MipsOperand::CreateImm(expr, VIdx, E));
1921 Operands.push_back(MipsOperand::CreateToken("]", Parser.getTok().getLoc()));
1923 Parser.Lex(); // Parse the ']' token.
1925 return MatchOperand_Success;
1928 MipsAsmParser::OperandMatchResultTy
1929 MipsAsmParser::parseMSACtrlRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1931 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1933 if (Kind != MipsOperand::Kind_MSA128CtrlRegs)
1934 return MatchOperand_NoMatch;
1936 if (Parser.getTok().isNot(AsmToken::Dollar))
1937 return MatchOperand_ParseFail;
1939 SMLoc S = Parser.getTok().getLoc();
1941 Parser.Lex(); // Eat the '$' symbol.
1944 if (getLexer().getKind() == AsmToken::Identifier)
1945 RegNum = matchMSA128CtrlRegisterName(Parser.getTok().getString().lower());
1946 else if (getLexer().getKind() == AsmToken::Integer)
1947 RegNum = Parser.getTok().getIntVal();
1949 return MatchOperand_ParseFail;
1951 if (RegNum < 0 || RegNum > 7)
1952 return MatchOperand_ParseFail;
1954 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1956 return MatchOperand_ParseFail;
1958 MipsOperand *RegOp =
1959 MipsOperand::CreateReg(RegVal, S, Parser.getTok().getLoc());
1960 RegOp->setRegKind(MipsOperand::Kind_MSA128CtrlRegs);
1961 Operands.push_back(RegOp);
1962 Parser.Lex(); // Eat the register identifier.
1964 return MatchOperand_Success;
1967 MipsAsmParser::OperandMatchResultTy
1968 MipsAsmParser::parseGPR64(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1971 return MatchOperand_NoMatch;
1972 return parseRegs(Operands, (int)MipsOperand::Kind_GPR64);
1975 MipsAsmParser::OperandMatchResultTy
1976 MipsAsmParser::parseGPR32(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1977 return parseRegs(Operands, (int)MipsOperand::Kind_GPR32);
1980 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseAFGR64Regs(
1981 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1984 return MatchOperand_NoMatch;
1985 return parseRegs(Operands, (int)MipsOperand::Kind_AFGR64Regs);
1988 MipsAsmParser::OperandMatchResultTy
1989 MipsAsmParser::parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1991 return MatchOperand_NoMatch;
1992 return parseRegs(Operands, (int)MipsOperand::Kind_FGR64Regs);
1995 MipsAsmParser::OperandMatchResultTy
1996 MipsAsmParser::parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1997 return parseRegs(Operands, (int)MipsOperand::Kind_FGR32Regs);
2000 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseFGRH32Regs(
2001 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2002 return parseRegs(Operands, (int)MipsOperand::Kind_FGRH32Regs);
2005 MipsAsmParser::OperandMatchResultTy
2006 MipsAsmParser::parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2007 return parseRegs(Operands, (int)MipsOperand::Kind_FCCRegs);
2010 MipsAsmParser::OperandMatchResultTy
2011 MipsAsmParser::parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2012 return parseRegs(Operands, (int)MipsOperand::Kind_ACC64DSP);
2015 MipsAsmParser::OperandMatchResultTy
2016 MipsAsmParser::parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2017 // If the first token is not '$' we have an error.
2018 if (Parser.getTok().isNot(AsmToken::Dollar))
2019 return MatchOperand_NoMatch;
2021 SMLoc S = Parser.getTok().getLoc();
2022 Parser.Lex(); // Eat the '$'
2024 const AsmToken &Tok = Parser.getTok(); // Get next token.
2026 if (Tok.isNot(AsmToken::Identifier))
2027 return MatchOperand_NoMatch;
2029 if (!Tok.getIdentifier().startswith("ac"))
2030 return MatchOperand_NoMatch;
2032 StringRef NumString = Tok.getIdentifier().substr(2);
2035 if (NumString.getAsInteger(10, IntVal))
2036 return MatchOperand_NoMatch;
2038 unsigned Reg = matchRegisterByNumber(IntVal, Mips::LO32DSPRegClassID);
2040 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
2041 Op->setRegKind(MipsOperand::Kind_LO32DSP);
2042 Operands.push_back(Op);
2044 Parser.Lex(); // Eat the register number.
2045 return MatchOperand_Success;
2048 MipsAsmParser::OperandMatchResultTy
2049 MipsAsmParser::parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2050 // If the first token is not '$' we have an error.
2051 if (Parser.getTok().isNot(AsmToken::Dollar))
2052 return MatchOperand_NoMatch;
2054 SMLoc S = Parser.getTok().getLoc();
2055 Parser.Lex(); // Eat the '$'
2057 const AsmToken &Tok = Parser.getTok(); // Get next token.
2059 if (Tok.isNot(AsmToken::Identifier))
2060 return MatchOperand_NoMatch;
2062 if (!Tok.getIdentifier().startswith("ac"))
2063 return MatchOperand_NoMatch;
2065 StringRef NumString = Tok.getIdentifier().substr(2);
2068 if (NumString.getAsInteger(10, IntVal))
2069 return MatchOperand_NoMatch;
2071 unsigned Reg = matchRegisterByNumber(IntVal, Mips::HI32DSPRegClassID);
2073 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
2074 Op->setRegKind(MipsOperand::Kind_HI32DSP);
2075 Operands.push_back(Op);
2077 Parser.Lex(); // Eat the register number.
2078 return MatchOperand_Success;
2081 MipsAsmParser::OperandMatchResultTy
2082 MipsAsmParser::parseCOP2(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2083 // If the first token is not '$' we have an error.
2084 if (Parser.getTok().isNot(AsmToken::Dollar))
2085 return MatchOperand_NoMatch;
2087 SMLoc S = Parser.getTok().getLoc();
2088 Parser.Lex(); // Eat the '$'
2090 const AsmToken &Tok = Parser.getTok(); // Get next token.
2092 if (Tok.isNot(AsmToken::Integer))
2093 return MatchOperand_NoMatch;
2095 unsigned IntVal = Tok.getIntVal();
2097 unsigned Reg = matchRegisterByNumber(IntVal, Mips::COP2RegClassID);
2099 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
2100 Op->setRegKind(MipsOperand::Kind_COP2);
2101 Operands.push_back(Op);
2103 Parser.Lex(); // Eat the register number.
2104 return MatchOperand_Success;
2107 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128BRegs(
2108 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2109 return parseMSARegs(Operands, (int)MipsOperand::Kind_MSA128BRegs);
2112 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128HRegs(
2113 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2114 return parseMSARegs(Operands, (int)MipsOperand::Kind_MSA128HRegs);
2117 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128WRegs(
2118 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2119 return parseMSARegs(Operands, (int)MipsOperand::Kind_MSA128WRegs);
2122 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128DRegs(
2123 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2124 return parseMSARegs(Operands, (int)MipsOperand::Kind_MSA128DRegs);
2127 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128CtrlRegs(
2128 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2129 return parseMSACtrlRegs(Operands, (int)MipsOperand::Kind_MSA128CtrlRegs);
2132 bool MipsAsmParser::searchSymbolAlias(
2133 SmallVectorImpl<MCParsedAsmOperand *> &Operands, unsigned RegKind) {
2135 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
2137 SMLoc S = Parser.getTok().getLoc();
2139 if (Sym->isVariable())
2140 Expr = Sym->getVariableValue();
2143 if (Expr->getKind() == MCExpr::SymbolRef) {
2144 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
2145 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
2146 const StringRef DefSymbol = Ref->getSymbol().getName();
2147 if (DefSymbol.startswith("$")) {
2149 APInt IntVal(32, -1);
2150 if (!DefSymbol.substr(1).getAsInteger(10, IntVal))
2151 RegNum = matchRegisterByNumber(IntVal.getZExtValue(),
2152 isGP64() ? Mips::GPR64RegClassID
2153 : Mips::GPR32RegClassID);
2155 // Lookup for the register with the corresponding name.
2157 case MipsOperand::Kind_AFGR64Regs:
2158 case MipsOperand::Kind_FGR64Regs:
2159 RegNum = matchFPURegisterName(DefSymbol.substr(1));
2161 case MipsOperand::Kind_FGR32Regs:
2162 RegNum = matchFPURegisterName(DefSymbol.substr(1));
2164 case MipsOperand::Kind_GPR64:
2165 case MipsOperand::Kind_GPR32:
2167 RegNum = matchCPURegisterName(DefSymbol.substr(1));
2171 RegNum = getReg(regKindToRegClass(Kind), RegNum);
2176 MipsOperand::CreateReg(RegNum, S, Parser.getTok().getLoc());
2177 op->setRegKind(Kind);
2178 Operands.push_back(op);
2182 } else if (Expr->getKind() == MCExpr::Constant) {
2184 const MCConstantExpr *Const = static_cast<const MCConstantExpr *>(Expr);
2186 MipsOperand::CreateImm(Const, S, Parser.getTok().getLoc());
2187 Operands.push_back(op);
2194 MipsAsmParser::OperandMatchResultTy
2195 MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2196 return parseRegs(Operands, (int)MipsOperand::Kind_HWRegs);
2199 MipsAsmParser::OperandMatchResultTy
2200 MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2201 return parseRegs(Operands, (int)MipsOperand::Kind_CCRRegs);
2204 MipsAsmParser::OperandMatchResultTy
2205 MipsAsmParser::parseInvNum(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2206 const MCExpr *IdVal;
2207 // If the first token is '$' we may have register operand.
2208 if (Parser.getTok().is(AsmToken::Dollar))
2209 return MatchOperand_NoMatch;
2210 SMLoc S = Parser.getTok().getLoc();
2211 if (getParser().parseExpression(IdVal))
2212 return MatchOperand_ParseFail;
2213 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
2214 assert(MCE && "Unexpected MCExpr type.");
2215 int64_t Val = MCE->getValue();
2216 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2217 Operands.push_back(MipsOperand::CreateImm(
2218 MCConstantExpr::Create(0 - Val, getContext()), S, E));
2219 return MatchOperand_Success;
2222 MipsAsmParser::OperandMatchResultTy
2223 MipsAsmParser::parseLSAImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2224 switch (getLexer().getKind()) {
2226 return MatchOperand_NoMatch;
2227 case AsmToken::LParen:
2228 case AsmToken::Plus:
2229 case AsmToken::Minus:
2230 case AsmToken::Integer:
2235 SMLoc S = Parser.getTok().getLoc();
2237 if (getParser().parseExpression(Expr))
2238 return MatchOperand_ParseFail;
2241 if (!Expr->EvaluateAsAbsolute(Val)) {
2242 Error(S, "expected immediate value");
2243 return MatchOperand_ParseFail;
2246 // The LSA instruction allows a 2-bit unsigned immediate. For this reason
2247 // and because the CPU always adds one to the immediate field, the allowed
2248 // range becomes 1..4. We'll only check the range here and will deal
2249 // with the addition/subtraction when actually decoding/encoding
2251 if (Val < 1 || Val > 4) {
2252 Error(S, "immediate not in range (1..4)");
2253 return MatchOperand_ParseFail;
2257 MipsOperand::CreateLSAImm(Expr, S, Parser.getTok().getLoc()));
2258 return MatchOperand_Success;
2261 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
2263 MCSymbolRefExpr::VariantKind VK =
2264 StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
2265 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
2266 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
2267 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
2268 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
2269 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
2270 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
2271 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
2272 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
2273 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
2274 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
2275 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
2276 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
2277 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
2278 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
2279 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
2280 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
2281 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
2282 .Case("got_hi", MCSymbolRefExpr::VK_Mips_GOT_HI16)
2283 .Case("got_lo", MCSymbolRefExpr::VK_Mips_GOT_LO16)
2284 .Case("call_hi", MCSymbolRefExpr::VK_Mips_CALL_HI16)
2285 .Case("call_lo", MCSymbolRefExpr::VK_Mips_CALL_LO16)
2286 .Case("higher", MCSymbolRefExpr::VK_Mips_HIGHER)
2287 .Case("highest", MCSymbolRefExpr::VK_Mips_HIGHEST)
2288 .Default(MCSymbolRefExpr::VK_None);
2290 assert (VK != MCSymbolRefExpr::VK_None);
2295 bool MipsAsmParser::ParseInstruction(
2296 ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
2297 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2298 // Check if we have valid mnemonic
2299 if (!mnemonicIsValid(Name, 0)) {
2300 Parser.eatToEndOfStatement();
2301 return Error(NameLoc, "Unknown instruction");
2303 // First operand in MCInst is instruction mnemonic.
2304 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
2306 // Read the remaining operands.
2307 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2308 // Read the first operand.
2309 if (ParseOperand(Operands, Name)) {
2310 SMLoc Loc = getLexer().getLoc();
2311 Parser.eatToEndOfStatement();
2312 return Error(Loc, "unexpected token in argument list");
2315 while (getLexer().is(AsmToken::Comma)) {
2316 Parser.Lex(); // Eat the comma.
2317 // Parse and remember the operand.
2318 if (ParseOperand(Operands, Name)) {
2319 SMLoc Loc = getLexer().getLoc();
2320 Parser.eatToEndOfStatement();
2321 return Error(Loc, "unexpected token in argument list");
2325 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2326 SMLoc Loc = getLexer().getLoc();
2327 Parser.eatToEndOfStatement();
2328 return Error(Loc, "unexpected token in argument list");
2330 Parser.Lex(); // Consume the EndOfStatement.
2334 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
2335 SMLoc Loc = getLexer().getLoc();
2336 Parser.eatToEndOfStatement();
2337 return Error(Loc, ErrorMsg);
2340 bool MipsAsmParser::parseSetNoAtDirective() {
2341 // Line should look like: ".set noat".
2343 Options.setATReg(0);
2346 // If this is not the end of the statement, report an error.
2347 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2348 reportParseError("unexpected token in statement");
2351 Parser.Lex(); // Consume the EndOfStatement.
2355 bool MipsAsmParser::parseSetAtDirective() {
2356 // Line can be .set at - defaults to $1
2360 if (getLexer().is(AsmToken::EndOfStatement)) {
2361 Options.setATReg(1);
2362 Parser.Lex(); // Consume the EndOfStatement.
2364 } else if (getLexer().is(AsmToken::Equal)) {
2365 getParser().Lex(); // Eat the '='.
2366 if (getLexer().isNot(AsmToken::Dollar)) {
2367 reportParseError("unexpected token in statement");
2370 Parser.Lex(); // Eat the '$'.
2371 const AsmToken &Reg = Parser.getTok();
2372 if (Reg.is(AsmToken::Identifier)) {
2373 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
2374 } else if (Reg.is(AsmToken::Integer)) {
2375 AtRegNo = Reg.getIntVal();
2377 reportParseError("unexpected token in statement");
2381 if (AtRegNo < 0 || AtRegNo > 31) {
2382 reportParseError("unexpected token in statement");
2386 if (!Options.setATReg(AtRegNo)) {
2387 reportParseError("unexpected token in statement");
2390 getParser().Lex(); // Eat the register.
2392 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2393 reportParseError("unexpected token in statement");
2396 Parser.Lex(); // Consume the EndOfStatement.
2399 reportParseError("unexpected token in statement");
2404 bool MipsAsmParser::parseSetReorderDirective() {
2406 // If this is not the end of the statement, report an error.
2407 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2408 reportParseError("unexpected token in statement");
2411 Options.setReorder();
2412 getTargetStreamer().emitDirectiveSetReorder();
2413 Parser.Lex(); // Consume the EndOfStatement.
2417 bool MipsAsmParser::parseSetNoReorderDirective() {
2419 // If this is not the end of the statement, report an error.
2420 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2421 reportParseError("unexpected token in statement");
2424 Options.setNoreorder();
2425 getTargetStreamer().emitDirectiveSetNoReorder();
2426 Parser.Lex(); // Consume the EndOfStatement.
2430 bool MipsAsmParser::parseSetMacroDirective() {
2432 // If this is not the end of the statement, report an error.
2433 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2434 reportParseError("unexpected token in statement");
2438 Parser.Lex(); // Consume the EndOfStatement.
2442 bool MipsAsmParser::parseSetNoMacroDirective() {
2444 // If this is not the end of the statement, report an error.
2445 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2446 reportParseError("`noreorder' must be set before `nomacro'");
2449 if (Options.isReorder()) {
2450 reportParseError("`noreorder' must be set before `nomacro'");
2453 Options.setNomacro();
2454 Parser.Lex(); // Consume the EndOfStatement.
2458 bool MipsAsmParser::parseSetNoMips16Directive() {
2460 // If this is not the end of the statement, report an error.
2461 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2462 reportParseError("unexpected token in statement");
2465 // For now do nothing.
2466 Parser.Lex(); // Consume the EndOfStatement.
2470 bool MipsAsmParser::parseSetAssignment() {
2472 const MCExpr *Value;
2474 if (Parser.parseIdentifier(Name))
2475 reportParseError("expected identifier after .set");
2477 if (getLexer().isNot(AsmToken::Comma))
2478 return reportParseError("unexpected token in .set directive");
2481 if (Parser.parseExpression(Value))
2482 return reportParseError("expected valid expression after comma");
2484 // Check if the Name already exists as a symbol.
2485 MCSymbol *Sym = getContext().LookupSymbol(Name);
2487 return reportParseError("symbol already defined");
2488 Sym = getContext().GetOrCreateSymbol(Name);
2489 Sym->setVariableValue(Value);
2494 bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
2496 if (getLexer().isNot(AsmToken::EndOfStatement))
2497 return reportParseError("unexpected token in .set directive");
2500 default: llvm_unreachable("Unimplemented feature");
2501 case Mips::FeatureDSP:
2502 setFeatureBits(Mips::FeatureDSP, "dsp");
2503 getTargetStreamer().emitDirectiveSetDsp();
2505 case Mips::FeatureMicroMips:
2506 getTargetStreamer().emitDirectiveSetMicroMips();
2508 case Mips::FeatureMips16:
2509 getTargetStreamer().emitDirectiveSetMips16();
2511 case Mips::FeatureMips32r2:
2512 setFeatureBits(Mips::FeatureMips32r2, "mips32r2");
2513 getTargetStreamer().emitDirectiveSetMips32R2();
2515 case Mips::FeatureMips64:
2516 setFeatureBits(Mips::FeatureMips64, "mips64");
2517 getTargetStreamer().emitDirectiveSetMips64();
2519 case Mips::FeatureMips64r2:
2520 setFeatureBits(Mips::FeatureMips64r2, "mips64r2");
2521 getTargetStreamer().emitDirectiveSetMips64R2();
2527 bool MipsAsmParser::parseRegister(unsigned &RegNum) {
2528 if (!getLexer().is(AsmToken::Dollar))
2533 const AsmToken &Reg = Parser.getTok();
2534 if (Reg.is(AsmToken::Identifier)) {
2535 RegNum = matchCPURegisterName(Reg.getIdentifier());
2536 } else if (Reg.is(AsmToken::Integer)) {
2537 RegNum = Reg.getIntVal();
2546 bool MipsAsmParser::eatComma(StringRef ErrorStr) {
2547 if (getLexer().isNot(AsmToken::Comma)) {
2548 SMLoc Loc = getLexer().getLoc();
2549 Parser.eatToEndOfStatement();
2550 return Error(Loc, ErrorStr);
2553 Parser.Lex(); // Eat the comma.
2557 bool MipsAsmParser::parseDirectiveCPSetup() {
2560 bool SaveIsReg = true;
2562 if (!parseRegister(FuncReg))
2563 return reportParseError("expected register containing function address");
2564 FuncReg = getGPR(FuncReg);
2566 if (!eatComma("expected comma parsing directive"))
2569 if (!parseRegister(Save)) {
2570 const AsmToken &Tok = Parser.getTok();
2571 if (Tok.is(AsmToken::Integer)) {
2572 Save = Tok.getIntVal();
2576 return reportParseError("expected save register or stack offset");
2578 Save = getGPR(Save);
2580 if (!eatComma("expected comma parsing directive"))
2584 if (Parser.parseIdentifier(Name))
2585 reportParseError("expected identifier");
2586 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
2587 unsigned GPReg = getGPR(matchCPURegisterName("gp"));
2589 // FIXME: The code below this point should be in the TargetStreamers.
2590 // Only N32 and N64 emit anything for .cpsetup
2591 // FIXME: We should only emit something for PIC mode too.
2592 if (!isN32() && !isN64())
2595 MCStreamer &TS = getStreamer();
2597 // Either store the old $gp in a register or on the stack
2599 // move $save, $gpreg
2600 Inst.setOpcode(Mips::DADDu);
2601 Inst.addOperand(MCOperand::CreateReg(Save));
2602 Inst.addOperand(MCOperand::CreateReg(GPReg));
2603 Inst.addOperand(MCOperand::CreateReg(getGPR(0)));
2605 // sd $gpreg, offset($sp)
2606 Inst.setOpcode(Mips::SD);
2607 Inst.addOperand(MCOperand::CreateReg(GPReg));
2608 Inst.addOperand(MCOperand::CreateReg(getGPR(matchCPURegisterName("sp"))));
2609 Inst.addOperand(MCOperand::CreateImm(Save));
2611 TS.EmitInstruction(Inst, STI);
2614 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
2615 Sym->getName(), MCSymbolRefExpr::VK_Mips_GPOFF_HI,
2617 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
2618 Sym->getName(), MCSymbolRefExpr::VK_Mips_GPOFF_LO,
2620 // lui $gp, %hi(%neg(%gp_rel(funcSym)))
2621 Inst.setOpcode(Mips::LUi);
2622 Inst.addOperand(MCOperand::CreateReg(GPReg));
2623 Inst.addOperand(MCOperand::CreateExpr(HiExpr));
2624 TS.EmitInstruction(Inst, STI);
2627 // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
2628 Inst.setOpcode(Mips::ADDiu);
2629 Inst.addOperand(MCOperand::CreateReg(GPReg));
2630 Inst.addOperand(MCOperand::CreateReg(GPReg));
2631 Inst.addOperand(MCOperand::CreateExpr(LoExpr));
2632 TS.EmitInstruction(Inst, STI);
2635 // daddu $gp, $gp, $funcreg
2636 Inst.setOpcode(Mips::DADDu);
2637 Inst.addOperand(MCOperand::CreateReg(GPReg));
2638 Inst.addOperand(MCOperand::CreateReg(GPReg));
2639 Inst.addOperand(MCOperand::CreateReg(FuncReg));
2640 TS.EmitInstruction(Inst, STI);
2644 bool MipsAsmParser::parseDirectiveSet() {
2646 // Get the next token.
2647 const AsmToken &Tok = Parser.getTok();
2649 if (Tok.getString() == "noat") {
2650 return parseSetNoAtDirective();
2651 } else if (Tok.getString() == "at") {
2652 return parseSetAtDirective();
2653 } else if (Tok.getString() == "reorder") {
2654 return parseSetReorderDirective();
2655 } else if (Tok.getString() == "noreorder") {
2656 return parseSetNoReorderDirective();
2657 } else if (Tok.getString() == "macro") {
2658 return parseSetMacroDirective();
2659 } else if (Tok.getString() == "nomacro") {
2660 return parseSetNoMacroDirective();
2661 } else if (Tok.getString() == "mips16") {
2662 return parseSetFeature(Mips::FeatureMips16);
2663 } else if (Tok.getString() == "nomips16") {
2664 return parseSetNoMips16Directive();
2665 } else if (Tok.getString() == "nomicromips") {
2666 getTargetStreamer().emitDirectiveSetNoMicroMips();
2667 Parser.eatToEndOfStatement();
2669 } else if (Tok.getString() == "micromips") {
2670 return parseSetFeature(Mips::FeatureMicroMips);
2671 } else if (Tok.getString() == "mips32r2") {
2672 return parseSetFeature(Mips::FeatureMips32r2);
2673 } else if (Tok.getString() == "mips64") {
2674 return parseSetFeature(Mips::FeatureMips64);
2675 } else if (Tok.getString() == "mips64r2") {
2676 return parseSetFeature(Mips::FeatureMips64r2);
2677 } else if (Tok.getString() == "dsp") {
2678 return parseSetFeature(Mips::FeatureDSP);
2680 // It is just an identifier, look for an assignment.
2681 parseSetAssignment();
2688 /// parseDataDirective
2689 /// ::= .word [ expression (, expression)* ]
2690 bool MipsAsmParser::parseDataDirective(unsigned Size, SMLoc L) {
2691 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2693 const MCExpr *Value;
2694 if (getParser().parseExpression(Value))
2697 getParser().getStreamer().EmitValue(Value, Size);
2699 if (getLexer().is(AsmToken::EndOfStatement))
2702 // FIXME: Improve diagnostic.
2703 if (getLexer().isNot(AsmToken::Comma))
2704 return Error(L, "unexpected token in directive");
2713 /// parseDirectiveGpWord
2714 /// ::= .gpword local_sym
2715 bool MipsAsmParser::parseDirectiveGpWord() {
2716 const MCExpr *Value;
2717 // EmitGPRel32Value requires an expression, so we are using base class
2718 // method to evaluate the expression.
2719 if (getParser().parseExpression(Value))
2721 getParser().getStreamer().EmitGPRel32Value(Value);
2723 if (getLexer().isNot(AsmToken::EndOfStatement))
2724 return Error(getLexer().getLoc(), "unexpected token in directive");
2725 Parser.Lex(); // Eat EndOfStatement token.
2729 /// parseDirectiveGpDWord
2730 /// ::= .gpdword local_sym
2731 bool MipsAsmParser::parseDirectiveGpDWord() {
2732 const MCExpr *Value;
2733 // EmitGPRel64Value requires an expression, so we are using base class
2734 // method to evaluate the expression.
2735 if (getParser().parseExpression(Value))
2737 getParser().getStreamer().EmitGPRel64Value(Value);
2739 if (getLexer().isNot(AsmToken::EndOfStatement))
2740 return Error(getLexer().getLoc(), "unexpected token in directive");
2741 Parser.Lex(); // Eat EndOfStatement token.
2745 bool MipsAsmParser::parseDirectiveOption() {
2746 // Get the option token.
2747 AsmToken Tok = Parser.getTok();
2748 // At the moment only identifiers are supported.
2749 if (Tok.isNot(AsmToken::Identifier)) {
2750 Error(Parser.getTok().getLoc(), "unexpected token in .option directive");
2751 Parser.eatToEndOfStatement();
2755 StringRef Option = Tok.getIdentifier();
2757 if (Option == "pic0") {
2758 getTargetStreamer().emitDirectiveOptionPic0();
2760 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2761 Error(Parser.getTok().getLoc(),
2762 "unexpected token in .option pic0 directive");
2763 Parser.eatToEndOfStatement();
2768 if (Option == "pic2") {
2769 getTargetStreamer().emitDirectiveOptionPic2();
2771 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2772 Error(Parser.getTok().getLoc(),
2773 "unexpected token in .option pic2 directive");
2774 Parser.eatToEndOfStatement();
2780 Warning(Parser.getTok().getLoc(), "unknown option in .option directive");
2781 Parser.eatToEndOfStatement();
2785 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
2786 StringRef IDVal = DirectiveID.getString();
2788 if (IDVal == ".dword") {
2789 parseDataDirective(8, DirectiveID.getLoc());
2793 if (IDVal == ".ent") {
2794 // Ignore this directive for now.
2799 if (IDVal == ".end") {
2800 // Ignore this directive for now.
2805 if (IDVal == ".frame") {
2806 // Ignore this directive for now.
2807 Parser.eatToEndOfStatement();
2811 if (IDVal == ".set") {
2812 return parseDirectiveSet();
2815 if (IDVal == ".fmask") {
2816 // Ignore this directive for now.
2817 Parser.eatToEndOfStatement();
2821 if (IDVal == ".mask") {
2822 // Ignore this directive for now.
2823 Parser.eatToEndOfStatement();
2827 if (IDVal == ".gpword") {
2828 parseDirectiveGpWord();
2832 if (IDVal == ".gpdword") {
2833 parseDirectiveGpDWord();
2837 if (IDVal == ".word") {
2838 parseDataDirective(4, DirectiveID.getLoc());
2842 if (IDVal == ".option")
2843 return parseDirectiveOption();
2845 if (IDVal == ".abicalls") {
2846 getTargetStreamer().emitDirectiveAbiCalls();
2847 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2848 Error(Parser.getTok().getLoc(), "unexpected token in directive");
2850 Parser.eatToEndOfStatement();
2855 if (IDVal == ".cpsetup")
2856 return parseDirectiveCPSetup();
2861 extern "C" void LLVMInitializeMipsAsmParser() {
2862 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
2863 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
2864 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
2865 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
2868 #define GET_REGISTER_MATCHER
2869 #define GET_MATCHER_IMPLEMENTATION
2870 #include "MipsGenAsmMatcher.inc"