1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCTargetDesc.h"
11 #include "MipsRegisterInfo.h"
12 #include "MipsTargetStreamer.h"
13 #include "llvm/ADT/StringSwitch.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCParser/MCAsmLexer.h"
18 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
19 #include "llvm/MC/MCStreamer.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/MC/MCTargetAsmParser.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/ADT/APInt.h"
33 class MipsAssemblerOptions {
35 MipsAssemblerOptions():
36 aTReg(1), reorder(true), macro(true) {
39 unsigned getATRegNum() {return aTReg;}
40 bool setATReg(unsigned Reg);
42 bool isReorder() {return reorder;}
43 void setReorder() {reorder = true;}
44 void setNoreorder() {reorder = false;}
46 bool isMacro() {return macro;}
47 void setMacro() {macro = true;}
48 void setNomacro() {macro = false;}
58 class MipsAsmParser : public MCTargetAsmParser {
60 MipsTargetStreamer &getTargetStreamer() {
61 MCTargetStreamer &TS = Parser.getStreamer().getTargetStreamer();
62 return static_cast<MipsTargetStreamer &>(TS);
67 MipsAssemblerOptions Options;
68 bool hasConsumedDollar;
70 #define GET_ASSEMBLER_HEADER
71 #include "MipsGenAsmMatcher.inc"
73 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
74 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
75 MCStreamer &Out, unsigned &ErrorInfo,
76 bool MatchingInlineAsm);
78 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
80 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
82 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
84 bool ParseDirective(AsmToken DirectiveID);
86 MipsAsmParser::OperandMatchResultTy
87 parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
90 MipsAsmParser::OperandMatchResultTy
91 parseMSARegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
94 MipsAsmParser::OperandMatchResultTy
95 parseMSACtrlRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
98 MipsAsmParser::OperandMatchResultTy
99 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
101 bool parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands, int RegKind);
103 MipsAsmParser::OperandMatchResultTy
104 parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
106 MipsAsmParser::OperandMatchResultTy
107 parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
109 MipsAsmParser::OperandMatchResultTy
110 parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
112 MipsAsmParser::OperandMatchResultTy
113 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
115 MipsAsmParser::OperandMatchResultTy
116 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
118 MipsAsmParser::OperandMatchResultTy
119 parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
121 MipsAsmParser::OperandMatchResultTy
122 parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
124 MipsAsmParser::OperandMatchResultTy
125 parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
127 MipsAsmParser::OperandMatchResultTy
128 parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
130 MipsAsmParser::OperandMatchResultTy
131 parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
133 MipsAsmParser::OperandMatchResultTy
134 parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
136 MipsAsmParser::OperandMatchResultTy
137 parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
139 MipsAsmParser::OperandMatchResultTy
140 parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
142 MipsAsmParser::OperandMatchResultTy
143 parseCOP2(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
145 MipsAsmParser::OperandMatchResultTy
146 parseMSA128BRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
148 MipsAsmParser::OperandMatchResultTy
149 parseMSA128HRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
151 MipsAsmParser::OperandMatchResultTy
152 parseMSA128WRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
154 MipsAsmParser::OperandMatchResultTy
155 parseMSA128DRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
157 MipsAsmParser::OperandMatchResultTy
158 parseMSA128CtrlRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
160 MipsAsmParser::OperandMatchResultTy
161 parseInvNum(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
163 bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
166 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &,
169 int tryParseRegister(bool is64BitReg);
171 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
174 bool needsExpansion(MCInst &Inst);
176 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
177 SmallVectorImpl<MCInst> &Instructions);
178 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
179 SmallVectorImpl<MCInst> &Instructions);
180 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
181 SmallVectorImpl<MCInst> &Instructions);
182 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
183 SmallVectorImpl<MCInst> &Instructions);
184 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
185 SmallVectorImpl<MCInst> &Instructions,
186 bool isLoad,bool isImmOpnd);
187 bool reportParseError(StringRef ErrorMsg);
189 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
190 bool parseRelocOperand(const MCExpr *&Res);
192 const MCExpr* evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
194 bool isEvaluated(const MCExpr *Expr);
195 bool parseDirectiveSet();
196 bool parseDirectiveMipsHackStocg();
197 bool parseDirectiveMipsHackELFFlags();
199 bool parseSetAtDirective();
200 bool parseSetNoAtDirective();
201 bool parseSetMacroDirective();
202 bool parseSetNoMacroDirective();
203 bool parseSetReorderDirective();
204 bool parseSetNoReorderDirective();
206 bool parseSetAssignment();
208 bool parseDirectiveWord(unsigned Size, SMLoc L);
210 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
212 bool isMips64() const {
213 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
216 bool isFP64() const {
217 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
221 return STI.getFeatureBits() & Mips::FeatureN64;
224 int matchRegisterName(StringRef Symbol, bool is64BitReg);
226 int matchCPURegisterName(StringRef Symbol);
228 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
230 int matchFPURegisterName(StringRef Name);
232 int matchFCCRegisterName(StringRef Name);
234 int matchACRegisterName(StringRef Name);
236 int matchMSA128RegisterName(StringRef Name);
238 int matchMSA128CtrlRegisterName(StringRef Name);
240 int regKindToRegClass(int RegKind);
242 unsigned getReg(int RC, int RegNo);
246 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
247 SmallVectorImpl<MCInst> &Instructions);
249 // Helper function that checks if the value of a vector index is within the
250 // boundaries of accepted values for each RegisterKind
251 // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
252 bool validateMSAIndex(int Val, int RegKind);
255 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
256 const MCInstrInfo &MII)
257 : MCTargetAsmParser(), STI(sti), Parser(parser),
258 hasConsumedDollar(false) {
259 // Initialize the set of available features.
260 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
263 MCAsmParser &getParser() const { return Parser; }
264 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
271 /// MipsOperand - Instances of this class represent a parsed Mips machine
273 class MipsOperand : public MCParsedAsmOperand {
310 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
338 SMLoc StartLoc, EndLoc;
341 void addRegOperands(MCInst &Inst, unsigned N) const {
342 assert(N == 1 && "Invalid number of operands!");
343 Inst.addOperand(MCOperand::CreateReg(getReg()));
346 void addPtrRegOperands(MCInst &Inst, unsigned N) const {
347 assert(N == 1 && "Invalid number of operands!");
348 Inst.addOperand(MCOperand::CreateReg(getPtrReg()));
351 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
352 // Add as immediate when possible. Null MCExpr = 0.
354 Inst.addOperand(MCOperand::CreateImm(0));
355 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
356 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
358 Inst.addOperand(MCOperand::CreateExpr(Expr));
361 void addImmOperands(MCInst &Inst, unsigned N) const {
362 assert(N == 1 && "Invalid number of operands!");
363 const MCExpr *Expr = getImm();
367 void addMemOperands(MCInst &Inst, unsigned N) const {
368 assert(N == 2 && "Invalid number of operands!");
370 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
372 const MCExpr *Expr = getMemOff();
376 bool isReg() const { return Kind == k_Register; }
377 bool isImm() const { return Kind == k_Immediate; }
378 bool isToken() const { return Kind == k_Token; }
379 bool isMem() const { return Kind == k_Memory; }
380 bool isPtrReg() const { return Kind == k_PtrReg; }
381 bool isInvNum() const { return Kind == k_Immediate; }
383 StringRef getToken() const {
384 assert(Kind == k_Token && "Invalid access!");
385 return StringRef(Tok.Data, Tok.Length);
388 unsigned getReg() const {
389 assert((Kind == k_Register) && "Invalid access!");
393 unsigned getPtrReg() const {
394 assert((Kind == k_PtrReg) && "Invalid access!");
398 void setRegKind(RegisterKind RegKind) {
399 assert((Kind == k_Register || Kind == k_PtrReg) && "Invalid access!");
403 const MCExpr *getImm() const {
404 assert((Kind == k_Immediate) && "Invalid access!");
408 unsigned getMemBase() const {
409 assert((Kind == k_Memory) && "Invalid access!");
413 const MCExpr *getMemOff() const {
414 assert((Kind == k_Memory) && "Invalid access!");
418 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
419 MipsOperand *Op = new MipsOperand(k_Token);
420 Op->Tok.Data = Str.data();
421 Op->Tok.Length = Str.size();
427 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
428 MipsOperand *Op = new MipsOperand(k_Register);
429 Op->Reg.RegNum = RegNum;
435 static MipsOperand *CreatePtrReg(unsigned RegNum, SMLoc S, SMLoc E) {
436 MipsOperand *Op = new MipsOperand(k_PtrReg);
437 Op->Reg.RegNum = RegNum;
443 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
444 MipsOperand *Op = new MipsOperand(k_Immediate);
451 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off,
453 MipsOperand *Op = new MipsOperand(k_Memory);
461 bool isGPR32Asm() const {
462 return Kind == k_Register && Reg.Kind == Kind_GPR32;
464 void addRegAsmOperands(MCInst &Inst, unsigned N) const {
465 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
468 bool isGPR64Asm() const {
469 return Kind == k_Register && Reg.Kind == Kind_GPR64;
472 bool isHWRegsAsm() const {
473 assert((Kind == k_Register) && "Invalid access!");
474 return Reg.Kind == Kind_HWRegs;
477 bool isCCRAsm() const {
478 assert((Kind == k_Register) && "Invalid access!");
479 return Reg.Kind == Kind_CCRRegs;
482 bool isAFGR64Asm() const {
483 return Kind == k_Register && Reg.Kind == Kind_AFGR64Regs;
486 bool isFGR64Asm() const {
487 return Kind == k_Register && Reg.Kind == Kind_FGR64Regs;
490 bool isFGR32Asm() const {
491 return (Kind == k_Register) && Reg.Kind == Kind_FGR32Regs;
494 bool isFGRH32Asm() const {
495 return (Kind == k_Register) && Reg.Kind == Kind_FGRH32Regs;
498 bool isFCCRegsAsm() const {
499 return (Kind == k_Register) && Reg.Kind == Kind_FCCRegs;
502 bool isACC64DSPAsm() const {
503 return Kind == k_Register && Reg.Kind == Kind_ACC64DSP;
506 bool isLO32DSPAsm() const {
507 return Kind == k_Register && Reg.Kind == Kind_LO32DSP;
510 bool isHI32DSPAsm() const {
511 return Kind == k_Register && Reg.Kind == Kind_HI32DSP;
514 bool isCOP2Asm() const {
515 return Kind == k_Register && Reg.Kind == Kind_COP2;
518 bool isMSA128BAsm() const {
519 return Kind == k_Register && Reg.Kind == Kind_MSA128BRegs;
522 bool isMSA128HAsm() const {
523 return Kind == k_Register && Reg.Kind == Kind_MSA128HRegs;
526 bool isMSA128WAsm() const {
527 return Kind == k_Register && Reg.Kind == Kind_MSA128WRegs;
530 bool isMSA128DAsm() const {
531 return Kind == k_Register && Reg.Kind == Kind_MSA128DRegs;
534 bool isMSA128CRAsm() const {
535 return Kind == k_Register && Reg.Kind == Kind_MSA128CtrlRegs;
538 /// getStartLoc - Get the location of the first token of this operand.
539 SMLoc getStartLoc() const {
542 /// getEndLoc - Get the location of the last token of this operand.
543 SMLoc getEndLoc() const {
547 virtual void print(raw_ostream &OS) const {
548 llvm_unreachable("unimplemented!");
550 }; // class MipsOperand
554 extern const MCInstrDesc MipsInsts[];
556 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
557 return MipsInsts[Opcode];
560 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
561 SmallVectorImpl<MCInst> &Instructions) {
562 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
564 if (MCID.hasDelaySlot() && Options.isReorder()) {
565 // If this instruction has a delay slot and .set reorder is active,
566 // emit a NOP after it.
567 Instructions.push_back(Inst);
569 NopInst.setOpcode(Mips::SLL);
570 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
571 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
572 NopInst.addOperand(MCOperand::CreateImm(0));
573 Instructions.push_back(NopInst);
577 if (MCID.mayLoad() || MCID.mayStore()) {
578 // Check the offset of memory operand, if it is a symbol
579 // reference or immediate we may have to expand instructions.
580 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
581 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
582 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY)
583 || (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
584 MCOperand &Op = Inst.getOperand(i);
586 int MemOffset = Op.getImm();
587 if (MemOffset < -32768 || MemOffset > 32767) {
588 // Offset can't exceed 16bit value.
589 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
592 } else if (Op.isExpr()) {
593 const MCExpr *Expr = Op.getExpr();
594 if (Expr->getKind() == MCExpr::SymbolRef) {
595 const MCSymbolRefExpr *SR =
596 static_cast<const MCSymbolRefExpr*>(Expr);
597 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
599 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
602 } else if (!isEvaluated(Expr)) {
603 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
611 if (needsExpansion(Inst))
612 expandInstruction(Inst, IDLoc, Instructions);
614 Instructions.push_back(Inst);
619 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
621 switch (Inst.getOpcode()) {
622 case Mips::LoadImm32Reg:
623 case Mips::LoadAddr32Imm:
624 case Mips::LoadAddr32Reg:
631 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
632 SmallVectorImpl<MCInst> &Instructions) {
633 switch (Inst.getOpcode()) {
634 case Mips::LoadImm32Reg:
635 return expandLoadImm(Inst, IDLoc, Instructions);
636 case Mips::LoadAddr32Imm:
637 return expandLoadAddressImm(Inst, IDLoc, Instructions);
638 case Mips::LoadAddr32Reg:
639 return expandLoadAddressReg(Inst, IDLoc, Instructions);
643 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
644 SmallVectorImpl<MCInst> &Instructions) {
646 const MCOperand &ImmOp = Inst.getOperand(1);
647 assert(ImmOp.isImm() && "expected immediate operand kind");
648 const MCOperand &RegOp = Inst.getOperand(0);
649 assert(RegOp.isReg() && "expected register operand kind");
651 int ImmValue = ImmOp.getImm();
652 tmpInst.setLoc(IDLoc);
653 if (0 <= ImmValue && ImmValue <= 65535) {
654 // For 0 <= j <= 65535.
655 // li d,j => ori d,$zero,j
656 tmpInst.setOpcode(Mips::ORi);
657 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
658 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
659 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
660 Instructions.push_back(tmpInst);
661 } else if (ImmValue < 0 && ImmValue >= -32768) {
662 // For -32768 <= j < 0.
663 // li d,j => addiu d,$zero,j
664 tmpInst.setOpcode(Mips::ADDiu);
665 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
666 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
667 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
668 Instructions.push_back(tmpInst);
670 // For any other value of j that is representable as a 32-bit integer.
671 // li d,j => lui d,hi16(j)
673 tmpInst.setOpcode(Mips::LUi);
674 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
675 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
676 Instructions.push_back(tmpInst);
678 tmpInst.setOpcode(Mips::ORi);
679 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
680 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
681 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
682 tmpInst.setLoc(IDLoc);
683 Instructions.push_back(tmpInst);
687 void MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
688 SmallVectorImpl<MCInst> &Instructions) {
690 const MCOperand &ImmOp = Inst.getOperand(2);
691 assert(ImmOp.isImm() && "expected immediate operand kind");
692 const MCOperand &SrcRegOp = Inst.getOperand(1);
693 assert(SrcRegOp.isReg() && "expected register operand kind");
694 const MCOperand &DstRegOp = Inst.getOperand(0);
695 assert(DstRegOp.isReg() && "expected register operand kind");
696 int ImmValue = ImmOp.getImm();
697 if (-32768 <= ImmValue && ImmValue <= 65535) {
698 // For -32768 <= j <= 65535.
699 // la d,j(s) => addiu d,s,j
700 tmpInst.setOpcode(Mips::ADDiu);
701 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
702 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
703 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
704 Instructions.push_back(tmpInst);
706 // For any other value of j that is representable as a 32-bit integer.
707 // la d,j(s) => lui d,hi16(j)
710 tmpInst.setOpcode(Mips::LUi);
711 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
712 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
713 Instructions.push_back(tmpInst);
715 tmpInst.setOpcode(Mips::ORi);
716 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
717 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
718 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
719 Instructions.push_back(tmpInst);
721 tmpInst.setOpcode(Mips::ADDu);
722 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
723 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
724 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
725 Instructions.push_back(tmpInst);
729 void MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
730 SmallVectorImpl<MCInst> &Instructions) {
732 const MCOperand &ImmOp = Inst.getOperand(1);
733 assert(ImmOp.isImm() && "expected immediate operand kind");
734 const MCOperand &RegOp = Inst.getOperand(0);
735 assert(RegOp.isReg() && "expected register operand kind");
736 int ImmValue = ImmOp.getImm();
737 if (-32768 <= ImmValue && ImmValue <= 65535) {
738 // For -32768 <= j <= 65535.
739 // la d,j => addiu d,$zero,j
740 tmpInst.setOpcode(Mips::ADDiu);
741 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
742 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
743 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
744 Instructions.push_back(tmpInst);
746 // For any other value of j that is representable as a 32-bit integer.
747 // la d,j => lui d,hi16(j)
749 tmpInst.setOpcode(Mips::LUi);
750 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
751 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
752 Instructions.push_back(tmpInst);
754 tmpInst.setOpcode(Mips::ORi);
755 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
756 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
757 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
758 Instructions.push_back(tmpInst);
762 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
763 SmallVectorImpl<MCInst> &Instructions, bool isLoad, bool isImmOpnd) {
764 const MCSymbolRefExpr *SR;
766 unsigned ImmOffset, HiOffset, LoOffset;
767 const MCExpr *ExprOffset;
769 unsigned AtRegNum = getReg((isMips64()) ? Mips::GPR64RegClassID
770 : Mips::GPR32RegClassID, getATReg());
771 // 1st operand is either the source or destination register.
772 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
773 unsigned RegOpNum = Inst.getOperand(0).getReg();
774 // 2nd operand is the base register.
775 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
776 unsigned BaseRegNum = Inst.getOperand(1).getReg();
777 // 3rd operand is either an immediate or expression.
779 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
780 ImmOffset = Inst.getOperand(2).getImm();
781 LoOffset = ImmOffset & 0x0000ffff;
782 HiOffset = (ImmOffset & 0xffff0000) >> 16;
783 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
784 if (LoOffset & 0x8000)
787 ExprOffset = Inst.getOperand(2).getExpr();
788 // All instructions will have the same location.
789 TempInst.setLoc(IDLoc);
790 // 1st instruction in expansion is LUi. For load instruction we can use
791 // the dst register as a temporary if base and dst are different,
792 // but for stores we must use $at.
793 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
794 TempInst.setOpcode(Mips::LUi);
795 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
797 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
799 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
800 SR = static_cast<const MCSymbolRefExpr*>(ExprOffset);
801 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
802 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
804 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
806 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
807 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
810 // Add the instruction to the list.
811 Instructions.push_back(TempInst);
812 // Prepare TempInst for next instruction.
814 // Add temp register to base.
815 TempInst.setOpcode(Mips::ADDu);
816 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
817 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
818 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
819 Instructions.push_back(TempInst);
821 // And finaly, create original instruction with low part
822 // of offset and new base.
823 TempInst.setOpcode(Inst.getOpcode());
824 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
825 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
827 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
829 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
830 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
831 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
833 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
835 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
836 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
839 Instructions.push_back(TempInst);
844 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
845 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
846 MCStreamer &Out, unsigned &ErrorInfo,
847 bool MatchingInlineAsm) {
849 SmallVector<MCInst, 8> Instructions;
850 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
853 switch (MatchResult) {
856 case Match_Success: {
857 if (processInstruction(Inst, IDLoc, Instructions))
859 for (unsigned i = 0; i < Instructions.size(); i++)
860 Out.EmitInstruction(Instructions[i]);
863 case Match_MissingFeature:
864 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
866 case Match_InvalidOperand: {
867 SMLoc ErrorLoc = IDLoc;
868 if (ErrorInfo != ~0U) {
869 if (ErrorInfo >= Operands.size())
870 return Error(IDLoc, "too few operands for instruction");
872 ErrorLoc = ((MipsOperand*) Operands[ErrorInfo])->getStartLoc();
873 if (ErrorLoc == SMLoc())
877 return Error(ErrorLoc, "invalid operand for instruction");
879 case Match_MnemonicFail:
880 return Error(IDLoc, "invalid instruction");
885 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
891 CC = StringSwitch<unsigned>(Name)
925 // Although SGI documentation just cuts out t0-t3 for n32/n64,
926 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
927 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
928 if (isMips64() && 8 <= CC && CC <= 11)
931 if (CC == -1 && isMips64())
932 CC = StringSwitch<unsigned>(Name)
945 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
947 if (Name[0] == 'f') {
948 StringRef NumString = Name.substr(1);
950 if (NumString.getAsInteger(10, IntVal))
951 return -1; // This is not an integer.
952 if (IntVal > 31) // Maximum index for fpu register.
959 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
961 if (Name.startswith("fcc")) {
962 StringRef NumString = Name.substr(3);
964 if (NumString.getAsInteger(10, IntVal))
965 return -1; // This is not an integer.
966 if (IntVal > 7) // There are only 8 fcc registers.
973 int MipsAsmParser::matchACRegisterName(StringRef Name) {
975 if (Name.startswith("ac")) {
976 StringRef NumString = Name.substr(2);
978 if (NumString.getAsInteger(10, IntVal))
979 return -1; // This is not an integer.
980 if (IntVal > 3) // There are only 3 acc registers.
987 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
990 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal))
999 int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) {
1002 CC = StringSwitch<unsigned>(Name)
1005 .Case("msaaccess", 2)
1007 .Case("msamodify", 4)
1008 .Case("msarequest", 5)
1010 .Case("msaunmap", 7)
1016 int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
1019 CC = matchCPURegisterName(Name);
1021 return matchRegisterByNumber(CC, is64BitReg ? Mips::GPR64RegClassID
1022 : Mips::GPR32RegClassID);
1023 CC = matchFPURegisterName(Name);
1024 //TODO: decide about fpu register class
1026 return matchRegisterByNumber(CC, isFP64() ? Mips::FGR64RegClassID
1027 : Mips::FGR32RegClassID);
1028 return matchMSA128RegisterName(Name);
1031 int MipsAsmParser::regKindToRegClass(int RegKind) {
1034 case MipsOperand::Kind_GPR32: return Mips::GPR32RegClassID;
1035 case MipsOperand::Kind_GPR64: return Mips::GPR64RegClassID;
1036 case MipsOperand::Kind_HWRegs: return Mips::HWRegsRegClassID;
1037 case MipsOperand::Kind_FGR32Regs: return Mips::FGR32RegClassID;
1038 case MipsOperand::Kind_FGRH32Regs: return Mips::FGRH32RegClassID;
1039 case MipsOperand::Kind_FGR64Regs: return Mips::FGR64RegClassID;
1040 case MipsOperand::Kind_AFGR64Regs: return Mips::AFGR64RegClassID;
1041 case MipsOperand::Kind_CCRRegs: return Mips::CCRRegClassID;
1042 case MipsOperand::Kind_ACC64DSP: return Mips::ACC64DSPRegClassID;
1043 case MipsOperand::Kind_FCCRegs: return Mips::FCCRegClassID;
1044 case MipsOperand::Kind_MSA128BRegs: return Mips::MSA128BRegClassID;
1045 case MipsOperand::Kind_MSA128HRegs: return Mips::MSA128HRegClassID;
1046 case MipsOperand::Kind_MSA128WRegs: return Mips::MSA128WRegClassID;
1047 case MipsOperand::Kind_MSA128DRegs: return Mips::MSA128DRegClassID;
1048 case MipsOperand::Kind_MSA128CtrlRegs: return Mips::MSACtrlRegClassID;
1054 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
1062 int MipsAsmParser::getATReg() {
1063 return Options.getATRegNum();
1066 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
1067 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1070 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
1072 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs())
1075 return getReg(RegClass, RegNum);
1078 int MipsAsmParser::tryParseRegister(bool is64BitReg) {
1079 const AsmToken &Tok = Parser.getTok();
1082 if (Tok.is(AsmToken::Identifier)) {
1083 std::string lowerCase = Tok.getString().lower();
1084 RegNum = matchRegisterName(lowerCase, is64BitReg);
1085 } else if (Tok.is(AsmToken::Integer))
1086 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
1087 is64BitReg ? Mips::GPR64RegClassID : Mips::GPR32RegClassID);
1091 bool MipsAsmParser::tryParseRegisterOperand(
1092 SmallVectorImpl<MCParsedAsmOperand*> &Operands, bool is64BitReg) {
1094 SMLoc S = Parser.getTok().getLoc();
1097 RegNo = tryParseRegister(is64BitReg);
1101 Operands.push_back(MipsOperand::CreateReg(RegNo, S,
1102 Parser.getTok().getLoc()));
1103 Parser.Lex(); // Eat register token.
1107 bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
1108 StringRef Mnemonic) {
1109 // Check if the current operand has a custom associated parser, if so, try to
1110 // custom parse the operand, or fallback to the general approach.
1111 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1112 if (ResTy == MatchOperand_Success)
1114 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1115 // there was a match, but an error occurred, in which case, just return that
1116 // the operand parsing failed.
1117 if (ResTy == MatchOperand_ParseFail)
1120 switch (getLexer().getKind()) {
1122 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1124 case AsmToken::Dollar: {
1125 // Parse the register.
1126 SMLoc S = Parser.getTok().getLoc();
1127 Parser.Lex(); // Eat dollar token.
1128 // Parse the register operand.
1129 if (!tryParseRegisterOperand(Operands, isMips64())) {
1130 if (getLexer().is(AsmToken::LParen)) {
1131 // Check if it is indexed addressing operand.
1132 Operands.push_back(MipsOperand::CreateToken("(", S));
1133 Parser.Lex(); // Eat the parenthesis.
1134 if (getLexer().isNot(AsmToken::Dollar))
1137 Parser.Lex(); // Eat the dollar
1138 if (tryParseRegisterOperand(Operands, isMips64()))
1141 if (!getLexer().is(AsmToken::RParen))
1144 S = Parser.getTok().getLoc();
1145 Operands.push_back(MipsOperand::CreateToken(")", S));
1150 // Maybe it is a symbol reference.
1151 StringRef Identifier;
1152 if (Parser.parseIdentifier(Identifier))
1155 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1157 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1159 // Otherwise create a symbol reference.
1160 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
1163 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
1166 case AsmToken::Identifier:
1167 // Look for the existing symbol, we should check if
1168 // we need to assigne the propper RegisterKind.
1169 if (searchSymbolAlias(Operands, MipsOperand::Kind_None))
1171 // Else drop to expression parsing.
1172 case AsmToken::LParen:
1173 case AsmToken::Minus:
1174 case AsmToken::Plus:
1175 case AsmToken::Integer:
1176 case AsmToken::String: {
1177 // Quoted label names.
1178 const MCExpr *IdVal;
1179 SMLoc S = Parser.getTok().getLoc();
1180 if (getParser().parseExpression(IdVal))
1182 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1183 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1186 case AsmToken::Percent: {
1187 // It is a symbol reference or constant expression.
1188 const MCExpr *IdVal;
1189 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1190 if (parseRelocOperand(IdVal))
1193 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1195 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1197 } // case AsmToken::Percent
1198 } // switch(getLexer().getKind())
1202 const MCExpr* MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1203 StringRef RelocStr) {
1205 // Check the type of the expression.
1206 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1207 // It's a constant, evaluate lo or hi value.
1208 if (RelocStr == "lo") {
1209 short Val = MCE->getValue();
1210 Res = MCConstantExpr::Create(Val, getContext());
1211 } else if (RelocStr == "hi") {
1212 int Val = MCE->getValue();
1213 int LoSign = Val & 0x8000;
1214 Val = (Val & 0xffff0000) >> 16;
1215 // Lower part is treated as a signed int, so if it is negative
1216 // we must add 1 to the hi part to compensate.
1219 Res = MCConstantExpr::Create(Val, getContext());
1221 llvm_unreachable("Invalid RelocStr value");
1226 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1227 // It's a symbol, create a symbolic expression from the symbol.
1228 StringRef Symbol = MSRE->getSymbol().getName();
1229 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1230 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1234 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1235 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1236 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1237 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1241 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1242 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1243 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1246 // Just return the original expression.
1250 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1252 switch (Expr->getKind()) {
1253 case MCExpr::Constant:
1255 case MCExpr::SymbolRef:
1256 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1257 case MCExpr::Binary:
1258 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1259 if (!isEvaluated(BE->getLHS()))
1261 return isEvaluated(BE->getRHS());
1264 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1271 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1272 Parser.Lex(); // Eat the % token.
1273 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1274 if (Tok.isNot(AsmToken::Identifier))
1277 std::string Str = Tok.getIdentifier().str();
1279 Parser.Lex(); // Eat the identifier.
1280 // Now make an expression from the rest of the operand.
1281 const MCExpr *IdVal;
1284 if (getLexer().getKind() == AsmToken::LParen) {
1286 Parser.Lex(); // Eat the '(' token.
1287 if (getLexer().getKind() == AsmToken::Percent) {
1288 Parser.Lex(); // Eat the % token.
1289 const AsmToken &nextTok = Parser.getTok();
1290 if (nextTok.isNot(AsmToken::Identifier))
1293 Str += nextTok.getIdentifier();
1294 Parser.Lex(); // Eat the identifier.
1295 if (getLexer().getKind() != AsmToken::LParen)
1300 if (getParser().parseParenExpression(IdVal, EndLoc))
1303 while (getLexer().getKind() == AsmToken::RParen)
1304 Parser.Lex(); // Eat the ')' token.
1307 return true; // Parenthesis must follow the relocation operand.
1309 Res = evaluateRelocExpr(IdVal, Str);
1313 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1315 StartLoc = Parser.getTok().getLoc();
1316 RegNo = tryParseRegister(isMips64());
1317 EndLoc = Parser.getTok().getLoc();
1318 return (RegNo == (unsigned) -1);
1321 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1325 while (getLexer().getKind() == AsmToken::LParen)
1328 switch (getLexer().getKind()) {
1331 case AsmToken::Identifier:
1332 case AsmToken::LParen:
1333 case AsmToken::Integer:
1334 case AsmToken::Minus:
1335 case AsmToken::Plus:
1337 Result = getParser().parseParenExpression(Res, S);
1339 Result = (getParser().parseExpression(Res));
1340 while (getLexer().getKind() == AsmToken::RParen)
1343 case AsmToken::Percent:
1344 Result = parseRelocOperand(Res);
1349 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1350 SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
1352 const MCExpr *IdVal = 0;
1354 bool isParenExpr = false;
1355 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1356 // First operand is the offset.
1357 S = Parser.getTok().getLoc();
1359 if (getLexer().getKind() == AsmToken::LParen) {
1364 if (getLexer().getKind() != AsmToken::Dollar) {
1365 if (parseMemOffset(IdVal, isParenExpr))
1366 return MatchOperand_ParseFail;
1368 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1369 if (Tok.isNot(AsmToken::LParen)) {
1370 MipsOperand *Mnemonic = static_cast<MipsOperand*>(Operands[0]);
1371 if (Mnemonic->getToken() == "la") {
1372 SMLoc E = SMLoc::getFromPointer(
1373 Parser.getTok().getLoc().getPointer() - 1);
1374 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1375 return MatchOperand_Success;
1377 if (Tok.is(AsmToken::EndOfStatement)) {
1378 SMLoc E = SMLoc::getFromPointer(
1379 Parser.getTok().getLoc().getPointer() - 1);
1381 // Zero register assumed, add a memory operand with ZERO as its base.
1382 Operands.push_back(MipsOperand::CreateMem(isMips64() ? Mips::ZERO_64
1385 return MatchOperand_Success;
1387 Error(Parser.getTok().getLoc(), "'(' expected");
1388 return MatchOperand_ParseFail;
1391 Parser.Lex(); // Eat the '(' token.
1394 Res = parseRegs(Operands, isMips64()? (int) MipsOperand::Kind_GPR64:
1395 (int) MipsOperand::Kind_GPR32);
1396 if (Res != MatchOperand_Success)
1399 if (Parser.getTok().isNot(AsmToken::RParen)) {
1400 Error(Parser.getTok().getLoc(), "')' expected");
1401 return MatchOperand_ParseFail;
1404 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1406 Parser.Lex(); // Eat the ')' token.
1409 IdVal = MCConstantExpr::Create(0, getContext());
1411 // Replace the register operand with the memory operand.
1412 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1413 int RegNo = op->getReg();
1414 // Remove the register from the operands.
1415 Operands.pop_back();
1416 // Add the memory operand.
1417 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1419 if (IdVal->EvaluateAsAbsolute(Imm))
1420 IdVal = MCConstantExpr::Create(Imm, getContext());
1421 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1422 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1426 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
1428 return MatchOperand_Success;
1432 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1434 // If the first token is not '$' we have an error.
1435 if (Parser.getTok().isNot(AsmToken::Dollar))
1438 SMLoc S = Parser.getTok().getLoc();
1440 AsmToken::TokenKind TkKind = getLexer().getKind();
1443 if (TkKind == AsmToken::Integer) {
1444 Reg = matchRegisterByNumber(Parser.getTok().getIntVal(),
1445 regKindToRegClass(RegKind));
1448 } else if (TkKind == AsmToken::Identifier) {
1449 if ((Reg = matchCPURegisterName(Parser.getTok().getString().lower())) == -1)
1451 Reg = getReg(regKindToRegClass(RegKind), Reg);
1456 MipsOperand *Op = MipsOperand::CreatePtrReg(Reg, S, Parser.getTok().getLoc());
1457 Op->setRegKind((MipsOperand::RegisterKind)RegKind);
1458 Operands.push_back(Op);
1463 MipsAsmParser::OperandMatchResultTy
1464 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1465 MipsOperand::RegisterKind RegKind = isN64() ? MipsOperand::Kind_GPR64 :
1466 MipsOperand::Kind_GPR32;
1468 // Parse index register.
1469 if (!parsePtrReg(Operands, RegKind))
1470 return MatchOperand_NoMatch;
1473 if (Parser.getTok().isNot(AsmToken::LParen))
1474 return MatchOperand_NoMatch;
1476 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1479 // Parse base register.
1480 if (!parsePtrReg(Operands, RegKind))
1481 return MatchOperand_NoMatch;
1484 if (Parser.getTok().isNot(AsmToken::RParen))
1485 return MatchOperand_NoMatch;
1487 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1490 return MatchOperand_Success;
1493 MipsAsmParser::OperandMatchResultTy
1494 MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1496 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1497 if (getLexer().getKind() == AsmToken::Identifier
1498 && !hasConsumedDollar) {
1499 if (searchSymbolAlias(Operands, Kind))
1500 return MatchOperand_Success;
1501 return MatchOperand_NoMatch;
1503 SMLoc S = Parser.getTok().getLoc();
1504 // If the first token is not '$', we have an error.
1505 if (Parser.getTok().isNot(AsmToken::Dollar) && !hasConsumedDollar)
1506 return MatchOperand_NoMatch;
1507 if (!hasConsumedDollar) {
1508 Parser.Lex(); // Eat the '$'
1509 hasConsumedDollar = true;
1511 if (getLexer().getKind() == AsmToken::Identifier) {
1513 std::string RegName = Parser.getTok().getString().lower();
1514 // Match register by name
1516 case MipsOperand::Kind_GPR32:
1517 case MipsOperand::Kind_GPR64:
1518 RegNum = matchCPURegisterName(RegName);
1520 case MipsOperand::Kind_AFGR64Regs:
1521 case MipsOperand::Kind_FGR64Regs:
1522 case MipsOperand::Kind_FGR32Regs:
1523 case MipsOperand::Kind_FGRH32Regs:
1524 RegNum = matchFPURegisterName(RegName);
1525 if (RegKind == MipsOperand::Kind_AFGR64Regs)
1527 else if (RegKind == MipsOperand::Kind_FGRH32Regs
1529 if (RegNum != -1 && RegNum %2 != 0)
1530 Warning(S, "Float register should be even.");
1532 case MipsOperand::Kind_FCCRegs:
1533 RegNum = matchFCCRegisterName(RegName);
1535 case MipsOperand::Kind_ACC64DSP:
1536 RegNum = matchACRegisterName(RegName);
1538 default: break; // No match, value is set to -1.
1540 // No match found, return _NoMatch to give a chance to other round.
1542 return MatchOperand_NoMatch;
1544 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1546 return MatchOperand_NoMatch;
1548 MipsOperand *Op = MipsOperand::CreateReg(RegVal, S,
1549 Parser.getTok().getLoc());
1550 Op->setRegKind(Kind);
1551 Operands.push_back(Op);
1552 hasConsumedDollar = false;
1553 Parser.Lex(); // Eat the register name.
1554 return MatchOperand_Success;
1555 } else if (getLexer().getKind() == AsmToken::Integer) {
1556 unsigned RegNum = Parser.getTok().getIntVal();
1557 if (Kind == MipsOperand::Kind_HWRegs) {
1559 return MatchOperand_NoMatch;
1560 // Only hwreg 29 is supported, found at index 0.
1563 int Reg = matchRegisterByNumber(RegNum, regKindToRegClass(Kind));
1565 return MatchOperand_NoMatch;
1566 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1567 Op->setRegKind(Kind);
1568 Operands.push_back(Op);
1569 hasConsumedDollar = false;
1570 Parser.Lex(); // Eat the register number.
1571 if ((RegKind == MipsOperand::Kind_GPR32)
1572 && (getLexer().is(AsmToken::LParen))) {
1573 // Check if it is indexed addressing operand.
1574 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1575 Parser.Lex(); // Eat the parenthesis.
1576 if (parseRegs(Operands,RegKind) != MatchOperand_Success)
1577 return MatchOperand_NoMatch;
1578 if (getLexer().isNot(AsmToken::RParen))
1579 return MatchOperand_NoMatch;
1580 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1583 return MatchOperand_Success;
1585 return MatchOperand_NoMatch;
1588 bool MipsAsmParser::validateMSAIndex(int Val, int RegKind) {
1589 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1597 case MipsOperand::Kind_MSA128BRegs:
1599 case MipsOperand::Kind_MSA128HRegs:
1601 case MipsOperand::Kind_MSA128WRegs:
1603 case MipsOperand::Kind_MSA128DRegs:
1608 MipsAsmParser::OperandMatchResultTy
1609 MipsAsmParser::parseMSARegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1611 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1612 SMLoc S = Parser.getTok().getLoc();
1613 std::string RegName;
1615 if (Parser.getTok().isNot(AsmToken::Dollar))
1616 return MatchOperand_NoMatch;
1620 return MatchOperand_ParseFail;
1621 case MipsOperand::Kind_MSA128BRegs:
1622 case MipsOperand::Kind_MSA128HRegs:
1623 case MipsOperand::Kind_MSA128WRegs:
1624 case MipsOperand::Kind_MSA128DRegs:
1628 Parser.Lex(); // Eat the '$'.
1629 if (getLexer().getKind() == AsmToken::Identifier)
1630 RegName = Parser.getTok().getString().lower();
1632 return MatchOperand_ParseFail;
1634 int RegNum = matchMSA128RegisterName(RegName);
1636 if (RegNum < 0 || RegNum > 31)
1637 return MatchOperand_ParseFail;
1639 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1641 return MatchOperand_ParseFail;
1643 MipsOperand *Op = MipsOperand::CreateReg(RegVal, S,
1644 Parser.getTok().getLoc());
1645 Op->setRegKind(Kind);
1646 Operands.push_back(Op);
1648 Parser.Lex(); // Eat the register identifier.
1650 // MSA registers may be suffixed with an index in the form of:
1651 // 1) Immediate expression.
1652 // 2) General Purpose Register.
1654 // 1) copy_s.b $29,$w0[0]
1655 // 2) sld.b $w0,$w1[$1]
1657 if (Parser.getTok().isNot(AsmToken::LBrac))
1658 return MatchOperand_Success;
1660 MipsOperand *Mnemonic = static_cast<MipsOperand *>(Operands[0]);
1662 Operands.push_back(MipsOperand::CreateToken("[", Parser.getTok().getLoc()));
1663 Parser.Lex(); // Parse the '[' token.
1665 if (Parser.getTok().is(AsmToken::Dollar)) {
1666 // This must be a GPR.
1668 SMLoc VIdx = Parser.getTok().getLoc();
1669 Parser.Lex(); // Parse the '$' token.
1671 // GPR have aliases and we must account for that. Example: $30 == $fp
1672 if (getLexer().getKind() == AsmToken::Integer) {
1673 unsigned RegNum = Parser.getTok().getIntVal();
1674 int Reg = matchRegisterByNumber(
1675 RegNum, regKindToRegClass(MipsOperand::Kind_GPR32));
1677 Error(VIdx, "invalid general purpose register");
1678 return MatchOperand_ParseFail;
1681 RegOp = MipsOperand::CreateReg(Reg, VIdx, Parser.getTok().getLoc());
1682 } else if (getLexer().getKind() == AsmToken::Identifier) {
1684 std::string RegName = Parser.getTok().getString().lower();
1686 RegNum = matchCPURegisterName(RegName);
1688 Error(VIdx, "general purpose register expected");
1689 return MatchOperand_ParseFail;
1691 RegNum = getReg(regKindToRegClass(MipsOperand::Kind_GPR32), RegNum);
1692 RegOp = MipsOperand::CreateReg(RegNum, VIdx, Parser.getTok().getLoc());
1694 return MatchOperand_ParseFail;
1696 RegOp->setRegKind(MipsOperand::Kind_GPR32);
1697 Operands.push_back(RegOp);
1698 Parser.Lex(); // Eat the register identifier.
1700 if (Parser.getTok().isNot(AsmToken::RBrac))
1701 return MatchOperand_ParseFail;
1703 Operands.push_back(MipsOperand::CreateToken("]", Parser.getTok().getLoc()));
1704 Parser.Lex(); // Parse the ']' token.
1706 return MatchOperand_Success;
1709 // The index must be a constant expression then.
1710 SMLoc VIdx = Parser.getTok().getLoc();
1711 const MCExpr *ImmVal;
1713 if (getParser().parseExpression(ImmVal))
1714 return MatchOperand_ParseFail;
1716 const MCConstantExpr *expr = dyn_cast<MCConstantExpr>(ImmVal);
1717 if (!expr || !validateMSAIndex((int)expr->getValue(), Kind)) {
1718 Error(VIdx, "invalid immediate value");
1719 return MatchOperand_ParseFail;
1722 SMLoc E = Parser.getTok().getEndLoc();
1724 if (Parser.getTok().isNot(AsmToken::RBrac))
1725 return MatchOperand_ParseFail;
1727 bool insve = Mnemonic->getToken() == "insve.b" ||
1728 Mnemonic->getToken() == "insve.h" ||
1729 Mnemonic->getToken() == "insve.w" ||
1730 Mnemonic->getToken() == "insve.d";
1732 // The second vector index of insve instructions is always 0.
1733 if (insve && Operands.size() > 6) {
1734 if (expr->getValue() != 0) {
1735 Error(VIdx, "immediate value must be 0");
1736 return MatchOperand_ParseFail;
1738 Operands.push_back(MipsOperand::CreateToken("0", VIdx));
1740 Operands.push_back(MipsOperand::CreateImm(expr, VIdx, E));
1742 Operands.push_back(MipsOperand::CreateToken("]", Parser.getTok().getLoc()));
1744 Parser.Lex(); // Parse the ']' token.
1746 return MatchOperand_Success;
1749 MipsAsmParser::OperandMatchResultTy
1750 MipsAsmParser::parseMSACtrlRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1752 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1754 if (Kind != MipsOperand::Kind_MSA128CtrlRegs)
1755 return MatchOperand_NoMatch;
1757 if (Parser.getTok().isNot(AsmToken::Dollar))
1758 return MatchOperand_ParseFail;
1760 SMLoc S = Parser.getTok().getLoc();
1762 Parser.Lex(); // Eat the '$' symbol.
1765 if (getLexer().getKind() == AsmToken::Identifier)
1766 RegNum = matchMSA128CtrlRegisterName(Parser.getTok().getString().lower());
1767 else if (getLexer().getKind() == AsmToken::Integer)
1768 RegNum = Parser.getTok().getIntVal();
1770 return MatchOperand_ParseFail;
1772 if (RegNum < 0 || RegNum > 7)
1773 return MatchOperand_ParseFail;
1775 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1777 return MatchOperand_ParseFail;
1779 MipsOperand *RegOp = MipsOperand::CreateReg(RegVal, S,
1780 Parser.getTok().getLoc());
1781 RegOp->setRegKind(MipsOperand::Kind_MSA128CtrlRegs);
1782 Operands.push_back(RegOp);
1783 Parser.Lex(); // Eat the register identifier.
1785 return MatchOperand_Success;
1788 MipsAsmParser::OperandMatchResultTy
1789 MipsAsmParser::parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1792 return MatchOperand_NoMatch;
1793 return parseRegs(Operands, (int) MipsOperand::Kind_GPR64);
1796 MipsAsmParser::OperandMatchResultTy
1797 MipsAsmParser::parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1798 return parseRegs(Operands, (int) MipsOperand::Kind_GPR32);
1801 MipsAsmParser::OperandMatchResultTy
1802 MipsAsmParser::parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1805 return MatchOperand_NoMatch;
1806 return parseRegs(Operands, (int) MipsOperand::Kind_AFGR64Regs);
1809 MipsAsmParser::OperandMatchResultTy
1810 MipsAsmParser::parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1812 return MatchOperand_NoMatch;
1813 return parseRegs(Operands, (int) MipsOperand::Kind_FGR64Regs);
1816 MipsAsmParser::OperandMatchResultTy
1817 MipsAsmParser::parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1818 return parseRegs(Operands, (int) MipsOperand::Kind_FGR32Regs);
1821 MipsAsmParser::OperandMatchResultTy
1822 MipsAsmParser::parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1823 return parseRegs(Operands, (int) MipsOperand::Kind_FGRH32Regs);
1826 MipsAsmParser::OperandMatchResultTy
1827 MipsAsmParser::parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1828 return parseRegs(Operands, (int) MipsOperand::Kind_FCCRegs);
1831 MipsAsmParser::OperandMatchResultTy
1832 MipsAsmParser::parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1833 return parseRegs(Operands, (int) MipsOperand::Kind_ACC64DSP);
1836 MipsAsmParser::OperandMatchResultTy
1837 MipsAsmParser::parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1838 // If the first token is not '$' we have an error.
1839 if (Parser.getTok().isNot(AsmToken::Dollar))
1840 return MatchOperand_NoMatch;
1842 SMLoc S = Parser.getTok().getLoc();
1843 Parser.Lex(); // Eat the '$'
1845 const AsmToken &Tok = Parser.getTok(); // Get next token.
1847 if (Tok.isNot(AsmToken::Identifier))
1848 return MatchOperand_NoMatch;
1850 if (!Tok.getIdentifier().startswith("ac"))
1851 return MatchOperand_NoMatch;
1853 StringRef NumString = Tok.getIdentifier().substr(2);
1856 if (NumString.getAsInteger(10, IntVal))
1857 return MatchOperand_NoMatch;
1859 unsigned Reg = matchRegisterByNumber(IntVal, Mips::LO32DSPRegClassID);
1861 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1862 Op->setRegKind(MipsOperand::Kind_LO32DSP);
1863 Operands.push_back(Op);
1865 Parser.Lex(); // Eat the register number.
1866 return MatchOperand_Success;
1869 MipsAsmParser::OperandMatchResultTy
1870 MipsAsmParser::parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1871 // If the first token is not '$' we have an error.
1872 if (Parser.getTok().isNot(AsmToken::Dollar))
1873 return MatchOperand_NoMatch;
1875 SMLoc S = Parser.getTok().getLoc();
1876 Parser.Lex(); // Eat the '$'
1878 const AsmToken &Tok = Parser.getTok(); // Get next token.
1880 if (Tok.isNot(AsmToken::Identifier))
1881 return MatchOperand_NoMatch;
1883 if (!Tok.getIdentifier().startswith("ac"))
1884 return MatchOperand_NoMatch;
1886 StringRef NumString = Tok.getIdentifier().substr(2);
1889 if (NumString.getAsInteger(10, IntVal))
1890 return MatchOperand_NoMatch;
1892 unsigned Reg = matchRegisterByNumber(IntVal, Mips::HI32DSPRegClassID);
1894 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1895 Op->setRegKind(MipsOperand::Kind_HI32DSP);
1896 Operands.push_back(Op);
1898 Parser.Lex(); // Eat the register number.
1899 return MatchOperand_Success;
1902 MipsAsmParser::OperandMatchResultTy
1903 MipsAsmParser::parseCOP2(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1904 // If the first token is not '$' we have an error.
1905 if (Parser.getTok().isNot(AsmToken::Dollar))
1906 return MatchOperand_NoMatch;
1908 SMLoc S = Parser.getTok().getLoc();
1909 Parser.Lex(); // Eat the '$'
1911 const AsmToken &Tok = Parser.getTok(); // Get next token.
1913 if (Tok.isNot(AsmToken::Integer))
1914 return MatchOperand_NoMatch;
1916 unsigned IntVal = Tok.getIntVal();
1918 unsigned Reg = matchRegisterByNumber(IntVal, Mips::COP2RegClassID);
1920 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1921 Op->setRegKind(MipsOperand::Kind_COP2);
1922 Operands.push_back(Op);
1924 Parser.Lex(); // Eat the register number.
1925 return MatchOperand_Success;
1928 MipsAsmParser::OperandMatchResultTy
1929 MipsAsmParser::parseMSA128BRegs(
1930 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1931 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128BRegs);
1934 MipsAsmParser::OperandMatchResultTy
1935 MipsAsmParser::parseMSA128HRegs(
1936 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1937 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128HRegs);
1940 MipsAsmParser::OperandMatchResultTy
1941 MipsAsmParser::parseMSA128WRegs(
1942 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1943 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128WRegs);
1946 MipsAsmParser::OperandMatchResultTy
1947 MipsAsmParser::parseMSA128DRegs(
1948 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1949 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128DRegs);
1952 MipsAsmParser::OperandMatchResultTy
1953 MipsAsmParser::parseMSA128CtrlRegs(
1954 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1955 return parseMSACtrlRegs(Operands, (int) MipsOperand::Kind_MSA128CtrlRegs);
1958 bool MipsAsmParser::searchSymbolAlias(
1959 SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegKind) {
1961 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1963 SMLoc S = Parser.getTok().getLoc();
1965 if (Sym->isVariable())
1966 Expr = Sym->getVariableValue();
1969 if (Expr->getKind() == MCExpr::SymbolRef) {
1970 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind) RegKind;
1971 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
1972 const StringRef DefSymbol = Ref->getSymbol().getName();
1973 if (DefSymbol.startswith("$")) {
1975 APInt IntVal(32, -1);
1976 if (!DefSymbol.substr(1).getAsInteger(10, IntVal))
1977 RegNum = matchRegisterByNumber(IntVal.getZExtValue(),
1979 ? Mips::GPR64RegClassID
1980 : Mips::GPR32RegClassID);
1982 // Lookup for the register with the corresponding name.
1984 case MipsOperand::Kind_AFGR64Regs:
1985 case MipsOperand::Kind_FGR64Regs:
1986 RegNum = matchFPURegisterName(DefSymbol.substr(1));
1988 case MipsOperand::Kind_FGR32Regs:
1989 RegNum = matchFPURegisterName(DefSymbol.substr(1));
1991 case MipsOperand::Kind_GPR64:
1992 case MipsOperand::Kind_GPR32:
1994 RegNum = matchCPURegisterName(DefSymbol.substr(1));
1998 RegNum = getReg(regKindToRegClass(Kind), RegNum);
2002 MipsOperand *op = MipsOperand::CreateReg(RegNum, S,
2003 Parser.getTok().getLoc());
2004 op->setRegKind(Kind);
2005 Operands.push_back(op);
2009 } else if (Expr->getKind() == MCExpr::Constant) {
2011 const MCConstantExpr *Const = static_cast<const MCConstantExpr*>(Expr);
2012 MipsOperand *op = MipsOperand::CreateImm(Const, S,
2013 Parser.getTok().getLoc());
2014 Operands.push_back(op);
2021 MipsAsmParser::OperandMatchResultTy
2022 MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2023 return parseRegs(Operands, (int) MipsOperand::Kind_HWRegs);
2026 MipsAsmParser::OperandMatchResultTy
2027 MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2028 return parseRegs(Operands, (int) MipsOperand::Kind_CCRRegs);
2031 MipsAsmParser::OperandMatchResultTy
2032 MipsAsmParser::parseInvNum(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2033 const MCExpr *IdVal;
2034 // If the first token is '$' we may have register operand.
2035 if (Parser.getTok().is(AsmToken::Dollar))
2036 return MatchOperand_NoMatch;
2037 SMLoc S = Parser.getTok().getLoc();
2038 if (getParser().parseExpression(IdVal))
2039 return MatchOperand_ParseFail;
2040 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
2041 assert( MCE && "Unexpected MCExpr type.");
2042 int64_t Val = MCE->getValue();
2043 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2044 Operands.push_back(MipsOperand::CreateImm(
2045 MCConstantExpr::Create(0 - Val, getContext()), S, E));
2046 return MatchOperand_Success;
2049 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
2051 MCSymbolRefExpr::VariantKind VK
2052 = StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
2053 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
2054 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
2055 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
2056 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
2057 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
2058 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
2059 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
2060 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
2061 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
2062 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
2063 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
2064 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
2065 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
2066 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
2067 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
2068 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
2069 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
2070 .Default(MCSymbolRefExpr::VK_None);
2075 bool MipsAsmParser::
2076 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
2077 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2078 // Check if we have valid mnemonic
2079 if (!mnemonicIsValid(Name, 0)) {
2080 Parser.eatToEndOfStatement();
2081 return Error(NameLoc, "Unknown instruction");
2083 // First operand in MCInst is instruction mnemonic.
2084 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
2086 // Read the remaining operands.
2087 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2088 // Read the first operand.
2089 if (ParseOperand(Operands, Name)) {
2090 SMLoc Loc = getLexer().getLoc();
2091 Parser.eatToEndOfStatement();
2092 return Error(Loc, "unexpected token in argument list");
2095 while (getLexer().is(AsmToken::Comma)) {
2096 Parser.Lex(); // Eat the comma.
2097 // Parse and remember the operand.
2098 if (ParseOperand(Operands, Name)) {
2099 SMLoc Loc = getLexer().getLoc();
2100 Parser.eatToEndOfStatement();
2101 return Error(Loc, "unexpected token in argument list");
2105 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2106 SMLoc Loc = getLexer().getLoc();
2107 Parser.eatToEndOfStatement();
2108 return Error(Loc, "unexpected token in argument list");
2110 Parser.Lex(); // Consume the EndOfStatement.
2114 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
2115 SMLoc Loc = getLexer().getLoc();
2116 Parser.eatToEndOfStatement();
2117 return Error(Loc, ErrorMsg);
2120 bool MipsAsmParser::parseSetNoAtDirective() {
2121 // Line should look like: ".set noat".
2123 Options.setATReg(0);
2126 // If this is not the end of the statement, report an error.
2127 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2128 reportParseError("unexpected token in statement");
2131 Parser.Lex(); // Consume the EndOfStatement.
2135 bool MipsAsmParser::parseSetAtDirective() {
2136 // Line can be .set at - defaults to $1
2140 if (getLexer().is(AsmToken::EndOfStatement)) {
2141 Options.setATReg(1);
2142 Parser.Lex(); // Consume the EndOfStatement.
2144 } else if (getLexer().is(AsmToken::Equal)) {
2145 getParser().Lex(); // Eat the '='.
2146 if (getLexer().isNot(AsmToken::Dollar)) {
2147 reportParseError("unexpected token in statement");
2150 Parser.Lex(); // Eat the '$'.
2151 const AsmToken &Reg = Parser.getTok();
2152 if (Reg.is(AsmToken::Identifier)) {
2153 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
2154 } else if (Reg.is(AsmToken::Integer)) {
2155 AtRegNo = Reg.getIntVal();
2157 reportParseError("unexpected token in statement");
2161 if (AtRegNo < 1 || AtRegNo > 31) {
2162 reportParseError("unexpected token in statement");
2166 if (!Options.setATReg(AtRegNo)) {
2167 reportParseError("unexpected token in statement");
2170 getParser().Lex(); // Eat the register.
2172 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2173 reportParseError("unexpected token in statement");
2176 Parser.Lex(); // Consume the EndOfStatement.
2179 reportParseError("unexpected token in statement");
2184 bool MipsAsmParser::parseSetReorderDirective() {
2186 // If this is not the end of the statement, report an error.
2187 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2188 reportParseError("unexpected token in statement");
2191 Options.setReorder();
2192 Parser.Lex(); // Consume the EndOfStatement.
2196 bool MipsAsmParser::parseSetNoReorderDirective() {
2198 // If this is not the end of the statement, report an error.
2199 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2200 reportParseError("unexpected token in statement");
2203 Options.setNoreorder();
2204 Parser.Lex(); // Consume the EndOfStatement.
2208 bool MipsAsmParser::parseSetMacroDirective() {
2210 // If this is not the end of the statement, report an error.
2211 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2212 reportParseError("unexpected token in statement");
2216 Parser.Lex(); // Consume the EndOfStatement.
2220 bool MipsAsmParser::parseSetNoMacroDirective() {
2222 // If this is not the end of the statement, report an error.
2223 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2224 reportParseError("`noreorder' must be set before `nomacro'");
2227 if (Options.isReorder()) {
2228 reportParseError("`noreorder' must be set before `nomacro'");
2231 Options.setNomacro();
2232 Parser.Lex(); // Consume the EndOfStatement.
2236 bool MipsAsmParser::parseSetAssignment() {
2238 const MCExpr *Value;
2240 if (Parser.parseIdentifier(Name))
2241 reportParseError("expected identifier after .set");
2243 if (getLexer().isNot(AsmToken::Comma))
2244 return reportParseError("unexpected token in .set directive");
2247 if (getLexer().is(AsmToken::Dollar)) {
2249 SMLoc DollarLoc = getLexer().getLoc();
2250 // Consume the dollar sign, and check for a following identifier.
2252 // We have a '$' followed by something, make sure they are adjacent.
2253 if (DollarLoc.getPointer() + 1 != getTok().getLoc().getPointer())
2255 StringRef Res = StringRef(DollarLoc.getPointer(),
2256 getTok().getEndLoc().getPointer() - DollarLoc.getPointer());
2257 Symbol = getContext().GetOrCreateSymbol(Res);
2259 Value = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
2261 } else if (Parser.parseExpression(Value))
2262 return reportParseError("expected valid expression after comma");
2264 // Check if the Name already exists as a symbol.
2265 MCSymbol *Sym = getContext().LookupSymbol(Name);
2267 return reportParseError("symbol already defined");
2268 Sym = getContext().GetOrCreateSymbol(Name);
2269 Sym->setVariableValue(Value);
2274 bool MipsAsmParser::parseDirectiveSet() {
2276 // Get the next token.
2277 const AsmToken &Tok = Parser.getTok();
2279 if (Tok.getString() == "noat") {
2280 return parseSetNoAtDirective();
2281 } else if (Tok.getString() == "at") {
2282 return parseSetAtDirective();
2283 } else if (Tok.getString() == "reorder") {
2284 return parseSetReorderDirective();
2285 } else if (Tok.getString() == "noreorder") {
2286 return parseSetNoReorderDirective();
2287 } else if (Tok.getString() == "macro") {
2288 return parseSetMacroDirective();
2289 } else if (Tok.getString() == "nomacro") {
2290 return parseSetNoMacroDirective();
2291 } else if (Tok.getString() == "nomips16") {
2292 // Ignore this directive for now.
2293 Parser.eatToEndOfStatement();
2295 } else if (Tok.getString() == "nomicromips") {
2296 // Ignore this directive for now.
2297 Parser.eatToEndOfStatement();
2300 // It is just an identifier, look for an assignment.
2301 parseSetAssignment();
2308 bool MipsAsmParser::parseDirectiveMipsHackStocg() {
2309 MCAsmParser &Parser = getParser();
2311 if (Parser.parseIdentifier(Name))
2312 reportParseError("expected identifier");
2314 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
2315 if (getLexer().isNot(AsmToken::Comma))
2316 return TokError("unexpected token");
2320 if (Parser.parseAbsoluteExpression(Flags))
2321 return TokError("unexpected token");
2323 getTargetStreamer().emitMipsHackSTOCG(Sym, Flags);
2327 bool MipsAsmParser::parseDirectiveMipsHackELFFlags() {
2329 if (Parser.parseAbsoluteExpression(Flags))
2330 return TokError("unexpected token");
2332 getTargetStreamer().emitMipsHackELFFlags(Flags);
2336 /// parseDirectiveWord
2337 /// ::= .word [ expression (, expression)* ]
2338 bool MipsAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
2339 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2341 const MCExpr *Value;
2342 if (getParser().parseExpression(Value))
2345 getParser().getStreamer().EmitValue(Value, Size);
2347 if (getLexer().is(AsmToken::EndOfStatement))
2350 // FIXME: Improve diagnostic.
2351 if (getLexer().isNot(AsmToken::Comma))
2352 return Error(L, "unexpected token in directive");
2361 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
2363 StringRef IDVal = DirectiveID.getString();
2365 if (IDVal == ".ent") {
2366 // Ignore this directive for now.
2371 if (IDVal == ".end") {
2372 // Ignore this directive for now.
2377 if (IDVal == ".frame") {
2378 // Ignore this directive for now.
2379 Parser.eatToEndOfStatement();
2383 if (IDVal == ".set") {
2384 return parseDirectiveSet();
2387 if (IDVal == ".fmask") {
2388 // Ignore this directive for now.
2389 Parser.eatToEndOfStatement();
2393 if (IDVal == ".mask") {
2394 // Ignore this directive for now.
2395 Parser.eatToEndOfStatement();
2399 if (IDVal == ".gpword") {
2400 // Ignore this directive for now.
2401 Parser.eatToEndOfStatement();
2405 if (IDVal == ".word") {
2406 parseDirectiveWord(4, DirectiveID.getLoc());
2410 if (IDVal == ".mips_hack_stocg")
2411 return parseDirectiveMipsHackStocg();
2413 if (IDVal == ".mips_hack_elf_flags")
2414 return parseDirectiveMipsHackELFFlags();
2419 extern "C" void LLVMInitializeMipsAsmParser() {
2420 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
2421 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
2422 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
2423 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
2426 #define GET_REGISTER_MATCHER
2427 #define GET_MATCHER_IMPLEMENTATION
2428 #include "MipsGenAsmMatcher.inc"