1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCTargetDesc.h"
11 #include "MipsRegisterInfo.h"
12 #include "MipsTargetStreamer.h"
13 #include "llvm/ADT/StringSwitch.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCParser/MCAsmLexer.h"
18 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
19 #include "llvm/MC/MCStreamer.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/MC/MCTargetAsmParser.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/ADT/APInt.h"
33 class MipsAssemblerOptions {
35 MipsAssemblerOptions():
36 aTReg(1), reorder(true), macro(true) {
39 unsigned getATRegNum() {return aTReg;}
40 bool setATReg(unsigned Reg);
42 bool isReorder() {return reorder;}
43 void setReorder() {reorder = true;}
44 void setNoreorder() {reorder = false;}
46 bool isMacro() {return macro;}
47 void setMacro() {macro = true;}
48 void setNomacro() {macro = false;}
58 class MipsAsmParser : public MCTargetAsmParser {
60 MipsTargetStreamer &getTargetStreamer() {
61 MCTargetStreamer &TS = Parser.getStreamer().getTargetStreamer();
62 return static_cast<MipsTargetStreamer &>(TS);
67 MipsAssemblerOptions Options;
68 bool hasConsumedDollar;
70 #define GET_ASSEMBLER_HEADER
71 #include "MipsGenAsmMatcher.inc"
73 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
74 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
75 MCStreamer &Out, unsigned &ErrorInfo,
76 bool MatchingInlineAsm);
78 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
80 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
82 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
84 bool ParseDirective(AsmToken DirectiveID);
86 MipsAsmParser::OperandMatchResultTy
87 parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
90 MipsAsmParser::OperandMatchResultTy
91 parseMSARegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
94 MipsAsmParser::OperandMatchResultTy
95 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
97 bool parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands, int RegKind);
99 MipsAsmParser::OperandMatchResultTy
100 parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
102 MipsAsmParser::OperandMatchResultTy
103 parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
105 MipsAsmParser::OperandMatchResultTy
106 parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
108 MipsAsmParser::OperandMatchResultTy
109 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
111 MipsAsmParser::OperandMatchResultTy
112 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
114 MipsAsmParser::OperandMatchResultTy
115 parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
117 MipsAsmParser::OperandMatchResultTy
118 parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
120 MipsAsmParser::OperandMatchResultTy
121 parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
123 MipsAsmParser::OperandMatchResultTy
124 parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
126 MipsAsmParser::OperandMatchResultTy
127 parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
129 MipsAsmParser::OperandMatchResultTy
130 parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
132 MipsAsmParser::OperandMatchResultTy
133 parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
135 MipsAsmParser::OperandMatchResultTy
136 parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
138 MipsAsmParser::OperandMatchResultTy
139 parseCOP2(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
141 MipsAsmParser::OperandMatchResultTy
142 parseMSA128BRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
144 MipsAsmParser::OperandMatchResultTy
145 parseMSA128HRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
147 MipsAsmParser::OperandMatchResultTy
148 parseMSA128WRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
150 MipsAsmParser::OperandMatchResultTy
151 parseMSA128DRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
153 MipsAsmParser::OperandMatchResultTy
154 parseInvNum(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
156 bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
159 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &,
162 int tryParseRegister(bool is64BitReg);
164 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
167 bool needsExpansion(MCInst &Inst);
169 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
170 SmallVectorImpl<MCInst> &Instructions);
171 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
172 SmallVectorImpl<MCInst> &Instructions);
173 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
174 SmallVectorImpl<MCInst> &Instructions);
175 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
176 SmallVectorImpl<MCInst> &Instructions);
177 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
178 SmallVectorImpl<MCInst> &Instructions,
179 bool isLoad,bool isImmOpnd);
180 bool reportParseError(StringRef ErrorMsg);
182 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
183 bool parseRelocOperand(const MCExpr *&Res);
185 const MCExpr* evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
187 bool isEvaluated(const MCExpr *Expr);
188 bool parseDirectiveSet();
189 bool parseDirectiveMipsHackStocg();
190 bool parseDirectiveMipsHackELFFlags();
192 bool parseSetAtDirective();
193 bool parseSetNoAtDirective();
194 bool parseSetMacroDirective();
195 bool parseSetNoMacroDirective();
196 bool parseSetReorderDirective();
197 bool parseSetNoReorderDirective();
199 bool parseSetAssignment();
201 bool parseDirectiveWord(unsigned Size, SMLoc L);
203 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
205 bool isMips64() const {
206 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
209 bool isFP64() const {
210 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
214 return STI.getFeatureBits() & Mips::FeatureN64;
217 int matchRegisterName(StringRef Symbol, bool is64BitReg);
219 int matchCPURegisterName(StringRef Symbol);
221 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
223 int matchFPURegisterName(StringRef Name);
225 int matchFCCRegisterName(StringRef Name);
227 int matchACRegisterName(StringRef Name);
229 int matchMSA128RegisterName(StringRef Name);
231 int regKindToRegClass(int RegKind);
233 unsigned getReg(int RC, int RegNo);
237 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
238 SmallVectorImpl<MCInst> &Instructions);
240 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
241 const MCInstrInfo &MII)
242 : MCTargetAsmParser(), STI(sti), Parser(parser),
243 hasConsumedDollar(false) {
244 // Initialize the set of available features.
245 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
248 MCAsmParser &getParser() const { return Parser; }
249 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
256 /// MipsOperand - Instances of this class represent a parsed Mips machine
258 class MipsOperand : public MCParsedAsmOperand {
294 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
322 SMLoc StartLoc, EndLoc;
325 void addRegOperands(MCInst &Inst, unsigned N) const {
326 assert(N == 1 && "Invalid number of operands!");
327 Inst.addOperand(MCOperand::CreateReg(getReg()));
330 void addPtrRegOperands(MCInst &Inst, unsigned N) const {
331 assert(N == 1 && "Invalid number of operands!");
332 Inst.addOperand(MCOperand::CreateReg(getPtrReg()));
335 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
336 // Add as immediate when possible. Null MCExpr = 0.
338 Inst.addOperand(MCOperand::CreateImm(0));
339 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
340 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
342 Inst.addOperand(MCOperand::CreateExpr(Expr));
345 void addImmOperands(MCInst &Inst, unsigned N) const {
346 assert(N == 1 && "Invalid number of operands!");
347 const MCExpr *Expr = getImm();
351 void addMemOperands(MCInst &Inst, unsigned N) const {
352 assert(N == 2 && "Invalid number of operands!");
354 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
356 const MCExpr *Expr = getMemOff();
360 bool isReg() const { return Kind == k_Register; }
361 bool isImm() const { return Kind == k_Immediate; }
362 bool isToken() const { return Kind == k_Token; }
363 bool isMem() const { return Kind == k_Memory; }
364 bool isPtrReg() const { return Kind == k_PtrReg; }
365 bool isInvNum() const { return Kind == k_Immediate; }
367 StringRef getToken() const {
368 assert(Kind == k_Token && "Invalid access!");
369 return StringRef(Tok.Data, Tok.Length);
372 unsigned getReg() const {
373 assert((Kind == k_Register) && "Invalid access!");
377 unsigned getPtrReg() const {
378 assert((Kind == k_PtrReg) && "Invalid access!");
382 void setRegKind(RegisterKind RegKind) {
383 assert((Kind == k_Register || Kind == k_PtrReg) && "Invalid access!");
387 const MCExpr *getImm() const {
388 assert((Kind == k_Immediate) && "Invalid access!");
392 unsigned getMemBase() const {
393 assert((Kind == k_Memory) && "Invalid access!");
397 const MCExpr *getMemOff() const {
398 assert((Kind == k_Memory) && "Invalid access!");
402 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
403 MipsOperand *Op = new MipsOperand(k_Token);
404 Op->Tok.Data = Str.data();
405 Op->Tok.Length = Str.size();
411 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
412 MipsOperand *Op = new MipsOperand(k_Register);
413 Op->Reg.RegNum = RegNum;
419 static MipsOperand *CreatePtrReg(unsigned RegNum, SMLoc S, SMLoc E) {
420 MipsOperand *Op = new MipsOperand(k_PtrReg);
421 Op->Reg.RegNum = RegNum;
427 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
428 MipsOperand *Op = new MipsOperand(k_Immediate);
435 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off,
437 MipsOperand *Op = new MipsOperand(k_Memory);
445 bool isGPR32Asm() const {
446 return Kind == k_Register && Reg.Kind == Kind_GPR32;
448 void addRegAsmOperands(MCInst &Inst, unsigned N) const {
449 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
452 bool isGPR64Asm() const {
453 return Kind == k_Register && Reg.Kind == Kind_GPR64;
456 bool isHWRegsAsm() const {
457 assert((Kind == k_Register) && "Invalid access!");
458 return Reg.Kind == Kind_HWRegs;
461 bool isCCRAsm() const {
462 assert((Kind == k_Register) && "Invalid access!");
463 return Reg.Kind == Kind_CCRRegs;
466 bool isAFGR64Asm() const {
467 return Kind == k_Register && Reg.Kind == Kind_AFGR64Regs;
470 bool isFGR64Asm() const {
471 return Kind == k_Register && Reg.Kind == Kind_FGR64Regs;
474 bool isFGR32Asm() const {
475 return (Kind == k_Register) && Reg.Kind == Kind_FGR32Regs;
478 bool isFGRH32Asm() const {
479 return (Kind == k_Register) && Reg.Kind == Kind_FGRH32Regs;
482 bool isFCCRegsAsm() const {
483 return (Kind == k_Register) && Reg.Kind == Kind_FCCRegs;
486 bool isACC64DSPAsm() const {
487 return Kind == k_Register && Reg.Kind == Kind_ACC64DSP;
490 bool isLO32DSPAsm() const {
491 return Kind == k_Register && Reg.Kind == Kind_LO32DSP;
494 bool isHI32DSPAsm() const {
495 return Kind == k_Register && Reg.Kind == Kind_HI32DSP;
498 bool isCOP2Asm() const {
499 return Kind == k_Register && Reg.Kind == Kind_COP2;
502 bool isMSA128BAsm() const {
503 return Kind == k_Register && Reg.Kind == Kind_MSA128BRegs;
506 bool isMSA128HAsm() const {
507 return Kind == k_Register && Reg.Kind == Kind_MSA128HRegs;
510 bool isMSA128WAsm() const {
511 return Kind == k_Register && Reg.Kind == Kind_MSA128WRegs;
514 bool isMSA128DAsm() const {
515 return Kind == k_Register && Reg.Kind == Kind_MSA128DRegs;
518 /// getStartLoc - Get the location of the first token of this operand.
519 SMLoc getStartLoc() const {
522 /// getEndLoc - Get the location of the last token of this operand.
523 SMLoc getEndLoc() const {
527 virtual void print(raw_ostream &OS) const {
528 llvm_unreachable("unimplemented!");
530 }; // class MipsOperand
534 extern const MCInstrDesc MipsInsts[];
536 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
537 return MipsInsts[Opcode];
540 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
541 SmallVectorImpl<MCInst> &Instructions) {
542 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
544 if (MCID.hasDelaySlot() && Options.isReorder()) {
545 // If this instruction has a delay slot and .set reorder is active,
546 // emit a NOP after it.
547 Instructions.push_back(Inst);
549 NopInst.setOpcode(Mips::SLL);
550 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
551 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
552 NopInst.addOperand(MCOperand::CreateImm(0));
553 Instructions.push_back(NopInst);
557 if (MCID.mayLoad() || MCID.mayStore()) {
558 // Check the offset of memory operand, if it is a symbol
559 // reference or immediate we may have to expand instructions.
560 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
561 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
562 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY)
563 || (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
564 MCOperand &Op = Inst.getOperand(i);
566 int MemOffset = Op.getImm();
567 if (MemOffset < -32768 || MemOffset > 32767) {
568 // Offset can't exceed 16bit value.
569 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
572 } else if (Op.isExpr()) {
573 const MCExpr *Expr = Op.getExpr();
574 if (Expr->getKind() == MCExpr::SymbolRef) {
575 const MCSymbolRefExpr *SR =
576 static_cast<const MCSymbolRefExpr*>(Expr);
577 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
579 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
582 } else if (!isEvaluated(Expr)) {
583 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
591 if (needsExpansion(Inst))
592 expandInstruction(Inst, IDLoc, Instructions);
594 Instructions.push_back(Inst);
599 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
601 switch (Inst.getOpcode()) {
602 case Mips::LoadImm32Reg:
603 case Mips::LoadAddr32Imm:
604 case Mips::LoadAddr32Reg:
611 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
612 SmallVectorImpl<MCInst> &Instructions) {
613 switch (Inst.getOpcode()) {
614 case Mips::LoadImm32Reg:
615 return expandLoadImm(Inst, IDLoc, Instructions);
616 case Mips::LoadAddr32Imm:
617 return expandLoadAddressImm(Inst, IDLoc, Instructions);
618 case Mips::LoadAddr32Reg:
619 return expandLoadAddressReg(Inst, IDLoc, Instructions);
623 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
624 SmallVectorImpl<MCInst> &Instructions) {
626 const MCOperand &ImmOp = Inst.getOperand(1);
627 assert(ImmOp.isImm() && "expected immediate operand kind");
628 const MCOperand &RegOp = Inst.getOperand(0);
629 assert(RegOp.isReg() && "expected register operand kind");
631 int ImmValue = ImmOp.getImm();
632 tmpInst.setLoc(IDLoc);
633 if (0 <= ImmValue && ImmValue <= 65535) {
634 // For 0 <= j <= 65535.
635 // li d,j => ori d,$zero,j
636 tmpInst.setOpcode(Mips::ORi);
637 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
638 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
639 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
640 Instructions.push_back(tmpInst);
641 } else if (ImmValue < 0 && ImmValue >= -32768) {
642 // For -32768 <= j < 0.
643 // li d,j => addiu d,$zero,j
644 tmpInst.setOpcode(Mips::ADDiu);
645 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
646 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
647 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
648 Instructions.push_back(tmpInst);
650 // For any other value of j that is representable as a 32-bit integer.
651 // li d,j => lui d,hi16(j)
653 tmpInst.setOpcode(Mips::LUi);
654 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
655 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
656 Instructions.push_back(tmpInst);
658 tmpInst.setOpcode(Mips::ORi);
659 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
660 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
661 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
662 tmpInst.setLoc(IDLoc);
663 Instructions.push_back(tmpInst);
667 void MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
668 SmallVectorImpl<MCInst> &Instructions) {
670 const MCOperand &ImmOp = Inst.getOperand(2);
671 assert(ImmOp.isImm() && "expected immediate operand kind");
672 const MCOperand &SrcRegOp = Inst.getOperand(1);
673 assert(SrcRegOp.isReg() && "expected register operand kind");
674 const MCOperand &DstRegOp = Inst.getOperand(0);
675 assert(DstRegOp.isReg() && "expected register operand kind");
676 int ImmValue = ImmOp.getImm();
677 if (-32768 <= ImmValue && ImmValue <= 65535) {
678 // For -32768 <= j <= 65535.
679 // la d,j(s) => addiu d,s,j
680 tmpInst.setOpcode(Mips::ADDiu);
681 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
682 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
683 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
684 Instructions.push_back(tmpInst);
686 // For any other value of j that is representable as a 32-bit integer.
687 // la d,j(s) => lui d,hi16(j)
690 tmpInst.setOpcode(Mips::LUi);
691 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
692 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
693 Instructions.push_back(tmpInst);
695 tmpInst.setOpcode(Mips::ORi);
696 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
697 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
698 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
699 Instructions.push_back(tmpInst);
701 tmpInst.setOpcode(Mips::ADDu);
702 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
703 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
704 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
705 Instructions.push_back(tmpInst);
709 void MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
710 SmallVectorImpl<MCInst> &Instructions) {
712 const MCOperand &ImmOp = Inst.getOperand(1);
713 assert(ImmOp.isImm() && "expected immediate operand kind");
714 const MCOperand &RegOp = Inst.getOperand(0);
715 assert(RegOp.isReg() && "expected register operand kind");
716 int ImmValue = ImmOp.getImm();
717 if (-32768 <= ImmValue && ImmValue <= 65535) {
718 // For -32768 <= j <= 65535.
719 // la d,j => addiu d,$zero,j
720 tmpInst.setOpcode(Mips::ADDiu);
721 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
722 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
723 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
724 Instructions.push_back(tmpInst);
726 // For any other value of j that is representable as a 32-bit integer.
727 // la d,j => lui d,hi16(j)
729 tmpInst.setOpcode(Mips::LUi);
730 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
731 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
732 Instructions.push_back(tmpInst);
734 tmpInst.setOpcode(Mips::ORi);
735 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
736 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
737 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
738 Instructions.push_back(tmpInst);
742 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
743 SmallVectorImpl<MCInst> &Instructions, bool isLoad, bool isImmOpnd) {
744 const MCSymbolRefExpr *SR;
746 unsigned ImmOffset, HiOffset, LoOffset;
747 const MCExpr *ExprOffset;
749 unsigned AtRegNum = getReg((isMips64()) ? Mips::GPR64RegClassID
750 : Mips::GPR32RegClassID, getATReg());
751 // 1st operand is either the source or destination register.
752 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
753 unsigned RegOpNum = Inst.getOperand(0).getReg();
754 // 2nd operand is the base register.
755 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
756 unsigned BaseRegNum = Inst.getOperand(1).getReg();
757 // 3rd operand is either an immediate or expression.
759 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
760 ImmOffset = Inst.getOperand(2).getImm();
761 LoOffset = ImmOffset & 0x0000ffff;
762 HiOffset = (ImmOffset & 0xffff0000) >> 16;
763 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
764 if (LoOffset & 0x8000)
767 ExprOffset = Inst.getOperand(2).getExpr();
768 // All instructions will have the same location.
769 TempInst.setLoc(IDLoc);
770 // 1st instruction in expansion is LUi. For load instruction we can use
771 // the dst register as a temporary if base and dst are different,
772 // but for stores we must use $at.
773 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
774 TempInst.setOpcode(Mips::LUi);
775 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
777 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
779 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
780 SR = static_cast<const MCSymbolRefExpr*>(ExprOffset);
781 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
782 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
784 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
786 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
787 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
790 // Add the instruction to the list.
791 Instructions.push_back(TempInst);
792 // Prepare TempInst for next instruction.
794 // Add temp register to base.
795 TempInst.setOpcode(Mips::ADDu);
796 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
797 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
798 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
799 Instructions.push_back(TempInst);
801 // And finaly, create original instruction with low part
802 // of offset and new base.
803 TempInst.setOpcode(Inst.getOpcode());
804 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
805 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
807 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
809 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
810 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
811 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
813 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
815 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
816 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
819 Instructions.push_back(TempInst);
824 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
825 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
826 MCStreamer &Out, unsigned &ErrorInfo,
827 bool MatchingInlineAsm) {
829 SmallVector<MCInst, 8> Instructions;
830 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
833 switch (MatchResult) {
836 case Match_Success: {
837 if (processInstruction(Inst, IDLoc, Instructions))
839 for (unsigned i = 0; i < Instructions.size(); i++)
840 Out.EmitInstruction(Instructions[i]);
843 case Match_MissingFeature:
844 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
846 case Match_InvalidOperand: {
847 SMLoc ErrorLoc = IDLoc;
848 if (ErrorInfo != ~0U) {
849 if (ErrorInfo >= Operands.size())
850 return Error(IDLoc, "too few operands for instruction");
852 ErrorLoc = ((MipsOperand*) Operands[ErrorInfo])->getStartLoc();
853 if (ErrorLoc == SMLoc())
857 return Error(ErrorLoc, "invalid operand for instruction");
859 case Match_MnemonicFail:
860 return Error(IDLoc, "invalid instruction");
865 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
871 CC = StringSwitch<unsigned>(Name)
905 // Although SGI documentation just cuts out t0-t3 for n32/n64,
906 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
907 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
908 if (isMips64() && 8 <= CC && CC <= 11)
911 if (CC == -1 && isMips64())
912 CC = StringSwitch<unsigned>(Name)
925 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
927 if (Name[0] == 'f') {
928 StringRef NumString = Name.substr(1);
930 if (NumString.getAsInteger(10, IntVal))
931 return -1; // This is not an integer.
932 if (IntVal > 31) // Maximum index for fpu register.
939 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
941 if (Name.startswith("fcc")) {
942 StringRef NumString = Name.substr(3);
944 if (NumString.getAsInteger(10, IntVal))
945 return -1; // This is not an integer.
946 if (IntVal > 7) // There are only 8 fcc registers.
953 int MipsAsmParser::matchACRegisterName(StringRef Name) {
955 if (Name.startswith("ac")) {
956 StringRef NumString = Name.substr(2);
958 if (NumString.getAsInteger(10, IntVal))
959 return -1; // This is not an integer.
960 if (IntVal > 3) // There are only 3 acc registers.
967 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
970 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal))
979 int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
982 CC = matchCPURegisterName(Name);
984 return matchRegisterByNumber(CC, is64BitReg ? Mips::GPR64RegClassID
985 : Mips::GPR32RegClassID);
986 CC = matchFPURegisterName(Name);
987 //TODO: decide about fpu register class
989 return matchRegisterByNumber(CC, isFP64() ? Mips::FGR64RegClassID
990 : Mips::FGR32RegClassID);
991 return matchMSA128RegisterName(Name);
994 int MipsAsmParser::regKindToRegClass(int RegKind) {
997 case MipsOperand::Kind_GPR32: return Mips::GPR32RegClassID;
998 case MipsOperand::Kind_GPR64: return Mips::GPR64RegClassID;
999 case MipsOperand::Kind_HWRegs: return Mips::HWRegsRegClassID;
1000 case MipsOperand::Kind_FGR32Regs: return Mips::FGR32RegClassID;
1001 case MipsOperand::Kind_FGRH32Regs: return Mips::FGRH32RegClassID;
1002 case MipsOperand::Kind_FGR64Regs: return Mips::FGR64RegClassID;
1003 case MipsOperand::Kind_AFGR64Regs: return Mips::AFGR64RegClassID;
1004 case MipsOperand::Kind_CCRRegs: return Mips::CCRRegClassID;
1005 case MipsOperand::Kind_ACC64DSP: return Mips::ACC64DSPRegClassID;
1006 case MipsOperand::Kind_FCCRegs: return Mips::FCCRegClassID;
1007 case MipsOperand::Kind_MSA128BRegs: return Mips::MSA128BRegClassID;
1008 case MipsOperand::Kind_MSA128HRegs: return Mips::MSA128HRegClassID;
1009 case MipsOperand::Kind_MSA128WRegs: return Mips::MSA128WRegClassID;
1010 case MipsOperand::Kind_MSA128DRegs: return Mips::MSA128DRegClassID;
1016 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
1024 int MipsAsmParser::getATReg() {
1025 return Options.getATRegNum();
1028 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
1029 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1032 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
1034 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs())
1037 return getReg(RegClass, RegNum);
1040 int MipsAsmParser::tryParseRegister(bool is64BitReg) {
1041 const AsmToken &Tok = Parser.getTok();
1044 if (Tok.is(AsmToken::Identifier)) {
1045 std::string lowerCase = Tok.getString().lower();
1046 RegNum = matchRegisterName(lowerCase, is64BitReg);
1047 } else if (Tok.is(AsmToken::Integer))
1048 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
1049 is64BitReg ? Mips::GPR64RegClassID : Mips::GPR32RegClassID);
1053 bool MipsAsmParser::tryParseRegisterOperand(
1054 SmallVectorImpl<MCParsedAsmOperand*> &Operands, bool is64BitReg) {
1056 SMLoc S = Parser.getTok().getLoc();
1059 RegNo = tryParseRegister(is64BitReg);
1063 Operands.push_back(MipsOperand::CreateReg(RegNo, S,
1064 Parser.getTok().getLoc()));
1065 Parser.Lex(); // Eat register token.
1069 bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
1070 StringRef Mnemonic) {
1071 // Check if the current operand has a custom associated parser, if so, try to
1072 // custom parse the operand, or fallback to the general approach.
1073 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1074 if (ResTy == MatchOperand_Success)
1076 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1077 // there was a match, but an error occurred, in which case, just return that
1078 // the operand parsing failed.
1079 if (ResTy == MatchOperand_ParseFail)
1082 switch (getLexer().getKind()) {
1084 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1086 case AsmToken::Dollar: {
1087 // Parse the register.
1088 SMLoc S = Parser.getTok().getLoc();
1089 Parser.Lex(); // Eat dollar token.
1090 // Parse the register operand.
1091 if (!tryParseRegisterOperand(Operands, isMips64())) {
1092 if (getLexer().is(AsmToken::LParen)) {
1093 // Check if it is indexed addressing operand.
1094 Operands.push_back(MipsOperand::CreateToken("(", S));
1095 Parser.Lex(); // Eat the parenthesis.
1096 if (getLexer().isNot(AsmToken::Dollar))
1099 Parser.Lex(); // Eat the dollar
1100 if (tryParseRegisterOperand(Operands, isMips64()))
1103 if (!getLexer().is(AsmToken::RParen))
1106 S = Parser.getTok().getLoc();
1107 Operands.push_back(MipsOperand::CreateToken(")", S));
1112 // Maybe it is a symbol reference.
1113 StringRef Identifier;
1114 if (Parser.parseIdentifier(Identifier))
1117 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1119 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1121 // Otherwise create a symbol reference.
1122 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
1125 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
1128 case AsmToken::Identifier:
1129 // Look for the existing symbol, we should check if
1130 // we need to assigne the propper RegisterKind.
1131 if (searchSymbolAlias(Operands, MipsOperand::Kind_None))
1133 // Else drop to expression parsing.
1134 case AsmToken::LParen:
1135 case AsmToken::Minus:
1136 case AsmToken::Plus:
1137 case AsmToken::Integer:
1138 case AsmToken::String: {
1139 // Quoted label names.
1140 const MCExpr *IdVal;
1141 SMLoc S = Parser.getTok().getLoc();
1142 if (getParser().parseExpression(IdVal))
1144 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1145 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1148 case AsmToken::Percent: {
1149 // It is a symbol reference or constant expression.
1150 const MCExpr *IdVal;
1151 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1152 if (parseRelocOperand(IdVal))
1155 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1157 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1159 } // case AsmToken::Percent
1160 } // switch(getLexer().getKind())
1164 const MCExpr* MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1165 StringRef RelocStr) {
1167 // Check the type of the expression.
1168 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1169 // It's a constant, evaluate lo or hi value.
1170 if (RelocStr == "lo") {
1171 short Val = MCE->getValue();
1172 Res = MCConstantExpr::Create(Val, getContext());
1173 } else if (RelocStr == "hi") {
1174 int Val = MCE->getValue();
1175 int LoSign = Val & 0x8000;
1176 Val = (Val & 0xffff0000) >> 16;
1177 // Lower part is treated as a signed int, so if it is negative
1178 // we must add 1 to the hi part to compensate.
1181 Res = MCConstantExpr::Create(Val, getContext());
1183 llvm_unreachable("Invalid RelocStr value");
1188 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1189 // It's a symbol, create a symbolic expression from the symbol.
1190 StringRef Symbol = MSRE->getSymbol().getName();
1191 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1192 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1196 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1197 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1198 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1199 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1203 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1204 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1205 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1208 // Just return the original expression.
1212 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1214 switch (Expr->getKind()) {
1215 case MCExpr::Constant:
1217 case MCExpr::SymbolRef:
1218 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1219 case MCExpr::Binary:
1220 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1221 if (!isEvaluated(BE->getLHS()))
1223 return isEvaluated(BE->getRHS());
1226 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1233 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1234 Parser.Lex(); // Eat the % token.
1235 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1236 if (Tok.isNot(AsmToken::Identifier))
1239 std::string Str = Tok.getIdentifier().str();
1241 Parser.Lex(); // Eat the identifier.
1242 // Now make an expression from the rest of the operand.
1243 const MCExpr *IdVal;
1246 if (getLexer().getKind() == AsmToken::LParen) {
1248 Parser.Lex(); // Eat the '(' token.
1249 if (getLexer().getKind() == AsmToken::Percent) {
1250 Parser.Lex(); // Eat the % token.
1251 const AsmToken &nextTok = Parser.getTok();
1252 if (nextTok.isNot(AsmToken::Identifier))
1255 Str += nextTok.getIdentifier();
1256 Parser.Lex(); // Eat the identifier.
1257 if (getLexer().getKind() != AsmToken::LParen)
1262 if (getParser().parseParenExpression(IdVal, EndLoc))
1265 while (getLexer().getKind() == AsmToken::RParen)
1266 Parser.Lex(); // Eat the ')' token.
1269 return true; // Parenthesis must follow the relocation operand.
1271 Res = evaluateRelocExpr(IdVal, Str);
1275 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1277 StartLoc = Parser.getTok().getLoc();
1278 RegNo = tryParseRegister(isMips64());
1279 EndLoc = Parser.getTok().getLoc();
1280 return (RegNo == (unsigned) -1);
1283 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1287 while (getLexer().getKind() == AsmToken::LParen)
1290 switch (getLexer().getKind()) {
1293 case AsmToken::Identifier:
1294 case AsmToken::LParen:
1295 case AsmToken::Integer:
1296 case AsmToken::Minus:
1297 case AsmToken::Plus:
1299 Result = getParser().parseParenExpression(Res, S);
1301 Result = (getParser().parseExpression(Res));
1302 while (getLexer().getKind() == AsmToken::RParen)
1305 case AsmToken::Percent:
1306 Result = parseRelocOperand(Res);
1311 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1312 SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
1314 const MCExpr *IdVal = 0;
1316 bool isParenExpr = false;
1317 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1318 // First operand is the offset.
1319 S = Parser.getTok().getLoc();
1321 if (getLexer().getKind() == AsmToken::LParen) {
1326 if (getLexer().getKind() != AsmToken::Dollar) {
1327 if (parseMemOffset(IdVal, isParenExpr))
1328 return MatchOperand_ParseFail;
1330 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1331 if (Tok.isNot(AsmToken::LParen)) {
1332 MipsOperand *Mnemonic = static_cast<MipsOperand*>(Operands[0]);
1333 if (Mnemonic->getToken() == "la") {
1334 SMLoc E = SMLoc::getFromPointer(
1335 Parser.getTok().getLoc().getPointer() - 1);
1336 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1337 return MatchOperand_Success;
1339 if (Tok.is(AsmToken::EndOfStatement)) {
1340 SMLoc E = SMLoc::getFromPointer(
1341 Parser.getTok().getLoc().getPointer() - 1);
1343 // Zero register assumed, add a memory operand with ZERO as its base.
1344 Operands.push_back(MipsOperand::CreateMem(isMips64() ? Mips::ZERO_64
1347 return MatchOperand_Success;
1349 Error(Parser.getTok().getLoc(), "'(' expected");
1350 return MatchOperand_ParseFail;
1353 Parser.Lex(); // Eat the '(' token.
1356 Res = parseRegs(Operands, isMips64()? (int) MipsOperand::Kind_GPR64:
1357 (int) MipsOperand::Kind_GPR32);
1358 if (Res != MatchOperand_Success)
1361 if (Parser.getTok().isNot(AsmToken::RParen)) {
1362 Error(Parser.getTok().getLoc(), "')' expected");
1363 return MatchOperand_ParseFail;
1366 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1368 Parser.Lex(); // Eat the ')' token.
1371 IdVal = MCConstantExpr::Create(0, getContext());
1373 // Replace the register operand with the memory operand.
1374 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1375 int RegNo = op->getReg();
1376 // Remove the register from the operands.
1377 Operands.pop_back();
1378 // Add the memory operand.
1379 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1381 if (IdVal->EvaluateAsAbsolute(Imm))
1382 IdVal = MCConstantExpr::Create(Imm, getContext());
1383 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1384 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1388 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
1390 return MatchOperand_Success;
1394 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1396 // If the first token is not '$' we have an error.
1397 if (Parser.getTok().isNot(AsmToken::Dollar))
1400 SMLoc S = Parser.getTok().getLoc();
1402 AsmToken::TokenKind TkKind = getLexer().getKind();
1405 if (TkKind == AsmToken::Integer) {
1406 Reg = matchRegisterByNumber(Parser.getTok().getIntVal(),
1407 regKindToRegClass(RegKind));
1410 } else if (TkKind == AsmToken::Identifier) {
1411 if ((Reg = matchCPURegisterName(Parser.getTok().getString().lower())) == -1)
1413 Reg = getReg(regKindToRegClass(RegKind), Reg);
1418 MipsOperand *Op = MipsOperand::CreatePtrReg(Reg, S, Parser.getTok().getLoc());
1419 Op->setRegKind((MipsOperand::RegisterKind)RegKind);
1420 Operands.push_back(Op);
1425 MipsAsmParser::OperandMatchResultTy
1426 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1427 MipsOperand::RegisterKind RegKind = isN64() ? MipsOperand::Kind_GPR64 :
1428 MipsOperand::Kind_GPR32;
1430 // Parse index register.
1431 if (!parsePtrReg(Operands, RegKind))
1432 return MatchOperand_NoMatch;
1435 if (Parser.getTok().isNot(AsmToken::LParen))
1436 return MatchOperand_NoMatch;
1438 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1441 // Parse base register.
1442 if (!parsePtrReg(Operands, RegKind))
1443 return MatchOperand_NoMatch;
1446 if (Parser.getTok().isNot(AsmToken::RParen))
1447 return MatchOperand_NoMatch;
1449 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1452 return MatchOperand_Success;
1455 MipsAsmParser::OperandMatchResultTy
1456 MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1458 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1459 if (getLexer().getKind() == AsmToken::Identifier
1460 && !hasConsumedDollar) {
1461 if (searchSymbolAlias(Operands, Kind))
1462 return MatchOperand_Success;
1463 return MatchOperand_NoMatch;
1465 SMLoc S = Parser.getTok().getLoc();
1466 // If the first token is not '$', we have an error.
1467 if (Parser.getTok().isNot(AsmToken::Dollar) && !hasConsumedDollar)
1468 return MatchOperand_NoMatch;
1469 if (!hasConsumedDollar) {
1470 Parser.Lex(); // Eat the '$'
1471 hasConsumedDollar = true;
1473 if (getLexer().getKind() == AsmToken::Identifier) {
1475 std::string RegName = Parser.getTok().getString().lower();
1476 // Match register by name
1478 case MipsOperand::Kind_GPR32:
1479 case MipsOperand::Kind_GPR64:
1480 RegNum = matchCPURegisterName(RegName);
1482 case MipsOperand::Kind_AFGR64Regs:
1483 case MipsOperand::Kind_FGR64Regs:
1484 case MipsOperand::Kind_FGR32Regs:
1485 case MipsOperand::Kind_FGRH32Regs:
1486 RegNum = matchFPURegisterName(RegName);
1487 if (RegKind == MipsOperand::Kind_AFGR64Regs)
1489 else if (RegKind == MipsOperand::Kind_FGRH32Regs
1491 if (RegNum != -1 && RegNum %2 != 0)
1492 Warning(S, "Float register should be even.");
1494 case MipsOperand::Kind_FCCRegs:
1495 RegNum = matchFCCRegisterName(RegName);
1497 case MipsOperand::Kind_ACC64DSP:
1498 RegNum = matchACRegisterName(RegName);
1500 default: break; // No match, value is set to -1.
1502 // No match found, return _NoMatch to give a chance to other round.
1504 return MatchOperand_NoMatch;
1506 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1508 return MatchOperand_NoMatch;
1510 MipsOperand *Op = MipsOperand::CreateReg(RegVal, S,
1511 Parser.getTok().getLoc());
1512 Op->setRegKind(Kind);
1513 Operands.push_back(Op);
1514 hasConsumedDollar = false;
1515 Parser.Lex(); // Eat the register name.
1516 return MatchOperand_Success;
1517 } else if (getLexer().getKind() == AsmToken::Integer) {
1518 unsigned RegNum = Parser.getTok().getIntVal();
1519 if (Kind == MipsOperand::Kind_HWRegs) {
1521 return MatchOperand_NoMatch;
1522 // Only hwreg 29 is supported, found at index 0.
1525 int Reg = matchRegisterByNumber(RegNum, regKindToRegClass(Kind));
1527 return MatchOperand_NoMatch;
1528 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1529 Op->setRegKind(Kind);
1530 Operands.push_back(Op);
1531 hasConsumedDollar = false;
1532 Parser.Lex(); // Eat the register number.
1533 if ((RegKind == MipsOperand::Kind_GPR32)
1534 && (getLexer().is(AsmToken::LParen))) {
1535 // Check if it is indexed addressing operand.
1536 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1537 Parser.Lex(); // Eat the parenthesis.
1538 if (parseRegs(Operands,RegKind) != MatchOperand_Success)
1539 return MatchOperand_NoMatch;
1540 if (getLexer().isNot(AsmToken::RParen))
1541 return MatchOperand_NoMatch;
1542 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1545 return MatchOperand_Success;
1547 return MatchOperand_NoMatch;
1550 MipsAsmParser::OperandMatchResultTy
1551 MipsAsmParser::parseMSARegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1553 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1554 SMLoc S = Parser.getTok().getLoc();
1555 std::string RegName;
1557 if (Parser.getTok().isNot(AsmToken::Dollar))
1558 return MatchOperand_NoMatch;
1562 return MatchOperand_ParseFail;
1563 case MipsOperand::Kind_MSA128BRegs:
1564 case MipsOperand::Kind_MSA128HRegs:
1565 case MipsOperand::Kind_MSA128WRegs:
1566 case MipsOperand::Kind_MSA128DRegs:
1570 Parser.Lex(); // Eat the '$'.
1571 if (getLexer().getKind() == AsmToken::Identifier)
1572 RegName = Parser.getTok().getString().lower();
1574 return MatchOperand_ParseFail;
1576 int RegNum = matchMSA128RegisterName(RegName);
1578 if (RegNum < 0 || RegNum > 31)
1579 return MatchOperand_ParseFail;
1581 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1583 return MatchOperand_ParseFail;
1585 MipsOperand *Op = MipsOperand::CreateReg(RegVal, S,
1586 Parser.getTok().getLoc());
1587 Op->setRegKind(Kind);
1588 Operands.push_back(Op);
1590 Parser.Lex(); // Eat the register identifier.
1592 return MatchOperand_Success;
1595 MipsAsmParser::OperandMatchResultTy
1596 MipsAsmParser::parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1599 return MatchOperand_NoMatch;
1600 return parseRegs(Operands, (int) MipsOperand::Kind_GPR64);
1603 MipsAsmParser::OperandMatchResultTy
1604 MipsAsmParser::parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1605 return parseRegs(Operands, (int) MipsOperand::Kind_GPR32);
1608 MipsAsmParser::OperandMatchResultTy
1609 MipsAsmParser::parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1612 return MatchOperand_NoMatch;
1613 return parseRegs(Operands, (int) MipsOperand::Kind_AFGR64Regs);
1616 MipsAsmParser::OperandMatchResultTy
1617 MipsAsmParser::parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1619 return MatchOperand_NoMatch;
1620 return parseRegs(Operands, (int) MipsOperand::Kind_FGR64Regs);
1623 MipsAsmParser::OperandMatchResultTy
1624 MipsAsmParser::parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1625 return parseRegs(Operands, (int) MipsOperand::Kind_FGR32Regs);
1628 MipsAsmParser::OperandMatchResultTy
1629 MipsAsmParser::parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1630 return parseRegs(Operands, (int) MipsOperand::Kind_FGRH32Regs);
1633 MipsAsmParser::OperandMatchResultTy
1634 MipsAsmParser::parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1635 return parseRegs(Operands, (int) MipsOperand::Kind_FCCRegs);
1638 MipsAsmParser::OperandMatchResultTy
1639 MipsAsmParser::parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1640 return parseRegs(Operands, (int) MipsOperand::Kind_ACC64DSP);
1643 MipsAsmParser::OperandMatchResultTy
1644 MipsAsmParser::parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1645 // If the first token is not '$' we have an error.
1646 if (Parser.getTok().isNot(AsmToken::Dollar))
1647 return MatchOperand_NoMatch;
1649 SMLoc S = Parser.getTok().getLoc();
1650 Parser.Lex(); // Eat the '$'
1652 const AsmToken &Tok = Parser.getTok(); // Get next token.
1654 if (Tok.isNot(AsmToken::Identifier))
1655 return MatchOperand_NoMatch;
1657 if (!Tok.getIdentifier().startswith("ac"))
1658 return MatchOperand_NoMatch;
1660 StringRef NumString = Tok.getIdentifier().substr(2);
1663 if (NumString.getAsInteger(10, IntVal))
1664 return MatchOperand_NoMatch;
1666 unsigned Reg = matchRegisterByNumber(IntVal, Mips::LO32DSPRegClassID);
1668 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1669 Op->setRegKind(MipsOperand::Kind_LO32DSP);
1670 Operands.push_back(Op);
1672 Parser.Lex(); // Eat the register number.
1673 return MatchOperand_Success;
1676 MipsAsmParser::OperandMatchResultTy
1677 MipsAsmParser::parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1678 // If the first token is not '$' we have an error.
1679 if (Parser.getTok().isNot(AsmToken::Dollar))
1680 return MatchOperand_NoMatch;
1682 SMLoc S = Parser.getTok().getLoc();
1683 Parser.Lex(); // Eat the '$'
1685 const AsmToken &Tok = Parser.getTok(); // Get next token.
1687 if (Tok.isNot(AsmToken::Identifier))
1688 return MatchOperand_NoMatch;
1690 if (!Tok.getIdentifier().startswith("ac"))
1691 return MatchOperand_NoMatch;
1693 StringRef NumString = Tok.getIdentifier().substr(2);
1696 if (NumString.getAsInteger(10, IntVal))
1697 return MatchOperand_NoMatch;
1699 unsigned Reg = matchRegisterByNumber(IntVal, Mips::HI32DSPRegClassID);
1701 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1702 Op->setRegKind(MipsOperand::Kind_HI32DSP);
1703 Operands.push_back(Op);
1705 Parser.Lex(); // Eat the register number.
1706 return MatchOperand_Success;
1709 MipsAsmParser::OperandMatchResultTy
1710 MipsAsmParser::parseCOP2(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1711 // If the first token is not '$' we have an error.
1712 if (Parser.getTok().isNot(AsmToken::Dollar))
1713 return MatchOperand_NoMatch;
1715 SMLoc S = Parser.getTok().getLoc();
1716 Parser.Lex(); // Eat the '$'
1718 const AsmToken &Tok = Parser.getTok(); // Get next token.
1720 if (Tok.isNot(AsmToken::Integer))
1721 return MatchOperand_NoMatch;
1723 unsigned IntVal = Tok.getIntVal();
1725 unsigned Reg = matchRegisterByNumber(IntVal, Mips::COP2RegClassID);
1727 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1728 Op->setRegKind(MipsOperand::Kind_COP2);
1729 Operands.push_back(Op);
1731 Parser.Lex(); // Eat the register number.
1732 return MatchOperand_Success;
1735 MipsAsmParser::OperandMatchResultTy
1736 MipsAsmParser::parseMSA128BRegs(
1737 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1738 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128BRegs);
1741 MipsAsmParser::OperandMatchResultTy
1742 MipsAsmParser::parseMSA128HRegs(
1743 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1744 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128HRegs);
1747 MipsAsmParser::OperandMatchResultTy
1748 MipsAsmParser::parseMSA128WRegs(
1749 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1750 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128WRegs);
1753 MipsAsmParser::OperandMatchResultTy
1754 MipsAsmParser::parseMSA128DRegs(
1755 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1756 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128DRegs);
1759 bool MipsAsmParser::searchSymbolAlias(
1760 SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegKind) {
1762 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1764 SMLoc S = Parser.getTok().getLoc();
1766 if (Sym->isVariable())
1767 Expr = Sym->getVariableValue();
1770 if (Expr->getKind() == MCExpr::SymbolRef) {
1771 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind) RegKind;
1772 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
1773 const StringRef DefSymbol = Ref->getSymbol().getName();
1774 if (DefSymbol.startswith("$")) {
1776 APInt IntVal(32, -1);
1777 if (!DefSymbol.substr(1).getAsInteger(10, IntVal))
1778 RegNum = matchRegisterByNumber(IntVal.getZExtValue(),
1780 ? Mips::GPR64RegClassID
1781 : Mips::GPR32RegClassID);
1783 // Lookup for the register with the corresponding name.
1785 case MipsOperand::Kind_AFGR64Regs:
1786 case MipsOperand::Kind_FGR64Regs:
1787 RegNum = matchFPURegisterName(DefSymbol.substr(1));
1789 case MipsOperand::Kind_FGR32Regs:
1790 RegNum = matchFPURegisterName(DefSymbol.substr(1));
1792 case MipsOperand::Kind_GPR64:
1793 case MipsOperand::Kind_GPR32:
1795 RegNum = matchCPURegisterName(DefSymbol.substr(1));
1799 RegNum = getReg(regKindToRegClass(Kind), RegNum);
1803 MipsOperand *op = MipsOperand::CreateReg(RegNum, S,
1804 Parser.getTok().getLoc());
1805 op->setRegKind(Kind);
1806 Operands.push_back(op);
1810 } else if (Expr->getKind() == MCExpr::Constant) {
1812 const MCConstantExpr *Const = static_cast<const MCConstantExpr*>(Expr);
1813 MipsOperand *op = MipsOperand::CreateImm(Const, S,
1814 Parser.getTok().getLoc());
1815 Operands.push_back(op);
1822 MipsAsmParser::OperandMatchResultTy
1823 MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1824 return parseRegs(Operands, (int) MipsOperand::Kind_HWRegs);
1827 MipsAsmParser::OperandMatchResultTy
1828 MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1829 return parseRegs(Operands, (int) MipsOperand::Kind_CCRRegs);
1832 MipsAsmParser::OperandMatchResultTy
1833 MipsAsmParser::parseInvNum(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1834 const MCExpr *IdVal;
1835 // If the first token is '$' we may have register operand.
1836 if (Parser.getTok().is(AsmToken::Dollar))
1837 return MatchOperand_NoMatch;
1838 SMLoc S = Parser.getTok().getLoc();
1839 if (getParser().parseExpression(IdVal))
1840 return MatchOperand_ParseFail;
1841 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
1842 assert( MCE && "Unexpected MCExpr type.");
1843 int64_t Val = MCE->getValue();
1844 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1845 Operands.push_back(MipsOperand::CreateImm(
1846 MCConstantExpr::Create(0 - Val, getContext()), S, E));
1847 return MatchOperand_Success;
1850 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
1852 MCSymbolRefExpr::VariantKind VK
1853 = StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
1854 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
1855 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
1856 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
1857 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
1858 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
1859 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
1860 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
1861 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
1862 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
1863 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
1864 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
1865 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
1866 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
1867 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
1868 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
1869 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
1870 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
1871 .Default(MCSymbolRefExpr::VK_None);
1876 bool MipsAsmParser::
1877 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1878 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1879 // Check if we have valid mnemonic
1880 if (!mnemonicIsValid(Name, 0)) {
1881 Parser.eatToEndOfStatement();
1882 return Error(NameLoc, "Unknown instruction");
1884 // First operand in MCInst is instruction mnemonic.
1885 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
1887 // Read the remaining operands.
1888 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1889 // Read the first operand.
1890 if (ParseOperand(Operands, Name)) {
1891 SMLoc Loc = getLexer().getLoc();
1892 Parser.eatToEndOfStatement();
1893 return Error(Loc, "unexpected token in argument list");
1896 while (getLexer().is(AsmToken::Comma)) {
1897 Parser.Lex(); // Eat the comma.
1898 // Parse and remember the operand.
1899 if (ParseOperand(Operands, Name)) {
1900 SMLoc Loc = getLexer().getLoc();
1901 Parser.eatToEndOfStatement();
1902 return Error(Loc, "unexpected token in argument list");
1906 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1907 SMLoc Loc = getLexer().getLoc();
1908 Parser.eatToEndOfStatement();
1909 return Error(Loc, "unexpected token in argument list");
1911 Parser.Lex(); // Consume the EndOfStatement.
1915 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
1916 SMLoc Loc = getLexer().getLoc();
1917 Parser.eatToEndOfStatement();
1918 return Error(Loc, ErrorMsg);
1921 bool MipsAsmParser::parseSetNoAtDirective() {
1922 // Line should look like: ".set noat".
1924 Options.setATReg(0);
1927 // If this is not the end of the statement, report an error.
1928 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1929 reportParseError("unexpected token in statement");
1932 Parser.Lex(); // Consume the EndOfStatement.
1936 bool MipsAsmParser::parseSetAtDirective() {
1937 // Line can be .set at - defaults to $1
1941 if (getLexer().is(AsmToken::EndOfStatement)) {
1942 Options.setATReg(1);
1943 Parser.Lex(); // Consume the EndOfStatement.
1945 } else if (getLexer().is(AsmToken::Equal)) {
1946 getParser().Lex(); // Eat the '='.
1947 if (getLexer().isNot(AsmToken::Dollar)) {
1948 reportParseError("unexpected token in statement");
1951 Parser.Lex(); // Eat the '$'.
1952 const AsmToken &Reg = Parser.getTok();
1953 if (Reg.is(AsmToken::Identifier)) {
1954 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
1955 } else if (Reg.is(AsmToken::Integer)) {
1956 AtRegNo = Reg.getIntVal();
1958 reportParseError("unexpected token in statement");
1962 if (AtRegNo < 1 || AtRegNo > 31) {
1963 reportParseError("unexpected token in statement");
1967 if (!Options.setATReg(AtRegNo)) {
1968 reportParseError("unexpected token in statement");
1971 getParser().Lex(); // Eat the register.
1973 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1974 reportParseError("unexpected token in statement");
1977 Parser.Lex(); // Consume the EndOfStatement.
1980 reportParseError("unexpected token in statement");
1985 bool MipsAsmParser::parseSetReorderDirective() {
1987 // If this is not the end of the statement, report an error.
1988 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1989 reportParseError("unexpected token in statement");
1992 Options.setReorder();
1993 Parser.Lex(); // Consume the EndOfStatement.
1997 bool MipsAsmParser::parseSetNoReorderDirective() {
1999 // If this is not the end of the statement, report an error.
2000 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2001 reportParseError("unexpected token in statement");
2004 Options.setNoreorder();
2005 Parser.Lex(); // Consume the EndOfStatement.
2009 bool MipsAsmParser::parseSetMacroDirective() {
2011 // If this is not the end of the statement, report an error.
2012 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2013 reportParseError("unexpected token in statement");
2017 Parser.Lex(); // Consume the EndOfStatement.
2021 bool MipsAsmParser::parseSetNoMacroDirective() {
2023 // If this is not the end of the statement, report an error.
2024 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2025 reportParseError("`noreorder' must be set before `nomacro'");
2028 if (Options.isReorder()) {
2029 reportParseError("`noreorder' must be set before `nomacro'");
2032 Options.setNomacro();
2033 Parser.Lex(); // Consume the EndOfStatement.
2037 bool MipsAsmParser::parseSetAssignment() {
2039 const MCExpr *Value;
2041 if (Parser.parseIdentifier(Name))
2042 reportParseError("expected identifier after .set");
2044 if (getLexer().isNot(AsmToken::Comma))
2045 return reportParseError("unexpected token in .set directive");
2048 if (getLexer().is(AsmToken::Dollar)) {
2050 SMLoc DollarLoc = getLexer().getLoc();
2051 // Consume the dollar sign, and check for a following identifier.
2053 // We have a '$' followed by something, make sure they are adjacent.
2054 if (DollarLoc.getPointer() + 1 != getTok().getLoc().getPointer())
2056 StringRef Res = StringRef(DollarLoc.getPointer(),
2057 getTok().getEndLoc().getPointer() - DollarLoc.getPointer());
2058 Symbol = getContext().GetOrCreateSymbol(Res);
2060 Value = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
2062 } else if (Parser.parseExpression(Value))
2063 return reportParseError("expected valid expression after comma");
2065 // Check if the Name already exists as a symbol.
2066 MCSymbol *Sym = getContext().LookupSymbol(Name);
2068 return reportParseError("symbol already defined");
2069 Sym = getContext().GetOrCreateSymbol(Name);
2070 Sym->setVariableValue(Value);
2075 bool MipsAsmParser::parseDirectiveSet() {
2077 // Get the next token.
2078 const AsmToken &Tok = Parser.getTok();
2080 if (Tok.getString() == "noat") {
2081 return parseSetNoAtDirective();
2082 } else if (Tok.getString() == "at") {
2083 return parseSetAtDirective();
2084 } else if (Tok.getString() == "reorder") {
2085 return parseSetReorderDirective();
2086 } else if (Tok.getString() == "noreorder") {
2087 return parseSetNoReorderDirective();
2088 } else if (Tok.getString() == "macro") {
2089 return parseSetMacroDirective();
2090 } else if (Tok.getString() == "nomacro") {
2091 return parseSetNoMacroDirective();
2092 } else if (Tok.getString() == "nomips16") {
2093 // Ignore this directive for now.
2094 Parser.eatToEndOfStatement();
2096 } else if (Tok.getString() == "nomicromips") {
2097 // Ignore this directive for now.
2098 Parser.eatToEndOfStatement();
2101 // It is just an identifier, look for an assignment.
2102 parseSetAssignment();
2109 bool MipsAsmParser::parseDirectiveMipsHackStocg() {
2110 MCAsmParser &Parser = getParser();
2112 if (Parser.parseIdentifier(Name))
2113 reportParseError("expected identifier");
2115 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
2116 if (getLexer().isNot(AsmToken::Comma))
2117 return TokError("unexpected token");
2121 if (Parser.parseAbsoluteExpression(Flags))
2122 return TokError("unexpected token");
2124 getTargetStreamer().emitMipsHackSTOCG(Sym, Flags);
2128 bool MipsAsmParser::parseDirectiveMipsHackELFFlags() {
2130 if (Parser.parseAbsoluteExpression(Flags))
2131 return TokError("unexpected token");
2133 getTargetStreamer().emitMipsHackELFFlags(Flags);
2137 /// parseDirectiveWord
2138 /// ::= .word [ expression (, expression)* ]
2139 bool MipsAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
2140 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2142 const MCExpr *Value;
2143 if (getParser().parseExpression(Value))
2146 getParser().getStreamer().EmitValue(Value, Size);
2148 if (getLexer().is(AsmToken::EndOfStatement))
2151 // FIXME: Improve diagnostic.
2152 if (getLexer().isNot(AsmToken::Comma))
2153 return Error(L, "unexpected token in directive");
2162 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
2164 StringRef IDVal = DirectiveID.getString();
2166 if (IDVal == ".ent") {
2167 // Ignore this directive for now.
2172 if (IDVal == ".end") {
2173 // Ignore this directive for now.
2178 if (IDVal == ".frame") {
2179 // Ignore this directive for now.
2180 Parser.eatToEndOfStatement();
2184 if (IDVal == ".set") {
2185 return parseDirectiveSet();
2188 if (IDVal == ".fmask") {
2189 // Ignore this directive for now.
2190 Parser.eatToEndOfStatement();
2194 if (IDVal == ".mask") {
2195 // Ignore this directive for now.
2196 Parser.eatToEndOfStatement();
2200 if (IDVal == ".gpword") {
2201 // Ignore this directive for now.
2202 Parser.eatToEndOfStatement();
2206 if (IDVal == ".word") {
2207 parseDirectiveWord(4, DirectiveID.getLoc());
2211 if (IDVal == ".mips_hack_stocg")
2212 return parseDirectiveMipsHackStocg();
2214 if (IDVal == ".mips_hack_elf_flags")
2215 return parseDirectiveMipsHackELFFlags();
2220 extern "C" void LLVMInitializeMipsAsmParser() {
2221 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
2222 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
2223 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
2224 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
2227 #define GET_REGISTER_MATCHER
2228 #define GET_MATCHER_IMPLEMENTATION
2229 #include "MipsGenAsmMatcher.inc"