1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCTargetDesc.h"
11 #include "MipsRegisterInfo.h"
12 #include "MipsTargetStreamer.h"
13 #include "llvm/ADT/StringSwitch.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCParser/MCAsmLexer.h"
18 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
19 #include "llvm/MC/MCStreamer.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/MC/MCTargetAsmParser.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/ADT/APInt.h"
33 class MipsAssemblerOptions {
35 MipsAssemblerOptions():
36 aTReg(1), reorder(true), macro(true) {
39 unsigned getATRegNum() {return aTReg;}
40 bool setATReg(unsigned Reg);
42 bool isReorder() {return reorder;}
43 void setReorder() {reorder = true;}
44 void setNoreorder() {reorder = false;}
46 bool isMacro() {return macro;}
47 void setMacro() {macro = true;}
48 void setNomacro() {macro = false;}
58 class MipsAsmParser : public MCTargetAsmParser {
60 MipsTargetStreamer &getTargetStreamer() {
61 MCTargetStreamer &TS = Parser.getStreamer().getTargetStreamer();
62 return static_cast<MipsTargetStreamer &>(TS);
67 MipsAssemblerOptions Options;
68 bool hasConsumedDollar;
70 #define GET_ASSEMBLER_HEADER
71 #include "MipsGenAsmMatcher.inc"
73 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
74 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
75 MCStreamer &Out, unsigned &ErrorInfo,
76 bool MatchingInlineAsm);
78 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
80 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
82 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
84 bool ParseDirective(AsmToken DirectiveID);
86 MipsAsmParser::OperandMatchResultTy
87 parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
90 MipsAsmParser::OperandMatchResultTy
91 parseMSARegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
94 MipsAsmParser::OperandMatchResultTy
95 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
97 bool parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands, int RegKind);
99 MipsAsmParser::OperandMatchResultTy
100 parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
102 MipsAsmParser::OperandMatchResultTy
103 parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
105 MipsAsmParser::OperandMatchResultTy
106 parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
108 MipsAsmParser::OperandMatchResultTy
109 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
111 MipsAsmParser::OperandMatchResultTy
112 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
114 MipsAsmParser::OperandMatchResultTy
115 parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
117 MipsAsmParser::OperandMatchResultTy
118 parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
120 MipsAsmParser::OperandMatchResultTy
121 parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
123 MipsAsmParser::OperandMatchResultTy
124 parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
126 MipsAsmParser::OperandMatchResultTy
127 parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
129 MipsAsmParser::OperandMatchResultTy
130 parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
132 MipsAsmParser::OperandMatchResultTy
133 parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
135 MipsAsmParser::OperandMatchResultTy
136 parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
138 MipsAsmParser::OperandMatchResultTy
139 parseCOP2(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
141 MipsAsmParser::OperandMatchResultTy
142 parseMSA128BRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
144 MipsAsmParser::OperandMatchResultTy
145 parseMSA128HRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
147 MipsAsmParser::OperandMatchResultTy
148 parseMSA128WRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
150 MipsAsmParser::OperandMatchResultTy
151 parseMSA128DRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
153 MipsAsmParser::OperandMatchResultTy
154 parseInvNum(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
156 bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
159 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &,
162 int tryParseRegister(bool is64BitReg);
164 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
167 bool needsExpansion(MCInst &Inst);
169 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
170 SmallVectorImpl<MCInst> &Instructions);
171 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
172 SmallVectorImpl<MCInst> &Instructions);
173 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
174 SmallVectorImpl<MCInst> &Instructions);
175 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
176 SmallVectorImpl<MCInst> &Instructions);
177 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
178 SmallVectorImpl<MCInst> &Instructions,
179 bool isLoad,bool isImmOpnd);
180 bool reportParseError(StringRef ErrorMsg);
182 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
183 bool parseRelocOperand(const MCExpr *&Res);
185 const MCExpr* evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
187 bool isEvaluated(const MCExpr *Expr);
188 bool parseDirectiveSet();
189 bool parseDirectiveMipsHackStocg();
190 bool parseDirectiveMipsHackELFFlags();
192 bool parseSetAtDirective();
193 bool parseSetNoAtDirective();
194 bool parseSetMacroDirective();
195 bool parseSetNoMacroDirective();
196 bool parseSetReorderDirective();
197 bool parseSetNoReorderDirective();
199 bool parseSetAssignment();
201 bool parseDirectiveWord(unsigned Size, SMLoc L);
203 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
205 bool isMips64() const {
206 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
209 bool isFP64() const {
210 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
214 return STI.getFeatureBits() & Mips::FeatureN64;
217 int matchRegisterName(StringRef Symbol, bool is64BitReg);
219 int matchCPURegisterName(StringRef Symbol);
221 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
223 int matchFPURegisterName(StringRef Name);
225 int matchFCCRegisterName(StringRef Name);
227 int matchACRegisterName(StringRef Name);
229 int matchMSA128RegisterName(StringRef Name);
231 int regKindToRegClass(int RegKind);
233 unsigned getReg(int RC, int RegNo);
237 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
238 SmallVectorImpl<MCInst> &Instructions);
240 // Helper function that checks if the value of a vector index is within the
241 // boundaries of accepted values for each RegisterKind
242 // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
243 bool validateMSAIndex(int Val, int RegKind);
246 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
247 const MCInstrInfo &MII)
248 : MCTargetAsmParser(), STI(sti), Parser(parser),
249 hasConsumedDollar(false) {
250 // Initialize the set of available features.
251 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
254 MCAsmParser &getParser() const { return Parser; }
255 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
262 /// MipsOperand - Instances of this class represent a parsed Mips machine
264 class MipsOperand : public MCParsedAsmOperand {
300 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
328 SMLoc StartLoc, EndLoc;
331 void addRegOperands(MCInst &Inst, unsigned N) const {
332 assert(N == 1 && "Invalid number of operands!");
333 Inst.addOperand(MCOperand::CreateReg(getReg()));
336 void addPtrRegOperands(MCInst &Inst, unsigned N) const {
337 assert(N == 1 && "Invalid number of operands!");
338 Inst.addOperand(MCOperand::CreateReg(getPtrReg()));
341 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
342 // Add as immediate when possible. Null MCExpr = 0.
344 Inst.addOperand(MCOperand::CreateImm(0));
345 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
346 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
348 Inst.addOperand(MCOperand::CreateExpr(Expr));
351 void addImmOperands(MCInst &Inst, unsigned N) const {
352 assert(N == 1 && "Invalid number of operands!");
353 const MCExpr *Expr = getImm();
357 void addMemOperands(MCInst &Inst, unsigned N) const {
358 assert(N == 2 && "Invalid number of operands!");
360 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
362 const MCExpr *Expr = getMemOff();
366 bool isReg() const { return Kind == k_Register; }
367 bool isImm() const { return Kind == k_Immediate; }
368 bool isToken() const { return Kind == k_Token; }
369 bool isMem() const { return Kind == k_Memory; }
370 bool isPtrReg() const { return Kind == k_PtrReg; }
371 bool isInvNum() const { return Kind == k_Immediate; }
373 StringRef getToken() const {
374 assert(Kind == k_Token && "Invalid access!");
375 return StringRef(Tok.Data, Tok.Length);
378 unsigned getReg() const {
379 assert((Kind == k_Register) && "Invalid access!");
383 unsigned getPtrReg() const {
384 assert((Kind == k_PtrReg) && "Invalid access!");
388 void setRegKind(RegisterKind RegKind) {
389 assert((Kind == k_Register || Kind == k_PtrReg) && "Invalid access!");
393 const MCExpr *getImm() const {
394 assert((Kind == k_Immediate) && "Invalid access!");
398 unsigned getMemBase() const {
399 assert((Kind == k_Memory) && "Invalid access!");
403 const MCExpr *getMemOff() const {
404 assert((Kind == k_Memory) && "Invalid access!");
408 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
409 MipsOperand *Op = new MipsOperand(k_Token);
410 Op->Tok.Data = Str.data();
411 Op->Tok.Length = Str.size();
417 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
418 MipsOperand *Op = new MipsOperand(k_Register);
419 Op->Reg.RegNum = RegNum;
425 static MipsOperand *CreatePtrReg(unsigned RegNum, SMLoc S, SMLoc E) {
426 MipsOperand *Op = new MipsOperand(k_PtrReg);
427 Op->Reg.RegNum = RegNum;
433 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
434 MipsOperand *Op = new MipsOperand(k_Immediate);
441 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off,
443 MipsOperand *Op = new MipsOperand(k_Memory);
451 bool isGPR32Asm() const {
452 return Kind == k_Register && Reg.Kind == Kind_GPR32;
454 void addRegAsmOperands(MCInst &Inst, unsigned N) const {
455 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
458 bool isGPR64Asm() const {
459 return Kind == k_Register && Reg.Kind == Kind_GPR64;
462 bool isHWRegsAsm() const {
463 assert((Kind == k_Register) && "Invalid access!");
464 return Reg.Kind == Kind_HWRegs;
467 bool isCCRAsm() const {
468 assert((Kind == k_Register) && "Invalid access!");
469 return Reg.Kind == Kind_CCRRegs;
472 bool isAFGR64Asm() const {
473 return Kind == k_Register && Reg.Kind == Kind_AFGR64Regs;
476 bool isFGR64Asm() const {
477 return Kind == k_Register && Reg.Kind == Kind_FGR64Regs;
480 bool isFGR32Asm() const {
481 return (Kind == k_Register) && Reg.Kind == Kind_FGR32Regs;
484 bool isFGRH32Asm() const {
485 return (Kind == k_Register) && Reg.Kind == Kind_FGRH32Regs;
488 bool isFCCRegsAsm() const {
489 return (Kind == k_Register) && Reg.Kind == Kind_FCCRegs;
492 bool isACC64DSPAsm() const {
493 return Kind == k_Register && Reg.Kind == Kind_ACC64DSP;
496 bool isLO32DSPAsm() const {
497 return Kind == k_Register && Reg.Kind == Kind_LO32DSP;
500 bool isHI32DSPAsm() const {
501 return Kind == k_Register && Reg.Kind == Kind_HI32DSP;
504 bool isCOP2Asm() const {
505 return Kind == k_Register && Reg.Kind == Kind_COP2;
508 bool isMSA128BAsm() const {
509 return Kind == k_Register && Reg.Kind == Kind_MSA128BRegs;
512 bool isMSA128HAsm() const {
513 return Kind == k_Register && Reg.Kind == Kind_MSA128HRegs;
516 bool isMSA128WAsm() const {
517 return Kind == k_Register && Reg.Kind == Kind_MSA128WRegs;
520 bool isMSA128DAsm() const {
521 return Kind == k_Register && Reg.Kind == Kind_MSA128DRegs;
524 /// getStartLoc - Get the location of the first token of this operand.
525 SMLoc getStartLoc() const {
528 /// getEndLoc - Get the location of the last token of this operand.
529 SMLoc getEndLoc() const {
533 virtual void print(raw_ostream &OS) const {
534 llvm_unreachable("unimplemented!");
536 }; // class MipsOperand
540 extern const MCInstrDesc MipsInsts[];
542 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
543 return MipsInsts[Opcode];
546 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
547 SmallVectorImpl<MCInst> &Instructions) {
548 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
550 if (MCID.hasDelaySlot() && Options.isReorder()) {
551 // If this instruction has a delay slot and .set reorder is active,
552 // emit a NOP after it.
553 Instructions.push_back(Inst);
555 NopInst.setOpcode(Mips::SLL);
556 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
557 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
558 NopInst.addOperand(MCOperand::CreateImm(0));
559 Instructions.push_back(NopInst);
563 if (MCID.mayLoad() || MCID.mayStore()) {
564 // Check the offset of memory operand, if it is a symbol
565 // reference or immediate we may have to expand instructions.
566 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
567 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
568 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY)
569 || (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
570 MCOperand &Op = Inst.getOperand(i);
572 int MemOffset = Op.getImm();
573 if (MemOffset < -32768 || MemOffset > 32767) {
574 // Offset can't exceed 16bit value.
575 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
578 } else if (Op.isExpr()) {
579 const MCExpr *Expr = Op.getExpr();
580 if (Expr->getKind() == MCExpr::SymbolRef) {
581 const MCSymbolRefExpr *SR =
582 static_cast<const MCSymbolRefExpr*>(Expr);
583 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
585 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
588 } else if (!isEvaluated(Expr)) {
589 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
597 if (needsExpansion(Inst))
598 expandInstruction(Inst, IDLoc, Instructions);
600 Instructions.push_back(Inst);
605 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
607 switch (Inst.getOpcode()) {
608 case Mips::LoadImm32Reg:
609 case Mips::LoadAddr32Imm:
610 case Mips::LoadAddr32Reg:
617 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
618 SmallVectorImpl<MCInst> &Instructions) {
619 switch (Inst.getOpcode()) {
620 case Mips::LoadImm32Reg:
621 return expandLoadImm(Inst, IDLoc, Instructions);
622 case Mips::LoadAddr32Imm:
623 return expandLoadAddressImm(Inst, IDLoc, Instructions);
624 case Mips::LoadAddr32Reg:
625 return expandLoadAddressReg(Inst, IDLoc, Instructions);
629 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
630 SmallVectorImpl<MCInst> &Instructions) {
632 const MCOperand &ImmOp = Inst.getOperand(1);
633 assert(ImmOp.isImm() && "expected immediate operand kind");
634 const MCOperand &RegOp = Inst.getOperand(0);
635 assert(RegOp.isReg() && "expected register operand kind");
637 int ImmValue = ImmOp.getImm();
638 tmpInst.setLoc(IDLoc);
639 if (0 <= ImmValue && ImmValue <= 65535) {
640 // For 0 <= j <= 65535.
641 // li d,j => ori d,$zero,j
642 tmpInst.setOpcode(Mips::ORi);
643 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
644 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
645 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
646 Instructions.push_back(tmpInst);
647 } else if (ImmValue < 0 && ImmValue >= -32768) {
648 // For -32768 <= j < 0.
649 // li d,j => addiu d,$zero,j
650 tmpInst.setOpcode(Mips::ADDiu);
651 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
652 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
653 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
654 Instructions.push_back(tmpInst);
656 // For any other value of j that is representable as a 32-bit integer.
657 // li d,j => lui d,hi16(j)
659 tmpInst.setOpcode(Mips::LUi);
660 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
661 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
662 Instructions.push_back(tmpInst);
664 tmpInst.setOpcode(Mips::ORi);
665 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
666 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
667 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
668 tmpInst.setLoc(IDLoc);
669 Instructions.push_back(tmpInst);
673 void MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
674 SmallVectorImpl<MCInst> &Instructions) {
676 const MCOperand &ImmOp = Inst.getOperand(2);
677 assert(ImmOp.isImm() && "expected immediate operand kind");
678 const MCOperand &SrcRegOp = Inst.getOperand(1);
679 assert(SrcRegOp.isReg() && "expected register operand kind");
680 const MCOperand &DstRegOp = Inst.getOperand(0);
681 assert(DstRegOp.isReg() && "expected register operand kind");
682 int ImmValue = ImmOp.getImm();
683 if (-32768 <= ImmValue && ImmValue <= 65535) {
684 // For -32768 <= j <= 65535.
685 // la d,j(s) => addiu d,s,j
686 tmpInst.setOpcode(Mips::ADDiu);
687 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
688 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
689 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
690 Instructions.push_back(tmpInst);
692 // For any other value of j that is representable as a 32-bit integer.
693 // la d,j(s) => lui d,hi16(j)
696 tmpInst.setOpcode(Mips::LUi);
697 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
698 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
699 Instructions.push_back(tmpInst);
701 tmpInst.setOpcode(Mips::ORi);
702 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
703 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
704 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
705 Instructions.push_back(tmpInst);
707 tmpInst.setOpcode(Mips::ADDu);
708 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
709 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
710 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
711 Instructions.push_back(tmpInst);
715 void MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
716 SmallVectorImpl<MCInst> &Instructions) {
718 const MCOperand &ImmOp = Inst.getOperand(1);
719 assert(ImmOp.isImm() && "expected immediate operand kind");
720 const MCOperand &RegOp = Inst.getOperand(0);
721 assert(RegOp.isReg() && "expected register operand kind");
722 int ImmValue = ImmOp.getImm();
723 if (-32768 <= ImmValue && ImmValue <= 65535) {
724 // For -32768 <= j <= 65535.
725 // la d,j => addiu d,$zero,j
726 tmpInst.setOpcode(Mips::ADDiu);
727 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
728 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
729 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
730 Instructions.push_back(tmpInst);
732 // For any other value of j that is representable as a 32-bit integer.
733 // la d,j => lui d,hi16(j)
735 tmpInst.setOpcode(Mips::LUi);
736 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
737 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
738 Instructions.push_back(tmpInst);
740 tmpInst.setOpcode(Mips::ORi);
741 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
742 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
743 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
744 Instructions.push_back(tmpInst);
748 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
749 SmallVectorImpl<MCInst> &Instructions, bool isLoad, bool isImmOpnd) {
750 const MCSymbolRefExpr *SR;
752 unsigned ImmOffset, HiOffset, LoOffset;
753 const MCExpr *ExprOffset;
755 unsigned AtRegNum = getReg((isMips64()) ? Mips::GPR64RegClassID
756 : Mips::GPR32RegClassID, getATReg());
757 // 1st operand is either the source or destination register.
758 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
759 unsigned RegOpNum = Inst.getOperand(0).getReg();
760 // 2nd operand is the base register.
761 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
762 unsigned BaseRegNum = Inst.getOperand(1).getReg();
763 // 3rd operand is either an immediate or expression.
765 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
766 ImmOffset = Inst.getOperand(2).getImm();
767 LoOffset = ImmOffset & 0x0000ffff;
768 HiOffset = (ImmOffset & 0xffff0000) >> 16;
769 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
770 if (LoOffset & 0x8000)
773 ExprOffset = Inst.getOperand(2).getExpr();
774 // All instructions will have the same location.
775 TempInst.setLoc(IDLoc);
776 // 1st instruction in expansion is LUi. For load instruction we can use
777 // the dst register as a temporary if base and dst are different,
778 // but for stores we must use $at.
779 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
780 TempInst.setOpcode(Mips::LUi);
781 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
783 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
785 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
786 SR = static_cast<const MCSymbolRefExpr*>(ExprOffset);
787 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
788 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
790 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
792 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
793 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
796 // Add the instruction to the list.
797 Instructions.push_back(TempInst);
798 // Prepare TempInst for next instruction.
800 // Add temp register to base.
801 TempInst.setOpcode(Mips::ADDu);
802 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
803 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
804 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
805 Instructions.push_back(TempInst);
807 // And finaly, create original instruction with low part
808 // of offset and new base.
809 TempInst.setOpcode(Inst.getOpcode());
810 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
811 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
813 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
815 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
816 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
817 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
819 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
821 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
822 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
825 Instructions.push_back(TempInst);
830 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
831 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
832 MCStreamer &Out, unsigned &ErrorInfo,
833 bool MatchingInlineAsm) {
835 SmallVector<MCInst, 8> Instructions;
836 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
839 switch (MatchResult) {
842 case Match_Success: {
843 if (processInstruction(Inst, IDLoc, Instructions))
845 for (unsigned i = 0; i < Instructions.size(); i++)
846 Out.EmitInstruction(Instructions[i]);
849 case Match_MissingFeature:
850 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
852 case Match_InvalidOperand: {
853 SMLoc ErrorLoc = IDLoc;
854 if (ErrorInfo != ~0U) {
855 if (ErrorInfo >= Operands.size())
856 return Error(IDLoc, "too few operands for instruction");
858 ErrorLoc = ((MipsOperand*) Operands[ErrorInfo])->getStartLoc();
859 if (ErrorLoc == SMLoc())
863 return Error(ErrorLoc, "invalid operand for instruction");
865 case Match_MnemonicFail:
866 return Error(IDLoc, "invalid instruction");
871 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
877 CC = StringSwitch<unsigned>(Name)
911 // Although SGI documentation just cuts out t0-t3 for n32/n64,
912 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
913 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
914 if (isMips64() && 8 <= CC && CC <= 11)
917 if (CC == -1 && isMips64())
918 CC = StringSwitch<unsigned>(Name)
931 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
933 if (Name[0] == 'f') {
934 StringRef NumString = Name.substr(1);
936 if (NumString.getAsInteger(10, IntVal))
937 return -1; // This is not an integer.
938 if (IntVal > 31) // Maximum index for fpu register.
945 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
947 if (Name.startswith("fcc")) {
948 StringRef NumString = Name.substr(3);
950 if (NumString.getAsInteger(10, IntVal))
951 return -1; // This is not an integer.
952 if (IntVal > 7) // There are only 8 fcc registers.
959 int MipsAsmParser::matchACRegisterName(StringRef Name) {
961 if (Name.startswith("ac")) {
962 StringRef NumString = Name.substr(2);
964 if (NumString.getAsInteger(10, IntVal))
965 return -1; // This is not an integer.
966 if (IntVal > 3) // There are only 3 acc registers.
973 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
976 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal))
985 int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
988 CC = matchCPURegisterName(Name);
990 return matchRegisterByNumber(CC, is64BitReg ? Mips::GPR64RegClassID
991 : Mips::GPR32RegClassID);
992 CC = matchFPURegisterName(Name);
993 //TODO: decide about fpu register class
995 return matchRegisterByNumber(CC, isFP64() ? Mips::FGR64RegClassID
996 : Mips::FGR32RegClassID);
997 return matchMSA128RegisterName(Name);
1000 int MipsAsmParser::regKindToRegClass(int RegKind) {
1003 case MipsOperand::Kind_GPR32: return Mips::GPR32RegClassID;
1004 case MipsOperand::Kind_GPR64: return Mips::GPR64RegClassID;
1005 case MipsOperand::Kind_HWRegs: return Mips::HWRegsRegClassID;
1006 case MipsOperand::Kind_FGR32Regs: return Mips::FGR32RegClassID;
1007 case MipsOperand::Kind_FGRH32Regs: return Mips::FGRH32RegClassID;
1008 case MipsOperand::Kind_FGR64Regs: return Mips::FGR64RegClassID;
1009 case MipsOperand::Kind_AFGR64Regs: return Mips::AFGR64RegClassID;
1010 case MipsOperand::Kind_CCRRegs: return Mips::CCRRegClassID;
1011 case MipsOperand::Kind_ACC64DSP: return Mips::ACC64DSPRegClassID;
1012 case MipsOperand::Kind_FCCRegs: return Mips::FCCRegClassID;
1013 case MipsOperand::Kind_MSA128BRegs: return Mips::MSA128BRegClassID;
1014 case MipsOperand::Kind_MSA128HRegs: return Mips::MSA128HRegClassID;
1015 case MipsOperand::Kind_MSA128WRegs: return Mips::MSA128WRegClassID;
1016 case MipsOperand::Kind_MSA128DRegs: return Mips::MSA128DRegClassID;
1022 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
1030 int MipsAsmParser::getATReg() {
1031 return Options.getATRegNum();
1034 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
1035 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1038 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
1040 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs())
1043 return getReg(RegClass, RegNum);
1046 int MipsAsmParser::tryParseRegister(bool is64BitReg) {
1047 const AsmToken &Tok = Parser.getTok();
1050 if (Tok.is(AsmToken::Identifier)) {
1051 std::string lowerCase = Tok.getString().lower();
1052 RegNum = matchRegisterName(lowerCase, is64BitReg);
1053 } else if (Tok.is(AsmToken::Integer))
1054 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
1055 is64BitReg ? Mips::GPR64RegClassID : Mips::GPR32RegClassID);
1059 bool MipsAsmParser::tryParseRegisterOperand(
1060 SmallVectorImpl<MCParsedAsmOperand*> &Operands, bool is64BitReg) {
1062 SMLoc S = Parser.getTok().getLoc();
1065 RegNo = tryParseRegister(is64BitReg);
1069 Operands.push_back(MipsOperand::CreateReg(RegNo, S,
1070 Parser.getTok().getLoc()));
1071 Parser.Lex(); // Eat register token.
1075 bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
1076 StringRef Mnemonic) {
1077 // Check if the current operand has a custom associated parser, if so, try to
1078 // custom parse the operand, or fallback to the general approach.
1079 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1080 if (ResTy == MatchOperand_Success)
1082 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1083 // there was a match, but an error occurred, in which case, just return that
1084 // the operand parsing failed.
1085 if (ResTy == MatchOperand_ParseFail)
1088 switch (getLexer().getKind()) {
1090 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1092 case AsmToken::Dollar: {
1093 // Parse the register.
1094 SMLoc S = Parser.getTok().getLoc();
1095 Parser.Lex(); // Eat dollar token.
1096 // Parse the register operand.
1097 if (!tryParseRegisterOperand(Operands, isMips64())) {
1098 if (getLexer().is(AsmToken::LParen)) {
1099 // Check if it is indexed addressing operand.
1100 Operands.push_back(MipsOperand::CreateToken("(", S));
1101 Parser.Lex(); // Eat the parenthesis.
1102 if (getLexer().isNot(AsmToken::Dollar))
1105 Parser.Lex(); // Eat the dollar
1106 if (tryParseRegisterOperand(Operands, isMips64()))
1109 if (!getLexer().is(AsmToken::RParen))
1112 S = Parser.getTok().getLoc();
1113 Operands.push_back(MipsOperand::CreateToken(")", S));
1118 // Maybe it is a symbol reference.
1119 StringRef Identifier;
1120 if (Parser.parseIdentifier(Identifier))
1123 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1125 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1127 // Otherwise create a symbol reference.
1128 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
1131 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
1134 case AsmToken::Identifier:
1135 // Look for the existing symbol, we should check if
1136 // we need to assigne the propper RegisterKind.
1137 if (searchSymbolAlias(Operands, MipsOperand::Kind_None))
1139 // Else drop to expression parsing.
1140 case AsmToken::LParen:
1141 case AsmToken::Minus:
1142 case AsmToken::Plus:
1143 case AsmToken::Integer:
1144 case AsmToken::String: {
1145 // Quoted label names.
1146 const MCExpr *IdVal;
1147 SMLoc S = Parser.getTok().getLoc();
1148 if (getParser().parseExpression(IdVal))
1150 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1151 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1154 case AsmToken::Percent: {
1155 // It is a symbol reference or constant expression.
1156 const MCExpr *IdVal;
1157 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1158 if (parseRelocOperand(IdVal))
1161 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1163 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1165 } // case AsmToken::Percent
1166 } // switch(getLexer().getKind())
1170 const MCExpr* MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1171 StringRef RelocStr) {
1173 // Check the type of the expression.
1174 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1175 // It's a constant, evaluate lo or hi value.
1176 if (RelocStr == "lo") {
1177 short Val = MCE->getValue();
1178 Res = MCConstantExpr::Create(Val, getContext());
1179 } else if (RelocStr == "hi") {
1180 int Val = MCE->getValue();
1181 int LoSign = Val & 0x8000;
1182 Val = (Val & 0xffff0000) >> 16;
1183 // Lower part is treated as a signed int, so if it is negative
1184 // we must add 1 to the hi part to compensate.
1187 Res = MCConstantExpr::Create(Val, getContext());
1189 llvm_unreachable("Invalid RelocStr value");
1194 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1195 // It's a symbol, create a symbolic expression from the symbol.
1196 StringRef Symbol = MSRE->getSymbol().getName();
1197 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1198 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1202 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1203 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1204 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1205 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1209 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1210 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1211 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1214 // Just return the original expression.
1218 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1220 switch (Expr->getKind()) {
1221 case MCExpr::Constant:
1223 case MCExpr::SymbolRef:
1224 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1225 case MCExpr::Binary:
1226 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1227 if (!isEvaluated(BE->getLHS()))
1229 return isEvaluated(BE->getRHS());
1232 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1239 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1240 Parser.Lex(); // Eat the % token.
1241 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1242 if (Tok.isNot(AsmToken::Identifier))
1245 std::string Str = Tok.getIdentifier().str();
1247 Parser.Lex(); // Eat the identifier.
1248 // Now make an expression from the rest of the operand.
1249 const MCExpr *IdVal;
1252 if (getLexer().getKind() == AsmToken::LParen) {
1254 Parser.Lex(); // Eat the '(' token.
1255 if (getLexer().getKind() == AsmToken::Percent) {
1256 Parser.Lex(); // Eat the % token.
1257 const AsmToken &nextTok = Parser.getTok();
1258 if (nextTok.isNot(AsmToken::Identifier))
1261 Str += nextTok.getIdentifier();
1262 Parser.Lex(); // Eat the identifier.
1263 if (getLexer().getKind() != AsmToken::LParen)
1268 if (getParser().parseParenExpression(IdVal, EndLoc))
1271 while (getLexer().getKind() == AsmToken::RParen)
1272 Parser.Lex(); // Eat the ')' token.
1275 return true; // Parenthesis must follow the relocation operand.
1277 Res = evaluateRelocExpr(IdVal, Str);
1281 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1283 StartLoc = Parser.getTok().getLoc();
1284 RegNo = tryParseRegister(isMips64());
1285 EndLoc = Parser.getTok().getLoc();
1286 return (RegNo == (unsigned) -1);
1289 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1293 while (getLexer().getKind() == AsmToken::LParen)
1296 switch (getLexer().getKind()) {
1299 case AsmToken::Identifier:
1300 case AsmToken::LParen:
1301 case AsmToken::Integer:
1302 case AsmToken::Minus:
1303 case AsmToken::Plus:
1305 Result = getParser().parseParenExpression(Res, S);
1307 Result = (getParser().parseExpression(Res));
1308 while (getLexer().getKind() == AsmToken::RParen)
1311 case AsmToken::Percent:
1312 Result = parseRelocOperand(Res);
1317 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1318 SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
1320 const MCExpr *IdVal = 0;
1322 bool isParenExpr = false;
1323 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1324 // First operand is the offset.
1325 S = Parser.getTok().getLoc();
1327 if (getLexer().getKind() == AsmToken::LParen) {
1332 if (getLexer().getKind() != AsmToken::Dollar) {
1333 if (parseMemOffset(IdVal, isParenExpr))
1334 return MatchOperand_ParseFail;
1336 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1337 if (Tok.isNot(AsmToken::LParen)) {
1338 MipsOperand *Mnemonic = static_cast<MipsOperand*>(Operands[0]);
1339 if (Mnemonic->getToken() == "la") {
1340 SMLoc E = SMLoc::getFromPointer(
1341 Parser.getTok().getLoc().getPointer() - 1);
1342 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1343 return MatchOperand_Success;
1345 if (Tok.is(AsmToken::EndOfStatement)) {
1346 SMLoc E = SMLoc::getFromPointer(
1347 Parser.getTok().getLoc().getPointer() - 1);
1349 // Zero register assumed, add a memory operand with ZERO as its base.
1350 Operands.push_back(MipsOperand::CreateMem(isMips64() ? Mips::ZERO_64
1353 return MatchOperand_Success;
1355 Error(Parser.getTok().getLoc(), "'(' expected");
1356 return MatchOperand_ParseFail;
1359 Parser.Lex(); // Eat the '(' token.
1362 Res = parseRegs(Operands, isMips64()? (int) MipsOperand::Kind_GPR64:
1363 (int) MipsOperand::Kind_GPR32);
1364 if (Res != MatchOperand_Success)
1367 if (Parser.getTok().isNot(AsmToken::RParen)) {
1368 Error(Parser.getTok().getLoc(), "')' expected");
1369 return MatchOperand_ParseFail;
1372 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1374 Parser.Lex(); // Eat the ')' token.
1377 IdVal = MCConstantExpr::Create(0, getContext());
1379 // Replace the register operand with the memory operand.
1380 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1381 int RegNo = op->getReg();
1382 // Remove the register from the operands.
1383 Operands.pop_back();
1384 // Add the memory operand.
1385 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1387 if (IdVal->EvaluateAsAbsolute(Imm))
1388 IdVal = MCConstantExpr::Create(Imm, getContext());
1389 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1390 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1394 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
1396 return MatchOperand_Success;
1400 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1402 // If the first token is not '$' we have an error.
1403 if (Parser.getTok().isNot(AsmToken::Dollar))
1406 SMLoc S = Parser.getTok().getLoc();
1408 AsmToken::TokenKind TkKind = getLexer().getKind();
1411 if (TkKind == AsmToken::Integer) {
1412 Reg = matchRegisterByNumber(Parser.getTok().getIntVal(),
1413 regKindToRegClass(RegKind));
1416 } else if (TkKind == AsmToken::Identifier) {
1417 if ((Reg = matchCPURegisterName(Parser.getTok().getString().lower())) == -1)
1419 Reg = getReg(regKindToRegClass(RegKind), Reg);
1424 MipsOperand *Op = MipsOperand::CreatePtrReg(Reg, S, Parser.getTok().getLoc());
1425 Op->setRegKind((MipsOperand::RegisterKind)RegKind);
1426 Operands.push_back(Op);
1431 MipsAsmParser::OperandMatchResultTy
1432 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1433 MipsOperand::RegisterKind RegKind = isN64() ? MipsOperand::Kind_GPR64 :
1434 MipsOperand::Kind_GPR32;
1436 // Parse index register.
1437 if (!parsePtrReg(Operands, RegKind))
1438 return MatchOperand_NoMatch;
1441 if (Parser.getTok().isNot(AsmToken::LParen))
1442 return MatchOperand_NoMatch;
1444 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1447 // Parse base register.
1448 if (!parsePtrReg(Operands, RegKind))
1449 return MatchOperand_NoMatch;
1452 if (Parser.getTok().isNot(AsmToken::RParen))
1453 return MatchOperand_NoMatch;
1455 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1458 return MatchOperand_Success;
1461 MipsAsmParser::OperandMatchResultTy
1462 MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1464 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1465 if (getLexer().getKind() == AsmToken::Identifier
1466 && !hasConsumedDollar) {
1467 if (searchSymbolAlias(Operands, Kind))
1468 return MatchOperand_Success;
1469 return MatchOperand_NoMatch;
1471 SMLoc S = Parser.getTok().getLoc();
1472 // If the first token is not '$', we have an error.
1473 if (Parser.getTok().isNot(AsmToken::Dollar) && !hasConsumedDollar)
1474 return MatchOperand_NoMatch;
1475 if (!hasConsumedDollar) {
1476 Parser.Lex(); // Eat the '$'
1477 hasConsumedDollar = true;
1479 if (getLexer().getKind() == AsmToken::Identifier) {
1481 std::string RegName = Parser.getTok().getString().lower();
1482 // Match register by name
1484 case MipsOperand::Kind_GPR32:
1485 case MipsOperand::Kind_GPR64:
1486 RegNum = matchCPURegisterName(RegName);
1488 case MipsOperand::Kind_AFGR64Regs:
1489 case MipsOperand::Kind_FGR64Regs:
1490 case MipsOperand::Kind_FGR32Regs:
1491 case MipsOperand::Kind_FGRH32Regs:
1492 RegNum = matchFPURegisterName(RegName);
1493 if (RegKind == MipsOperand::Kind_AFGR64Regs)
1495 else if (RegKind == MipsOperand::Kind_FGRH32Regs
1497 if (RegNum != -1 && RegNum %2 != 0)
1498 Warning(S, "Float register should be even.");
1500 case MipsOperand::Kind_FCCRegs:
1501 RegNum = matchFCCRegisterName(RegName);
1503 case MipsOperand::Kind_ACC64DSP:
1504 RegNum = matchACRegisterName(RegName);
1506 default: break; // No match, value is set to -1.
1508 // No match found, return _NoMatch to give a chance to other round.
1510 return MatchOperand_NoMatch;
1512 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1514 return MatchOperand_NoMatch;
1516 MipsOperand *Op = MipsOperand::CreateReg(RegVal, S,
1517 Parser.getTok().getLoc());
1518 Op->setRegKind(Kind);
1519 Operands.push_back(Op);
1520 hasConsumedDollar = false;
1521 Parser.Lex(); // Eat the register name.
1522 return MatchOperand_Success;
1523 } else if (getLexer().getKind() == AsmToken::Integer) {
1524 unsigned RegNum = Parser.getTok().getIntVal();
1525 if (Kind == MipsOperand::Kind_HWRegs) {
1527 return MatchOperand_NoMatch;
1528 // Only hwreg 29 is supported, found at index 0.
1531 int Reg = matchRegisterByNumber(RegNum, regKindToRegClass(Kind));
1533 return MatchOperand_NoMatch;
1534 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1535 Op->setRegKind(Kind);
1536 Operands.push_back(Op);
1537 hasConsumedDollar = false;
1538 Parser.Lex(); // Eat the register number.
1539 if ((RegKind == MipsOperand::Kind_GPR32)
1540 && (getLexer().is(AsmToken::LParen))) {
1541 // Check if it is indexed addressing operand.
1542 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1543 Parser.Lex(); // Eat the parenthesis.
1544 if (parseRegs(Operands,RegKind) != MatchOperand_Success)
1545 return MatchOperand_NoMatch;
1546 if (getLexer().isNot(AsmToken::RParen))
1547 return MatchOperand_NoMatch;
1548 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1551 return MatchOperand_Success;
1553 return MatchOperand_NoMatch;
1556 bool MipsAsmParser::validateMSAIndex(int Val, int RegKind) {
1557 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1565 case MipsOperand::Kind_MSA128BRegs:
1567 case MipsOperand::Kind_MSA128HRegs:
1569 case MipsOperand::Kind_MSA128WRegs:
1571 case MipsOperand::Kind_MSA128DRegs:
1576 MipsAsmParser::OperandMatchResultTy
1577 MipsAsmParser::parseMSARegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1579 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1580 SMLoc S = Parser.getTok().getLoc();
1581 std::string RegName;
1583 if (Parser.getTok().isNot(AsmToken::Dollar))
1584 return MatchOperand_NoMatch;
1588 return MatchOperand_ParseFail;
1589 case MipsOperand::Kind_MSA128BRegs:
1590 case MipsOperand::Kind_MSA128HRegs:
1591 case MipsOperand::Kind_MSA128WRegs:
1592 case MipsOperand::Kind_MSA128DRegs:
1596 Parser.Lex(); // Eat the '$'.
1597 if (getLexer().getKind() == AsmToken::Identifier)
1598 RegName = Parser.getTok().getString().lower();
1600 return MatchOperand_ParseFail;
1602 int RegNum = matchMSA128RegisterName(RegName);
1604 if (RegNum < 0 || RegNum > 31)
1605 return MatchOperand_ParseFail;
1607 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1609 return MatchOperand_ParseFail;
1611 MipsOperand *Op = MipsOperand::CreateReg(RegVal, S,
1612 Parser.getTok().getLoc());
1613 Op->setRegKind(Kind);
1614 Operands.push_back(Op);
1616 Parser.Lex(); // Eat the register identifier.
1618 // MSA registers may be suffixed with an index in the form of:
1619 // 1) Immediate expression.
1620 // 2) General Purpose Register.
1622 // 1) copy_s.b $29,$w0[0]
1623 // 2) sld.b $w0,$w1[$1]
1625 if (Parser.getTok().isNot(AsmToken::LBrac))
1626 return MatchOperand_Success;
1628 MipsOperand *Mnemonic = static_cast<MipsOperand *>(Operands[0]);
1630 Operands.push_back(MipsOperand::CreateToken("[", Parser.getTok().getLoc()));
1631 Parser.Lex(); // Parse the '[' token.
1633 if (Parser.getTok().is(AsmToken::Dollar)) {
1634 // This must be a GPR.
1636 SMLoc VIdx = Parser.getTok().getLoc();
1637 Parser.Lex(); // Parse the '$' token.
1639 // GPR have aliases and we must account for that. Example: $30 == $fp
1640 if (getLexer().getKind() == AsmToken::Integer) {
1641 unsigned RegNum = Parser.getTok().getIntVal();
1642 int Reg = matchRegisterByNumber(
1643 RegNum, regKindToRegClass(MipsOperand::Kind_GPR32));
1645 Error(VIdx, "invalid general purpose register");
1646 return MatchOperand_ParseFail;
1649 RegOp = MipsOperand::CreateReg(Reg, VIdx, Parser.getTok().getLoc());
1650 } else if (getLexer().getKind() == AsmToken::Identifier) {
1652 std::string RegName = Parser.getTok().getString().lower();
1654 RegNum = matchCPURegisterName(RegName);
1656 Error(VIdx, "general purpose register expected");
1657 return MatchOperand_ParseFail;
1659 RegNum = getReg(regKindToRegClass(MipsOperand::Kind_GPR32), RegNum);
1660 RegOp = MipsOperand::CreateReg(RegNum, VIdx, Parser.getTok().getLoc());
1662 return MatchOperand_ParseFail;
1664 RegOp->setRegKind(MipsOperand::Kind_GPR32);
1665 Operands.push_back(RegOp);
1666 Parser.Lex(); // Eat the register identifier.
1668 if (Parser.getTok().isNot(AsmToken::RBrac))
1669 return MatchOperand_ParseFail;
1671 Operands.push_back(MipsOperand::CreateToken("]", Parser.getTok().getLoc()));
1672 Parser.Lex(); // Parse the ']' token.
1674 return MatchOperand_Success;
1677 // The index must be a constant expression then.
1678 SMLoc VIdx = Parser.getTok().getLoc();
1679 const MCExpr *ImmVal;
1681 if (getParser().parseExpression(ImmVal))
1682 return MatchOperand_ParseFail;
1684 const MCConstantExpr *expr = dyn_cast<MCConstantExpr>(ImmVal);
1685 if (!expr || !validateMSAIndex((int)expr->getValue(), Kind)) {
1686 Error(VIdx, "invalid immediate value");
1687 return MatchOperand_ParseFail;
1690 SMLoc E = Parser.getTok().getEndLoc();
1692 if (Parser.getTok().isNot(AsmToken::RBrac))
1693 return MatchOperand_ParseFail;
1695 bool insve = Mnemonic->getToken() == "insve.b" ||
1696 Mnemonic->getToken() == "insve.h" ||
1697 Mnemonic->getToken() == "insve.w" ||
1698 Mnemonic->getToken() == "insve.d";
1700 // The second vector index of insve instructions is always 0.
1701 if (insve && Operands.size() > 6) {
1702 if (expr->getValue() != 0) {
1703 Error(VIdx, "immediate value must be 0");
1704 return MatchOperand_ParseFail;
1706 Operands.push_back(MipsOperand::CreateToken("0", VIdx));
1708 Operands.push_back(MipsOperand::CreateImm(expr, VIdx, E));
1710 Operands.push_back(MipsOperand::CreateToken("]", Parser.getTok().getLoc()));
1712 Parser.Lex(); // Parse the ']' token.
1714 return MatchOperand_Success;
1717 MipsAsmParser::OperandMatchResultTy
1718 MipsAsmParser::parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1721 return MatchOperand_NoMatch;
1722 return parseRegs(Operands, (int) MipsOperand::Kind_GPR64);
1725 MipsAsmParser::OperandMatchResultTy
1726 MipsAsmParser::parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1727 return parseRegs(Operands, (int) MipsOperand::Kind_GPR32);
1730 MipsAsmParser::OperandMatchResultTy
1731 MipsAsmParser::parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1734 return MatchOperand_NoMatch;
1735 return parseRegs(Operands, (int) MipsOperand::Kind_AFGR64Regs);
1738 MipsAsmParser::OperandMatchResultTy
1739 MipsAsmParser::parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1741 return MatchOperand_NoMatch;
1742 return parseRegs(Operands, (int) MipsOperand::Kind_FGR64Regs);
1745 MipsAsmParser::OperandMatchResultTy
1746 MipsAsmParser::parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1747 return parseRegs(Operands, (int) MipsOperand::Kind_FGR32Regs);
1750 MipsAsmParser::OperandMatchResultTy
1751 MipsAsmParser::parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1752 return parseRegs(Operands, (int) MipsOperand::Kind_FGRH32Regs);
1755 MipsAsmParser::OperandMatchResultTy
1756 MipsAsmParser::parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1757 return parseRegs(Operands, (int) MipsOperand::Kind_FCCRegs);
1760 MipsAsmParser::OperandMatchResultTy
1761 MipsAsmParser::parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1762 return parseRegs(Operands, (int) MipsOperand::Kind_ACC64DSP);
1765 MipsAsmParser::OperandMatchResultTy
1766 MipsAsmParser::parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1767 // If the first token is not '$' we have an error.
1768 if (Parser.getTok().isNot(AsmToken::Dollar))
1769 return MatchOperand_NoMatch;
1771 SMLoc S = Parser.getTok().getLoc();
1772 Parser.Lex(); // Eat the '$'
1774 const AsmToken &Tok = Parser.getTok(); // Get next token.
1776 if (Tok.isNot(AsmToken::Identifier))
1777 return MatchOperand_NoMatch;
1779 if (!Tok.getIdentifier().startswith("ac"))
1780 return MatchOperand_NoMatch;
1782 StringRef NumString = Tok.getIdentifier().substr(2);
1785 if (NumString.getAsInteger(10, IntVal))
1786 return MatchOperand_NoMatch;
1788 unsigned Reg = matchRegisterByNumber(IntVal, Mips::LO32DSPRegClassID);
1790 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1791 Op->setRegKind(MipsOperand::Kind_LO32DSP);
1792 Operands.push_back(Op);
1794 Parser.Lex(); // Eat the register number.
1795 return MatchOperand_Success;
1798 MipsAsmParser::OperandMatchResultTy
1799 MipsAsmParser::parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1800 // If the first token is not '$' we have an error.
1801 if (Parser.getTok().isNot(AsmToken::Dollar))
1802 return MatchOperand_NoMatch;
1804 SMLoc S = Parser.getTok().getLoc();
1805 Parser.Lex(); // Eat the '$'
1807 const AsmToken &Tok = Parser.getTok(); // Get next token.
1809 if (Tok.isNot(AsmToken::Identifier))
1810 return MatchOperand_NoMatch;
1812 if (!Tok.getIdentifier().startswith("ac"))
1813 return MatchOperand_NoMatch;
1815 StringRef NumString = Tok.getIdentifier().substr(2);
1818 if (NumString.getAsInteger(10, IntVal))
1819 return MatchOperand_NoMatch;
1821 unsigned Reg = matchRegisterByNumber(IntVal, Mips::HI32DSPRegClassID);
1823 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1824 Op->setRegKind(MipsOperand::Kind_HI32DSP);
1825 Operands.push_back(Op);
1827 Parser.Lex(); // Eat the register number.
1828 return MatchOperand_Success;
1831 MipsAsmParser::OperandMatchResultTy
1832 MipsAsmParser::parseCOP2(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1833 // If the first token is not '$' we have an error.
1834 if (Parser.getTok().isNot(AsmToken::Dollar))
1835 return MatchOperand_NoMatch;
1837 SMLoc S = Parser.getTok().getLoc();
1838 Parser.Lex(); // Eat the '$'
1840 const AsmToken &Tok = Parser.getTok(); // Get next token.
1842 if (Tok.isNot(AsmToken::Integer))
1843 return MatchOperand_NoMatch;
1845 unsigned IntVal = Tok.getIntVal();
1847 unsigned Reg = matchRegisterByNumber(IntVal, Mips::COP2RegClassID);
1849 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1850 Op->setRegKind(MipsOperand::Kind_COP2);
1851 Operands.push_back(Op);
1853 Parser.Lex(); // Eat the register number.
1854 return MatchOperand_Success;
1857 MipsAsmParser::OperandMatchResultTy
1858 MipsAsmParser::parseMSA128BRegs(
1859 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1860 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128BRegs);
1863 MipsAsmParser::OperandMatchResultTy
1864 MipsAsmParser::parseMSA128HRegs(
1865 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1866 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128HRegs);
1869 MipsAsmParser::OperandMatchResultTy
1870 MipsAsmParser::parseMSA128WRegs(
1871 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1872 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128WRegs);
1875 MipsAsmParser::OperandMatchResultTy
1876 MipsAsmParser::parseMSA128DRegs(
1877 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1878 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128DRegs);
1881 bool MipsAsmParser::searchSymbolAlias(
1882 SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegKind) {
1884 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1886 SMLoc S = Parser.getTok().getLoc();
1888 if (Sym->isVariable())
1889 Expr = Sym->getVariableValue();
1892 if (Expr->getKind() == MCExpr::SymbolRef) {
1893 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind) RegKind;
1894 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
1895 const StringRef DefSymbol = Ref->getSymbol().getName();
1896 if (DefSymbol.startswith("$")) {
1898 APInt IntVal(32, -1);
1899 if (!DefSymbol.substr(1).getAsInteger(10, IntVal))
1900 RegNum = matchRegisterByNumber(IntVal.getZExtValue(),
1902 ? Mips::GPR64RegClassID
1903 : Mips::GPR32RegClassID);
1905 // Lookup for the register with the corresponding name.
1907 case MipsOperand::Kind_AFGR64Regs:
1908 case MipsOperand::Kind_FGR64Regs:
1909 RegNum = matchFPURegisterName(DefSymbol.substr(1));
1911 case MipsOperand::Kind_FGR32Regs:
1912 RegNum = matchFPURegisterName(DefSymbol.substr(1));
1914 case MipsOperand::Kind_GPR64:
1915 case MipsOperand::Kind_GPR32:
1917 RegNum = matchCPURegisterName(DefSymbol.substr(1));
1921 RegNum = getReg(regKindToRegClass(Kind), RegNum);
1925 MipsOperand *op = MipsOperand::CreateReg(RegNum, S,
1926 Parser.getTok().getLoc());
1927 op->setRegKind(Kind);
1928 Operands.push_back(op);
1932 } else if (Expr->getKind() == MCExpr::Constant) {
1934 const MCConstantExpr *Const = static_cast<const MCConstantExpr*>(Expr);
1935 MipsOperand *op = MipsOperand::CreateImm(Const, S,
1936 Parser.getTok().getLoc());
1937 Operands.push_back(op);
1944 MipsAsmParser::OperandMatchResultTy
1945 MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1946 return parseRegs(Operands, (int) MipsOperand::Kind_HWRegs);
1949 MipsAsmParser::OperandMatchResultTy
1950 MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1951 return parseRegs(Operands, (int) MipsOperand::Kind_CCRRegs);
1954 MipsAsmParser::OperandMatchResultTy
1955 MipsAsmParser::parseInvNum(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1956 const MCExpr *IdVal;
1957 // If the first token is '$' we may have register operand.
1958 if (Parser.getTok().is(AsmToken::Dollar))
1959 return MatchOperand_NoMatch;
1960 SMLoc S = Parser.getTok().getLoc();
1961 if (getParser().parseExpression(IdVal))
1962 return MatchOperand_ParseFail;
1963 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
1964 assert( MCE && "Unexpected MCExpr type.");
1965 int64_t Val = MCE->getValue();
1966 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1967 Operands.push_back(MipsOperand::CreateImm(
1968 MCConstantExpr::Create(0 - Val, getContext()), S, E));
1969 return MatchOperand_Success;
1972 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
1974 MCSymbolRefExpr::VariantKind VK
1975 = StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
1976 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
1977 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
1978 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
1979 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
1980 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
1981 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
1982 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
1983 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
1984 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
1985 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
1986 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
1987 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
1988 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
1989 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
1990 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
1991 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
1992 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
1993 .Default(MCSymbolRefExpr::VK_None);
1998 bool MipsAsmParser::
1999 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
2000 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2001 // Check if we have valid mnemonic
2002 if (!mnemonicIsValid(Name, 0)) {
2003 Parser.eatToEndOfStatement();
2004 return Error(NameLoc, "Unknown instruction");
2006 // First operand in MCInst is instruction mnemonic.
2007 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
2009 // Read the remaining operands.
2010 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2011 // Read the first operand.
2012 if (ParseOperand(Operands, Name)) {
2013 SMLoc Loc = getLexer().getLoc();
2014 Parser.eatToEndOfStatement();
2015 return Error(Loc, "unexpected token in argument list");
2018 while (getLexer().is(AsmToken::Comma)) {
2019 Parser.Lex(); // Eat the comma.
2020 // Parse and remember the operand.
2021 if (ParseOperand(Operands, Name)) {
2022 SMLoc Loc = getLexer().getLoc();
2023 Parser.eatToEndOfStatement();
2024 return Error(Loc, "unexpected token in argument list");
2028 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2029 SMLoc Loc = getLexer().getLoc();
2030 Parser.eatToEndOfStatement();
2031 return Error(Loc, "unexpected token in argument list");
2033 Parser.Lex(); // Consume the EndOfStatement.
2037 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
2038 SMLoc Loc = getLexer().getLoc();
2039 Parser.eatToEndOfStatement();
2040 return Error(Loc, ErrorMsg);
2043 bool MipsAsmParser::parseSetNoAtDirective() {
2044 // Line should look like: ".set noat".
2046 Options.setATReg(0);
2049 // If this is not the end of the statement, report an error.
2050 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2051 reportParseError("unexpected token in statement");
2054 Parser.Lex(); // Consume the EndOfStatement.
2058 bool MipsAsmParser::parseSetAtDirective() {
2059 // Line can be .set at - defaults to $1
2063 if (getLexer().is(AsmToken::EndOfStatement)) {
2064 Options.setATReg(1);
2065 Parser.Lex(); // Consume the EndOfStatement.
2067 } else if (getLexer().is(AsmToken::Equal)) {
2068 getParser().Lex(); // Eat the '='.
2069 if (getLexer().isNot(AsmToken::Dollar)) {
2070 reportParseError("unexpected token in statement");
2073 Parser.Lex(); // Eat the '$'.
2074 const AsmToken &Reg = Parser.getTok();
2075 if (Reg.is(AsmToken::Identifier)) {
2076 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
2077 } else if (Reg.is(AsmToken::Integer)) {
2078 AtRegNo = Reg.getIntVal();
2080 reportParseError("unexpected token in statement");
2084 if (AtRegNo < 1 || AtRegNo > 31) {
2085 reportParseError("unexpected token in statement");
2089 if (!Options.setATReg(AtRegNo)) {
2090 reportParseError("unexpected token in statement");
2093 getParser().Lex(); // Eat the register.
2095 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2096 reportParseError("unexpected token in statement");
2099 Parser.Lex(); // Consume the EndOfStatement.
2102 reportParseError("unexpected token in statement");
2107 bool MipsAsmParser::parseSetReorderDirective() {
2109 // If this is not the end of the statement, report an error.
2110 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2111 reportParseError("unexpected token in statement");
2114 Options.setReorder();
2115 Parser.Lex(); // Consume the EndOfStatement.
2119 bool MipsAsmParser::parseSetNoReorderDirective() {
2121 // If this is not the end of the statement, report an error.
2122 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2123 reportParseError("unexpected token in statement");
2126 Options.setNoreorder();
2127 Parser.Lex(); // Consume the EndOfStatement.
2131 bool MipsAsmParser::parseSetMacroDirective() {
2133 // If this is not the end of the statement, report an error.
2134 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2135 reportParseError("unexpected token in statement");
2139 Parser.Lex(); // Consume the EndOfStatement.
2143 bool MipsAsmParser::parseSetNoMacroDirective() {
2145 // If this is not the end of the statement, report an error.
2146 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2147 reportParseError("`noreorder' must be set before `nomacro'");
2150 if (Options.isReorder()) {
2151 reportParseError("`noreorder' must be set before `nomacro'");
2154 Options.setNomacro();
2155 Parser.Lex(); // Consume the EndOfStatement.
2159 bool MipsAsmParser::parseSetAssignment() {
2161 const MCExpr *Value;
2163 if (Parser.parseIdentifier(Name))
2164 reportParseError("expected identifier after .set");
2166 if (getLexer().isNot(AsmToken::Comma))
2167 return reportParseError("unexpected token in .set directive");
2170 if (getLexer().is(AsmToken::Dollar)) {
2172 SMLoc DollarLoc = getLexer().getLoc();
2173 // Consume the dollar sign, and check for a following identifier.
2175 // We have a '$' followed by something, make sure they are adjacent.
2176 if (DollarLoc.getPointer() + 1 != getTok().getLoc().getPointer())
2178 StringRef Res = StringRef(DollarLoc.getPointer(),
2179 getTok().getEndLoc().getPointer() - DollarLoc.getPointer());
2180 Symbol = getContext().GetOrCreateSymbol(Res);
2182 Value = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
2184 } else if (Parser.parseExpression(Value))
2185 return reportParseError("expected valid expression after comma");
2187 // Check if the Name already exists as a symbol.
2188 MCSymbol *Sym = getContext().LookupSymbol(Name);
2190 return reportParseError("symbol already defined");
2191 Sym = getContext().GetOrCreateSymbol(Name);
2192 Sym->setVariableValue(Value);
2197 bool MipsAsmParser::parseDirectiveSet() {
2199 // Get the next token.
2200 const AsmToken &Tok = Parser.getTok();
2202 if (Tok.getString() == "noat") {
2203 return parseSetNoAtDirective();
2204 } else if (Tok.getString() == "at") {
2205 return parseSetAtDirective();
2206 } else if (Tok.getString() == "reorder") {
2207 return parseSetReorderDirective();
2208 } else if (Tok.getString() == "noreorder") {
2209 return parseSetNoReorderDirective();
2210 } else if (Tok.getString() == "macro") {
2211 return parseSetMacroDirective();
2212 } else if (Tok.getString() == "nomacro") {
2213 return parseSetNoMacroDirective();
2214 } else if (Tok.getString() == "nomips16") {
2215 // Ignore this directive for now.
2216 Parser.eatToEndOfStatement();
2218 } else if (Tok.getString() == "nomicromips") {
2219 // Ignore this directive for now.
2220 Parser.eatToEndOfStatement();
2223 // It is just an identifier, look for an assignment.
2224 parseSetAssignment();
2231 bool MipsAsmParser::parseDirectiveMipsHackStocg() {
2232 MCAsmParser &Parser = getParser();
2234 if (Parser.parseIdentifier(Name))
2235 reportParseError("expected identifier");
2237 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
2238 if (getLexer().isNot(AsmToken::Comma))
2239 return TokError("unexpected token");
2243 if (Parser.parseAbsoluteExpression(Flags))
2244 return TokError("unexpected token");
2246 getTargetStreamer().emitMipsHackSTOCG(Sym, Flags);
2250 bool MipsAsmParser::parseDirectiveMipsHackELFFlags() {
2252 if (Parser.parseAbsoluteExpression(Flags))
2253 return TokError("unexpected token");
2255 getTargetStreamer().emitMipsHackELFFlags(Flags);
2259 /// parseDirectiveWord
2260 /// ::= .word [ expression (, expression)* ]
2261 bool MipsAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
2262 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2264 const MCExpr *Value;
2265 if (getParser().parseExpression(Value))
2268 getParser().getStreamer().EmitValue(Value, Size);
2270 if (getLexer().is(AsmToken::EndOfStatement))
2273 // FIXME: Improve diagnostic.
2274 if (getLexer().isNot(AsmToken::Comma))
2275 return Error(L, "unexpected token in directive");
2284 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
2286 StringRef IDVal = DirectiveID.getString();
2288 if (IDVal == ".ent") {
2289 // Ignore this directive for now.
2294 if (IDVal == ".end") {
2295 // Ignore this directive for now.
2300 if (IDVal == ".frame") {
2301 // Ignore this directive for now.
2302 Parser.eatToEndOfStatement();
2306 if (IDVal == ".set") {
2307 return parseDirectiveSet();
2310 if (IDVal == ".fmask") {
2311 // Ignore this directive for now.
2312 Parser.eatToEndOfStatement();
2316 if (IDVal == ".mask") {
2317 // Ignore this directive for now.
2318 Parser.eatToEndOfStatement();
2322 if (IDVal == ".gpword") {
2323 // Ignore this directive for now.
2324 Parser.eatToEndOfStatement();
2328 if (IDVal == ".word") {
2329 parseDirectiveWord(4, DirectiveID.getLoc());
2333 if (IDVal == ".mips_hack_stocg")
2334 return parseDirectiveMipsHackStocg();
2336 if (IDVal == ".mips_hack_elf_flags")
2337 return parseDirectiveMipsHackELFFlags();
2342 extern "C" void LLVMInitializeMipsAsmParser() {
2343 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
2344 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
2345 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
2346 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
2349 #define GET_REGISTER_MATCHER
2350 #define GET_MATCHER_IMPLEMENTATION
2351 #include "MipsGenAsmMatcher.inc"