1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCTargetDesc.h"
11 #include "MipsRegisterInfo.h"
12 #include "llvm/ADT/StringSwitch.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCStreamer.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCSymbol.h"
19 #include "llvm/MC/MCParser/MCAsmLexer.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/MC/MCTargetAsmParser.h"
22 #include "llvm/Support/TargetRegistry.h"
27 class MipsAssemblerOptions {
29 MipsAssemblerOptions():
30 aTReg(1), reorder(true), macro(true) {
33 unsigned getATRegNum() {return aTReg;}
34 bool setATReg(unsigned Reg);
36 bool isReorder() {return reorder;}
37 void setReorder() {reorder = true;}
38 void setNoreorder() {reorder = false;}
40 bool isMacro() {return macro;}
41 void setMacro() {macro = true;}
42 void setNomacro() {macro = false;}
52 class MipsAsmParser : public MCTargetAsmParser {
64 MipsAssemblerOptions Options;
67 #define GET_ASSEMBLER_HEADER
68 #include "MipsGenAsmMatcher.inc"
70 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
71 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
72 MCStreamer &Out, unsigned &ErrorInfo,
73 bool MatchingInlineAsm);
75 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
77 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
79 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
81 bool parseMathOperation(StringRef Name, SMLoc NameLoc,
82 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
84 bool ParseDirective(AsmToken DirectiveID);
86 MipsAsmParser::OperandMatchResultTy
87 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*>&);
89 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &,
92 int tryParseRegister(StringRef Mnemonic);
94 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
97 bool needsExpansion(MCInst &Inst);
99 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
100 SmallVectorImpl<MCInst> &Instructions);
101 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
102 SmallVectorImpl<MCInst> &Instructions);
103 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
104 SmallVectorImpl<MCInst> &Instructions);
105 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
106 SmallVectorImpl<MCInst> &Instructions);
107 bool reportParseError(StringRef ErrorMsg);
109 bool parseMemOffset(const MCExpr *&Res);
110 bool parseRelocOperand(const MCExpr *&Res);
112 bool parseDirectiveSet();
114 bool parseSetAtDirective();
115 bool parseSetNoAtDirective();
116 bool parseSetMacroDirective();
117 bool parseSetNoMacroDirective();
118 bool parseSetReorderDirective();
119 bool parseSetNoReorderDirective();
121 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
123 bool isMips64() const {
124 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
127 bool isFP64() const {
128 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
131 int matchRegisterName(StringRef Symbol);
133 int matchRegisterByNumber(unsigned RegNum, StringRef Mnemonic);
135 void setFpFormat(FpFormatTy Format) {
139 void setDefaultFpFormat();
141 void setFpFormat(StringRef Format);
143 FpFormatTy getFpFormat() {return FpFormat;}
145 bool requestsDoubleOperand(StringRef Mnemonic);
147 unsigned getReg(int RC,int RegNo);
151 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
152 : MCTargetAsmParser(), STI(sti), Parser(parser) {
153 // Initialize the set of available features.
154 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
157 MCAsmParser &getParser() const { return Parser; }
158 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
165 /// MipsOperand - Instances of this class represent a parsed Mips machine
167 class MipsOperand : public MCParsedAsmOperand {
179 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
201 SMLoc StartLoc, EndLoc;
204 void addRegOperands(MCInst &Inst, unsigned N) const {
205 assert(N == 1 && "Invalid number of operands!");
206 Inst.addOperand(MCOperand::CreateReg(getReg()));
209 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
210 // Add as immediate when possible. Null MCExpr = 0.
212 Inst.addOperand(MCOperand::CreateImm(0));
213 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
214 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
216 Inst.addOperand(MCOperand::CreateExpr(Expr));
219 void addImmOperands(MCInst &Inst, unsigned N) const {
220 assert(N == 1 && "Invalid number of operands!");
221 const MCExpr *Expr = getImm();
225 void addMemOperands(MCInst &Inst, unsigned N) const {
226 assert(N == 2 && "Invalid number of operands!");
228 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
230 const MCExpr *Expr = getMemOff();
234 bool isReg() const { return Kind == k_Register; }
235 bool isImm() const { return Kind == k_Immediate; }
236 bool isToken() const { return Kind == k_Token; }
237 bool isMem() const { return Kind == k_Memory; }
239 StringRef getToken() const {
240 assert(Kind == k_Token && "Invalid access!");
241 return StringRef(Tok.Data, Tok.Length);
244 unsigned getReg() const {
245 assert((Kind == k_Register) && "Invalid access!");
249 const MCExpr *getImm() const {
250 assert((Kind == k_Immediate) && "Invalid access!");
254 unsigned getMemBase() const {
255 assert((Kind == k_Memory) && "Invalid access!");
259 const MCExpr *getMemOff() const {
260 assert((Kind == k_Memory) && "Invalid access!");
264 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
265 MipsOperand *Op = new MipsOperand(k_Token);
266 Op->Tok.Data = Str.data();
267 Op->Tok.Length = Str.size();
273 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
274 MipsOperand *Op = new MipsOperand(k_Register);
275 Op->Reg.RegNum = RegNum;
281 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
282 MipsOperand *Op = new MipsOperand(k_Immediate);
289 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off,
291 MipsOperand *Op = new MipsOperand(k_Memory);
299 /// getStartLoc - Get the location of the first token of this operand.
300 SMLoc getStartLoc() const { return StartLoc; }
301 /// getEndLoc - Get the location of the last token of this operand.
302 SMLoc getEndLoc() const { return EndLoc; }
304 virtual void print(raw_ostream &OS) const {
305 llvm_unreachable("unimplemented!");
310 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
312 switch(Inst.getOpcode()) {
313 case Mips::LoadImm32Reg:
314 case Mips::LoadAddr32Imm:
315 case Mips::LoadAddr32Reg:
322 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
323 SmallVectorImpl<MCInst> &Instructions){
324 switch(Inst.getOpcode()) {
325 case Mips::LoadImm32Reg:
326 return expandLoadImm(Inst, IDLoc, Instructions);
327 case Mips::LoadAddr32Imm:
328 return expandLoadAddressImm(Inst,IDLoc,Instructions);
329 case Mips::LoadAddr32Reg:
330 return expandLoadAddressReg(Inst,IDLoc,Instructions);
334 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
335 SmallVectorImpl<MCInst> &Instructions){
337 const MCOperand &ImmOp = Inst.getOperand(1);
338 assert(ImmOp.isImm() && "expected immediate operand kind");
339 const MCOperand &RegOp = Inst.getOperand(0);
340 assert(RegOp.isReg() && "expected register operand kind");
342 int ImmValue = ImmOp.getImm();
343 tmpInst.setLoc(IDLoc);
344 if ( 0 <= ImmValue && ImmValue <= 65535) {
345 // for 0 <= j <= 65535.
346 // li d,j => ori d,$zero,j
347 tmpInst.setOpcode(isMips64() ? Mips::ORi64 : Mips::ORi);
348 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
350 MCOperand::CreateReg(isMips64() ? Mips::ZERO_64 : Mips::ZERO));
351 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
352 Instructions.push_back(tmpInst);
353 } else if ( ImmValue < 0 && ImmValue >= -32768) {
354 // for -32768 <= j < 0.
355 // li d,j => addiu d,$zero,j
356 tmpInst.setOpcode(Mips::ADDiu); //TODO:no ADDiu64 in td files?
357 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
359 MCOperand::CreateReg(isMips64() ? Mips::ZERO_64 : Mips::ZERO));
360 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
361 Instructions.push_back(tmpInst);
363 // for any other value of j that is representable as a 32-bit integer.
364 // li d,j => lui d,hi16(j)
366 tmpInst.setOpcode(isMips64() ? Mips::LUi64 : Mips::LUi);
367 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
368 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
369 Instructions.push_back(tmpInst);
371 tmpInst.setOpcode(isMips64() ? Mips::ORi64 : Mips::ORi);
372 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
373 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
374 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
375 tmpInst.setLoc(IDLoc);
376 Instructions.push_back(tmpInst);
380 void MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
381 SmallVectorImpl<MCInst> &Instructions){
383 const MCOperand &ImmOp = Inst.getOperand(2);
384 assert(ImmOp.isImm() && "expected immediate operand kind");
385 const MCOperand &SrcRegOp = Inst.getOperand(1);
386 assert(SrcRegOp.isReg() && "expected register operand kind");
387 const MCOperand &DstRegOp = Inst.getOperand(0);
388 assert(DstRegOp.isReg() && "expected register operand kind");
389 int ImmValue = ImmOp.getImm();
390 if ( -32768 <= ImmValue && ImmValue <= 65535) {
391 //for -32768 <= j <= 65535.
392 //la d,j(s) => addiu d,s,j
393 tmpInst.setOpcode(Mips::ADDiu); //TODO:no ADDiu64 in td files?
394 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
395 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
396 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
397 Instructions.push_back(tmpInst);
399 //for any other value of j that is representable as a 32-bit integer.
400 //la d,j(s) => lui d,hi16(j)
403 tmpInst.setOpcode(isMips64()?Mips::LUi64:Mips::LUi);
404 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
405 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
406 Instructions.push_back(tmpInst);
408 tmpInst.setOpcode(isMips64()?Mips::ORi64:Mips::ORi);
409 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
410 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
411 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
412 Instructions.push_back(tmpInst);
414 tmpInst.setOpcode(Mips::ADDu);
415 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
416 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
417 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
418 Instructions.push_back(tmpInst);
422 void MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
423 SmallVectorImpl<MCInst> &Instructions){
425 const MCOperand &ImmOp = Inst.getOperand(1);
426 assert(ImmOp.isImm() && "expected immediate operand kind");
427 const MCOperand &RegOp = Inst.getOperand(0);
428 assert(RegOp.isReg() && "expected register operand kind");
429 int ImmValue = ImmOp.getImm();
430 if ( -32768 <= ImmValue && ImmValue <= 65535) {
431 //for -32768 <= j <= 65535.
432 //la d,j => addiu d,$zero,j
433 tmpInst.setOpcode(Mips::ADDiu);
434 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
436 MCOperand::CreateReg(isMips64()?Mips::ZERO_64:Mips::ZERO));
437 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
438 Instructions.push_back(tmpInst);
440 //for any other value of j that is representable as a 32-bit integer.
441 //la d,j => lui d,hi16(j)
443 tmpInst.setOpcode(isMips64()?Mips::LUi64:Mips::LUi);
444 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
445 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
446 Instructions.push_back(tmpInst);
448 tmpInst.setOpcode(isMips64()?Mips::ORi64:Mips::ORi);
449 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
450 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
451 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
452 Instructions.push_back(tmpInst);
457 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
458 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
459 MCStreamer &Out, unsigned &ErrorInfo,
460 bool MatchingInlineAsm) {
462 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
465 switch (MatchResult) {
467 case Match_Success: {
468 if (needsExpansion(Inst)) {
469 SmallVector<MCInst, 4> Instructions;
470 expandInstruction(Inst, IDLoc, Instructions);
471 for(unsigned i =0; i < Instructions.size(); i++){
472 Out.EmitInstruction(Instructions[i]);
476 Out.EmitInstruction(Inst);
480 case Match_MissingFeature:
481 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
483 case Match_InvalidOperand: {
484 SMLoc ErrorLoc = IDLoc;
485 if (ErrorInfo != ~0U) {
486 if (ErrorInfo >= Operands.size())
487 return Error(IDLoc, "too few operands for instruction");
489 ErrorLoc = ((MipsOperand*)Operands[ErrorInfo])->getStartLoc();
490 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
493 return Error(ErrorLoc, "invalid operand for instruction");
495 case Match_MnemonicFail:
496 return Error(IDLoc, "invalid instruction");
501 int MipsAsmParser::matchRegisterName(StringRef Name) {
505 CC = StringSwitch<unsigned>(Name)
506 .Case("zero", Mips::ZERO)
507 .Case("a0", Mips::A0)
508 .Case("a1", Mips::A1)
509 .Case("a2", Mips::A2)
510 .Case("a3", Mips::A3)
511 .Case("v0", Mips::V0)
512 .Case("v1", Mips::V1)
513 .Case("s0", Mips::S0)
514 .Case("s1", Mips::S1)
515 .Case("s2", Mips::S2)
516 .Case("s3", Mips::S3)
517 .Case("s4", Mips::S4)
518 .Case("s5", Mips::S5)
519 .Case("s6", Mips::S6)
520 .Case("s7", Mips::S7)
521 .Case("k0", Mips::K0)
522 .Case("k1", Mips::K1)
523 .Case("sp", Mips::SP)
524 .Case("fp", Mips::FP)
525 .Case("gp", Mips::GP)
526 .Case("ra", Mips::RA)
527 .Case("t0", Mips::T0)
528 .Case("t1", Mips::T1)
529 .Case("t2", Mips::T2)
530 .Case("t3", Mips::T3)
531 .Case("t4", Mips::T4)
532 .Case("t5", Mips::T5)
533 .Case("t6", Mips::T6)
534 .Case("t7", Mips::T7)
535 .Case("t8", Mips::T8)
536 .Case("t9", Mips::T9)
537 .Case("at", Mips::AT)
538 .Case("fcc0", Mips::FCC0)
541 CC = StringSwitch<unsigned>(Name)
542 .Case("zero", Mips::ZERO_64)
543 .Case("at", Mips::AT_64)
544 .Case("v0", Mips::V0_64)
545 .Case("v1", Mips::V1_64)
546 .Case("a0", Mips::A0_64)
547 .Case("a1", Mips::A1_64)
548 .Case("a2", Mips::A2_64)
549 .Case("a3", Mips::A3_64)
550 .Case("a4", Mips::T0_64)
551 .Case("a5", Mips::T1_64)
552 .Case("a6", Mips::T2_64)
553 .Case("a7", Mips::T3_64)
554 .Case("t4", Mips::T4_64)
555 .Case("t5", Mips::T5_64)
556 .Case("t6", Mips::T6_64)
557 .Case("t7", Mips::T7_64)
558 .Case("s0", Mips::S0_64)
559 .Case("s1", Mips::S1_64)
560 .Case("s2", Mips::S2_64)
561 .Case("s3", Mips::S3_64)
562 .Case("s4", Mips::S4_64)
563 .Case("s5", Mips::S5_64)
564 .Case("s6", Mips::S6_64)
565 .Case("s7", Mips::S7_64)
566 .Case("t8", Mips::T8_64)
567 .Case("t9", Mips::T9_64)
568 .Case("kt0", Mips::K0_64)
569 .Case("kt1", Mips::K1_64)
570 .Case("gp", Mips::GP_64)
571 .Case("sp", Mips::SP_64)
572 .Case("fp", Mips::FP_64)
573 .Case("s8", Mips::FP_64)
574 .Case("ra", Mips::RA_64)
580 if (Name[0] == 'f') {
581 StringRef NumString = Name.substr(1);
583 if( NumString.getAsInteger(10, IntVal))
584 return -1; // not integer
588 FpFormatTy Format = getFpFormat();
590 if (Format == FP_FORMAT_S || Format == FP_FORMAT_W)
591 return getReg(Mips::FGR32RegClassID, IntVal);
592 if (Format == FP_FORMAT_D) {
594 return getReg(Mips::FGR64RegClassID, IntVal);
596 // only even numbers available as register pairs
597 if (( IntVal > 31) || (IntVal%2 != 0))
599 return getReg(Mips::AFGR64RegClassID, IntVal/2);
605 void MipsAsmParser::setDefaultFpFormat() {
607 if (isMips64() || isFP64())
608 FpFormat = FP_FORMAT_D;
610 FpFormat = FP_FORMAT_S;
613 bool MipsAsmParser::requestsDoubleOperand(StringRef Mnemonic){
615 bool IsDouble = StringSwitch<bool>(Mnemonic.lower())
624 void MipsAsmParser::setFpFormat(StringRef Format) {
626 FpFormat = StringSwitch<FpFormatTy>(Format.lower())
627 .Case(".s", FP_FORMAT_S)
628 .Case(".d", FP_FORMAT_D)
629 .Case(".l", FP_FORMAT_L)
630 .Case(".w", FP_FORMAT_W)
631 .Default(FP_FORMAT_NONE);
634 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
642 unsigned MipsAsmParser::getATReg() {
643 unsigned Reg = Options.getATRegNum();
645 return getReg(Mips::CPU64RegsRegClassID,Reg);
647 return getReg(Mips::CPURegsRegClassID,Reg);
650 unsigned MipsAsmParser::getReg(int RC,int RegNo) {
651 return *(getContext().getRegisterInfo().getRegClass(RC).begin() + RegNo);
654 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, StringRef Mnemonic) {
656 if (Mnemonic.lower() == "rdhwr") {
657 // at the moment only hwreg29 is supported
666 // MIPS64 registers are numbered 1 after the 32-bit equivalents
667 return getReg(Mips::CPURegsRegClassID, RegNum) + isMips64();
670 int MipsAsmParser::tryParseRegister(StringRef Mnemonic) {
671 const AsmToken &Tok = Parser.getTok();
674 if (Tok.is(AsmToken::Identifier)) {
675 std::string lowerCase = Tok.getString().lower();
676 RegNum = matchRegisterName(lowerCase);
677 } else if (Tok.is(AsmToken::Integer))
678 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
681 return RegNum; //error
682 // 64 bit div operations require Mips::ZERO instead of MIPS::ZERO_64
683 if (isMips64() && RegNum == Mips::ZERO_64) {
684 if (Mnemonic.find("ddiv") != StringRef::npos)
691 tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
694 SMLoc S = Parser.getTok().getLoc();
697 // FIXME: we should make a more generic method for CCR
698 if ((Mnemonic == "cfc1" || Mnemonic == "ctc1")
699 && Operands.size() == 2 && Parser.getTok().is(AsmToken::Integer)){
700 RegNo = Parser.getTok().getIntVal(); // get the int value
701 // at the moment only fcc0 is supported
705 RegNo = tryParseRegister(Mnemonic);
709 Operands.push_back(MipsOperand::CreateReg(RegNo, S,
710 Parser.getTok().getLoc()));
711 Parser.Lex(); // Eat register token.
715 bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
716 StringRef Mnemonic) {
717 // Check if the current operand has a custom associated parser, if so, try to
718 // custom parse the operand, or fallback to the general approach.
719 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
720 if (ResTy == MatchOperand_Success)
722 // If there wasn't a custom match, try the generic matcher below. Otherwise,
723 // there was a match, but an error occurred, in which case, just return that
724 // the operand parsing failed.
725 if (ResTy == MatchOperand_ParseFail)
728 switch (getLexer().getKind()) {
730 Error(Parser.getTok().getLoc(), "unexpected token in operand");
732 case AsmToken::Dollar: {
734 SMLoc S = Parser.getTok().getLoc();
735 Parser.Lex(); // Eat dollar token.
736 // parse register operand
737 if (!tryParseRegisterOperand(Operands, Mnemonic)) {
738 if (getLexer().is(AsmToken::LParen)) {
739 // check if it is indexed addressing operand
740 Operands.push_back(MipsOperand::CreateToken("(", S));
741 Parser.Lex(); // eat parenthesis
742 if (getLexer().isNot(AsmToken::Dollar))
745 Parser.Lex(); // eat dollar
746 if (tryParseRegisterOperand(Operands, Mnemonic))
749 if (!getLexer().is(AsmToken::RParen))
752 S = Parser.getTok().getLoc();
753 Operands.push_back(MipsOperand::CreateToken(")", S));
758 // maybe it is a symbol reference
759 StringRef Identifier;
760 if (Parser.ParseIdentifier(Identifier))
763 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
765 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
767 // Otherwise create a symbol ref.
768 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
771 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
774 case AsmToken::Identifier:
775 case AsmToken::LParen:
776 case AsmToken::Minus:
778 case AsmToken::Integer:
779 case AsmToken::String: {
780 // quoted label names
782 SMLoc S = Parser.getTok().getLoc();
783 if (getParser().ParseExpression(IdVal))
785 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
786 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
789 case AsmToken::Percent: {
790 // it is a symbol reference or constant expression
792 SMLoc S = Parser.getTok().getLoc(); // start location of the operand
793 if (parseRelocOperand(IdVal))
796 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
798 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
800 } // case AsmToken::Percent
801 } // switch(getLexer().getKind())
805 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
807 Parser.Lex(); // eat % token
808 const AsmToken &Tok = Parser.getTok(); // get next token, operation
809 if (Tok.isNot(AsmToken::Identifier))
812 std::string Str = Tok.getIdentifier().str();
814 Parser.Lex(); // eat identifier
815 // now make expression from the rest of the operand
819 if (getLexer().getKind() == AsmToken::LParen) {
821 Parser.Lex(); // eat '(' token
822 if (getLexer().getKind() == AsmToken::Percent) {
823 Parser.Lex(); // eat % token
824 const AsmToken &nextTok = Parser.getTok();
825 if (nextTok.isNot(AsmToken::Identifier))
828 Str += nextTok.getIdentifier();
829 Parser.Lex(); // eat identifier
830 if (getLexer().getKind() != AsmToken::LParen)
835 if (getParser().ParseParenExpression(IdVal,EndLoc))
838 while (getLexer().getKind() == AsmToken::RParen)
839 Parser.Lex(); // eat ')' token
842 return true; // parenthesis must follow reloc operand
844 // Check the type of the expression
845 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal)) {
846 // it's a constant, evaluate lo or hi value
847 int Val = MCE->getValue();
850 } else if (Str == "hi") {
851 Val = (Val & 0xffff0000) >> 16;
853 Res = MCConstantExpr::Create(Val, getContext());
857 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(IdVal)) {
858 // it's a symbol, create symbolic expression from symbol
859 StringRef Symbol = MSRE->getSymbol().getName();
860 MCSymbolRefExpr::VariantKind VK = getVariantKind(Str);
861 Res = MCSymbolRefExpr::Create(Symbol,VK,getContext());
867 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
870 StartLoc = Parser.getTok().getLoc();
871 RegNo = tryParseRegister("");
872 EndLoc = Parser.getTok().getLoc();
873 return (RegNo == (unsigned)-1);
876 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res) {
880 switch(getLexer().getKind()) {
883 case AsmToken::Integer:
884 case AsmToken::Minus:
886 return (getParser().ParseExpression(Res));
887 case AsmToken::Percent:
888 return parseRelocOperand(Res);
889 case AsmToken::LParen:
890 return false; // it's probably assuming 0
895 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
896 SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
898 const MCExpr *IdVal = 0;
900 // first operand is the offset
901 S = Parser.getTok().getLoc();
903 if (parseMemOffset(IdVal))
904 return MatchOperand_ParseFail;
906 const AsmToken &Tok = Parser.getTok(); // get next token
907 if (Tok.isNot(AsmToken::LParen)) {
908 MipsOperand *Mnemonic = static_cast<MipsOperand*>(Operands[0]);
909 if (Mnemonic->getToken() == "la") {
910 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
911 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
912 return MatchOperand_Success;
914 Error(Parser.getTok().getLoc(), "'(' expected");
915 return MatchOperand_ParseFail;
918 Parser.Lex(); // Eat '(' token.
920 const AsmToken &Tok1 = Parser.getTok(); // get next token
921 if (Tok1.is(AsmToken::Dollar)) {
922 Parser.Lex(); // Eat '$' token.
923 if (tryParseRegisterOperand(Operands,"")) {
924 Error(Parser.getTok().getLoc(), "unexpected token in operand");
925 return MatchOperand_ParseFail;
929 Error(Parser.getTok().getLoc(), "unexpected token in operand");
930 return MatchOperand_ParseFail;
933 const AsmToken &Tok2 = Parser.getTok(); // get next token
934 if (Tok2.isNot(AsmToken::RParen)) {
935 Error(Parser.getTok().getLoc(), "')' expected");
936 return MatchOperand_ParseFail;
939 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
941 Parser.Lex(); // Eat ')' token.
944 IdVal = MCConstantExpr::Create(0, getContext());
946 // now replace register operand with the mem operand
947 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
948 int RegNo = op->getReg();
949 // remove register from operands
951 // and add memory operand
952 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
954 return MatchOperand_Success;
957 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
959 MCSymbolRefExpr::VariantKind VK
960 = StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
961 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
962 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
963 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
964 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
965 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
966 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
967 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
968 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
969 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
970 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
971 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
972 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
973 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
974 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
975 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
976 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
977 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
978 .Default(MCSymbolRefExpr::VK_None);
983 static int ConvertCcString(StringRef CondString) {
984 int CC = StringSwitch<unsigned>(CondString)
1006 bool MipsAsmParser::
1007 parseMathOperation(StringRef Name, SMLoc NameLoc,
1008 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1010 size_t Start = Name.find('.'), Next = Name.rfind('.');
1011 StringRef Format1 = Name.slice(Start, Next);
1012 // and add the first format to the operands
1013 Operands.push_back(MipsOperand::CreateToken(Format1, NameLoc));
1014 // now for the second format
1015 StringRef Format2 = Name.slice(Next, StringRef::npos);
1016 Operands.push_back(MipsOperand::CreateToken(Format2, NameLoc));
1018 // set the format for the first register
1019 setFpFormat(Format1);
1021 // Read the remaining operands.
1022 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1023 // Read the first operand.
1024 if (ParseOperand(Operands, Name)) {
1025 SMLoc Loc = getLexer().getLoc();
1026 Parser.EatToEndOfStatement();
1027 return Error(Loc, "unexpected token in argument list");
1030 if (getLexer().isNot(AsmToken::Comma)) {
1031 SMLoc Loc = getLexer().getLoc();
1032 Parser.EatToEndOfStatement();
1033 return Error(Loc, "unexpected token in argument list");
1036 Parser.Lex(); // Eat the comma.
1038 //set the format for the first register
1039 setFpFormat(Format2);
1041 // Parse and remember the operand.
1042 if (ParseOperand(Operands, Name)) {
1043 SMLoc Loc = getLexer().getLoc();
1044 Parser.EatToEndOfStatement();
1045 return Error(Loc, "unexpected token in argument list");
1049 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1050 SMLoc Loc = getLexer().getLoc();
1051 Parser.EatToEndOfStatement();
1052 return Error(Loc, "unexpected token in argument list");
1055 Parser.Lex(); // Consume the EndOfStatement
1059 bool MipsAsmParser::
1060 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1061 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1062 // floating point instructions: should register be treated as double?
1063 if (requestsDoubleOperand(Name)) {
1064 setFpFormat(FP_FORMAT_D);
1065 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
1068 setDefaultFpFormat();
1069 // Create the leading tokens for the mnemonic, split by '.' characters.
1070 size_t Start = 0, Next = Name.find('.');
1071 StringRef Mnemonic = Name.slice(Start, Next);
1073 Operands.push_back(MipsOperand::CreateToken(Mnemonic, NameLoc));
1075 if (Next != StringRef::npos) {
1076 // there is a format token in mnemonic
1077 // StringRef Rest = Name.slice(Next, StringRef::npos);
1078 size_t Dot = Name.find('.', Next+1);
1079 StringRef Format = Name.slice(Next, Dot);
1080 if (Dot == StringRef::npos) //only one '.' in a string, it's a format
1081 Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
1083 if (Name.startswith("c.")){
1084 // floating point compare, add '.' and immediate represent for cc
1085 Operands.push_back(MipsOperand::CreateToken(".", NameLoc));
1086 int Cc = ConvertCcString(Format);
1088 return Error(NameLoc, "Invalid conditional code");
1090 SMLoc E = SMLoc::getFromPointer(
1091 Parser.getTok().getLoc().getPointer() -1 );
1092 Operands.push_back(MipsOperand::CreateImm(
1093 MCConstantExpr::Create(Cc, getContext()), NameLoc, E));
1095 // trunc, ceil, floor ...
1096 return parseMathOperation(Name, NameLoc, Operands);
1099 // the rest is a format
1100 Format = Name.slice(Dot, StringRef::npos);
1101 Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
1104 setFpFormat(Format);
1108 // Read the remaining operands.
1109 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1110 // Read the first operand.
1111 if (ParseOperand(Operands, Name)) {
1112 SMLoc Loc = getLexer().getLoc();
1113 Parser.EatToEndOfStatement();
1114 return Error(Loc, "unexpected token in argument list");
1117 while (getLexer().is(AsmToken::Comma) ) {
1118 Parser.Lex(); // Eat the comma.
1120 // Parse and remember the operand.
1121 if (ParseOperand(Operands, Name)) {
1122 SMLoc Loc = getLexer().getLoc();
1123 Parser.EatToEndOfStatement();
1124 return Error(Loc, "unexpected token in argument list");
1129 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1130 SMLoc Loc = getLexer().getLoc();
1131 Parser.EatToEndOfStatement();
1132 return Error(Loc, "unexpected token in argument list");
1135 Parser.Lex(); // Consume the EndOfStatement
1139 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
1140 SMLoc Loc = getLexer().getLoc();
1141 Parser.EatToEndOfStatement();
1142 return Error(Loc, ErrorMsg);
1145 bool MipsAsmParser::parseSetNoAtDirective() {
1146 // line should look like:
1149 Options.setATReg(0);
1152 // if this is not the end of the statement, report error
1153 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1154 reportParseError("unexpected token in statement");
1157 Parser.Lex(); // Consume the EndOfStatement
1160 bool MipsAsmParser::parseSetAtDirective() {
1162 // .set at - defaults to $1
1165 if (getLexer().is(AsmToken::EndOfStatement)) {
1166 Options.setATReg(1);
1167 Parser.Lex(); // Consume the EndOfStatement
1169 } else if (getLexer().is(AsmToken::Equal)) {
1170 getParser().Lex(); //eat '='
1171 if (getLexer().isNot(AsmToken::Dollar)) {
1172 reportParseError("unexpected token in statement");
1175 Parser.Lex(); // eat '$'
1176 if (getLexer().isNot(AsmToken::Integer)) {
1177 reportParseError("unexpected token in statement");
1180 const AsmToken &Reg = Parser.getTok();
1181 if (!Options.setATReg(Reg.getIntVal())) {
1182 reportParseError("unexpected token in statement");
1185 getParser().Lex(); //eat reg
1187 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1188 reportParseError("unexpected token in statement");
1191 Parser.Lex(); // Consume the EndOfStatement
1194 reportParseError("unexpected token in statement");
1199 bool MipsAsmParser::parseSetReorderDirective() {
1201 // if this is not the end of the statement, report error
1202 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1203 reportParseError("unexpected token in statement");
1206 Options.setReorder();
1207 Parser.Lex(); // Consume the EndOfStatement
1211 bool MipsAsmParser::parseSetNoReorderDirective() {
1213 // if this is not the end of the statement, report error
1214 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1215 reportParseError("unexpected token in statement");
1218 Options.setNoreorder();
1219 Parser.Lex(); // Consume the EndOfStatement
1223 bool MipsAsmParser::parseSetMacroDirective() {
1225 // if this is not the end of the statement, report error
1226 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1227 reportParseError("unexpected token in statement");
1231 Parser.Lex(); // Consume the EndOfStatement
1235 bool MipsAsmParser::parseSetNoMacroDirective() {
1237 // if this is not the end of the statement, report error
1238 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1239 reportParseError("`noreorder' must be set before `nomacro'");
1242 if (Options.isReorder()) {
1243 reportParseError("`noreorder' must be set before `nomacro'");
1246 Options.setNomacro();
1247 Parser.Lex(); // Consume the EndOfStatement
1250 bool MipsAsmParser::parseDirectiveSet() {
1253 const AsmToken &Tok = Parser.getTok();
1255 if (Tok.getString() == "noat") {
1256 return parseSetNoAtDirective();
1257 } else if (Tok.getString() == "at") {
1258 return parseSetAtDirective();
1259 } else if (Tok.getString() == "reorder") {
1260 return parseSetReorderDirective();
1261 } else if (Tok.getString() == "noreorder") {
1262 return parseSetNoReorderDirective();
1263 } else if (Tok.getString() == "macro") {
1264 return parseSetMacroDirective();
1265 } else if (Tok.getString() == "nomacro") {
1266 return parseSetNoMacroDirective();
1267 } else if (Tok.getString() == "nomips16") {
1268 // ignore this directive for now
1269 Parser.EatToEndOfStatement();
1271 } else if (Tok.getString() == "nomicromips") {
1272 // ignore this directive for now
1273 Parser.EatToEndOfStatement();
1279 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
1281 if (DirectiveID.getString() == ".ent") {
1282 // ignore this directive for now
1287 if (DirectiveID.getString() == ".end") {
1288 // ignore this directive for now
1293 if (DirectiveID.getString() == ".frame") {
1294 // ignore this directive for now
1295 Parser.EatToEndOfStatement();
1299 if (DirectiveID.getString() == ".set") {
1300 return parseDirectiveSet();
1303 if (DirectiveID.getString() == ".fmask") {
1304 // ignore this directive for now
1305 Parser.EatToEndOfStatement();
1309 if (DirectiveID.getString() == ".mask") {
1310 // ignore this directive for now
1311 Parser.EatToEndOfStatement();
1315 if (DirectiveID.getString() == ".gpword") {
1316 // ignore this directive for now
1317 Parser.EatToEndOfStatement();
1324 extern "C" void LLVMInitializeMipsAsmParser() {
1325 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
1326 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
1327 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
1328 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
1331 #define GET_REGISTER_MATCHER
1332 #define GET_MATCHER_IMPLEMENTATION
1333 #include "MipsGenAsmMatcher.inc"