1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCTargetDesc.h"
11 #include "MipsRegisterInfo.h"
12 #include "llvm/ADT/StringSwitch.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCParser/MCAsmLexer.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/MC/MCSymbol.h"
21 #include "llvm/MC/MCTargetAsmParser.h"
22 #include "llvm/Support/TargetRegistry.h"
27 class MipsAssemblerOptions {
29 MipsAssemblerOptions():
30 aTReg(1), reorder(true), macro(true) {
33 unsigned getATRegNum() {return aTReg;}
34 bool setATReg(unsigned Reg);
36 bool isReorder() {return reorder;}
37 void setReorder() {reorder = true;}
38 void setNoreorder() {reorder = false;}
40 bool isMacro() {return macro;}
41 void setMacro() {macro = true;}
42 void setNomacro() {macro = false;}
52 class MipsAsmParser : public MCTargetAsmParser {
64 MipsAssemblerOptions Options;
66 #define GET_ASSEMBLER_HEADER
67 #include "MipsGenAsmMatcher.inc"
69 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
70 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
71 MCStreamer &Out, unsigned &ErrorInfo,
72 bool MatchingInlineAsm);
74 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
76 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
78 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
80 bool parseMathOperation(StringRef Name, SMLoc NameLoc,
81 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
83 bool ParseDirective(AsmToken DirectiveID);
85 MipsAsmParser::OperandMatchResultTy
86 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
88 MipsAsmParser::OperandMatchResultTy
89 parseCPURegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
91 MipsAsmParser::OperandMatchResultTy
92 parseCPU64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
94 MipsAsmParser::OperandMatchResultTy
95 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
97 MipsAsmParser::OperandMatchResultTy
98 parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
100 MipsAsmParser::OperandMatchResultTy
101 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
103 bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
104 unsigned RegisterClass);
106 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &,
109 int tryParseRegister(bool is64BitReg);
111 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
114 bool needsExpansion(MCInst &Inst);
116 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
117 SmallVectorImpl<MCInst> &Instructions);
118 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
119 SmallVectorImpl<MCInst> &Instructions);
120 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
121 SmallVectorImpl<MCInst> &Instructions);
122 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
123 SmallVectorImpl<MCInst> &Instructions);
124 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
125 SmallVectorImpl<MCInst> &Instructions,
126 bool isLoad,bool isImmOpnd);
127 bool reportParseError(StringRef ErrorMsg);
129 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
130 bool parseRelocOperand(const MCExpr *&Res);
132 const MCExpr* evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
134 bool isEvaluated(const MCExpr *Expr);
135 bool parseDirectiveSet();
137 bool parseSetAtDirective();
138 bool parseSetNoAtDirective();
139 bool parseSetMacroDirective();
140 bool parseSetNoMacroDirective();
141 bool parseSetReorderDirective();
142 bool parseSetNoReorderDirective();
144 bool parseSetAssignment();
146 bool parseDirectiveWord(unsigned Size, SMLoc L);
148 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
150 bool isMips64() const {
151 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
154 bool isFP64() const {
155 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
158 int matchRegisterName(StringRef Symbol, bool is64BitReg);
160 int matchCPURegisterName(StringRef Symbol);
162 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
164 void setFpFormat(FpFormatTy Format) {
168 void setDefaultFpFormat();
170 void setFpFormat(StringRef Format);
172 FpFormatTy getFpFormat() {return FpFormat;}
174 bool requestsDoubleOperand(StringRef Mnemonic);
176 unsigned getReg(int RC, int RegNo);
180 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
181 SmallVectorImpl<MCInst> &Instructions);
183 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
184 : MCTargetAsmParser(), STI(sti), Parser(parser) {
185 // Initialize the set of available features.
186 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
189 MCAsmParser &getParser() const { return Parser; }
190 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
197 /// MipsOperand - Instances of this class represent a parsed Mips machine
199 class MipsOperand : public MCParsedAsmOperand {
225 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
253 SMLoc StartLoc, EndLoc;
256 void addRegOperands(MCInst &Inst, unsigned N) const {
257 assert(N == 1 && "Invalid number of operands!");
258 Inst.addOperand(MCOperand::CreateReg(getReg()));
261 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
262 // Add as immediate when possible. Null MCExpr = 0.
264 Inst.addOperand(MCOperand::CreateImm(0));
265 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
266 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
268 Inst.addOperand(MCOperand::CreateExpr(Expr));
271 void addImmOperands(MCInst &Inst, unsigned N) const {
272 assert(N == 1 && "Invalid number of operands!");
273 const MCExpr *Expr = getImm();
277 void addMemOperands(MCInst &Inst, unsigned N) const {
278 assert(N == 2 && "Invalid number of operands!");
280 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
282 const MCExpr *Expr = getMemOff();
286 bool isReg() const { return Kind == k_Register; }
287 bool isImm() const { return Kind == k_Immediate; }
288 bool isToken() const { return Kind == k_Token; }
289 bool isMem() const { return Kind == k_Memory; }
291 StringRef getToken() const {
292 assert(Kind == k_Token && "Invalid access!");
293 return StringRef(Tok.Data, Tok.Length);
296 unsigned getReg() const {
297 assert((Kind == k_Register) && "Invalid access!");
301 void setRegKind(RegisterKind RegKind) {
302 assert((Kind == k_Register) && "Invalid access!");
306 const MCExpr *getImm() const {
307 assert((Kind == k_Immediate) && "Invalid access!");
311 unsigned getMemBase() const {
312 assert((Kind == k_Memory) && "Invalid access!");
316 const MCExpr *getMemOff() const {
317 assert((Kind == k_Memory) && "Invalid access!");
321 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
322 MipsOperand *Op = new MipsOperand(k_Token);
323 Op->Tok.Data = Str.data();
324 Op->Tok.Length = Str.size();
330 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
331 MipsOperand *Op = new MipsOperand(k_Register);
332 Op->Reg.RegNum = RegNum;
338 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
339 MipsOperand *Op = new MipsOperand(k_Immediate);
346 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off,
348 MipsOperand *Op = new MipsOperand(k_Memory);
356 bool isCPURegsAsm() const {
357 return Kind == k_Register && Reg.Kind == Kind_CPURegs;
359 void addCPURegsAsmOperands(MCInst &Inst, unsigned N) const {
360 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
363 bool isCPU64RegsAsm() const {
364 return Kind == k_Register && Reg.Kind == Kind_CPU64Regs;
366 void addCPU64RegsAsmOperands(MCInst &Inst, unsigned N) const {
367 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
370 bool isHWRegsAsm() const {
371 assert((Kind == k_Register) && "Invalid access!");
372 return Reg.Kind == Kind_HWRegs;
374 void addHWRegsAsmOperands(MCInst &Inst, unsigned N) const {
375 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
378 bool isHW64RegsAsm() const {
379 assert((Kind == k_Register) && "Invalid access!");
380 return Reg.Kind == Kind_HW64Regs;
382 void addHW64RegsAsmOperands(MCInst &Inst, unsigned N) const {
383 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
386 void addCCRAsmOperands(MCInst &Inst, unsigned N) const {
387 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
390 bool isCCRAsm() const {
391 assert((Kind == k_Register) && "Invalid access!");
392 return Reg.Kind == Kind_CCRRegs;
395 /// getStartLoc - Get the location of the first token of this operand.
396 SMLoc getStartLoc() const {
399 /// getEndLoc - Get the location of the last token of this operand.
400 SMLoc getEndLoc() const {
404 virtual void print(raw_ostream &OS) const {
405 llvm_unreachable("unimplemented!");
407 }; // class MipsOperand
411 extern const MCInstrDesc MipsInsts[];
413 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
414 return MipsInsts[Opcode];
417 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
418 SmallVectorImpl<MCInst> &Instructions) {
419 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
421 if (MCID.mayLoad() || MCID.mayStore()) {
422 // Check the offset of memory operand, if it is a symbol
423 // reference or immediate we may have to expand instructions.
424 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
425 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
426 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY)
427 || (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
428 MCOperand &Op = Inst.getOperand(i);
430 int MemOffset = Op.getImm();
431 if (MemOffset < -32768 || MemOffset > 32767) {
432 // Offset can't exceed 16bit value.
433 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
436 } else if (Op.isExpr()) {
437 const MCExpr *Expr = Op.getExpr();
438 if (Expr->getKind() == MCExpr::SymbolRef) {
439 const MCSymbolRefExpr *SR =
440 static_cast<const MCSymbolRefExpr*>(Expr);
441 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
443 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
446 } else if (!isEvaluated(Expr)) {
447 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
455 if (needsExpansion(Inst))
456 expandInstruction(Inst, IDLoc, Instructions);
458 Instructions.push_back(Inst);
463 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
465 switch (Inst.getOpcode()) {
466 case Mips::LoadImm32Reg:
467 case Mips::LoadAddr32Imm:
468 case Mips::LoadAddr32Reg:
475 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
476 SmallVectorImpl<MCInst> &Instructions) {
477 switch (Inst.getOpcode()) {
478 case Mips::LoadImm32Reg:
479 return expandLoadImm(Inst, IDLoc, Instructions);
480 case Mips::LoadAddr32Imm:
481 return expandLoadAddressImm(Inst, IDLoc, Instructions);
482 case Mips::LoadAddr32Reg:
483 return expandLoadAddressReg(Inst, IDLoc, Instructions);
487 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
488 SmallVectorImpl<MCInst> &Instructions) {
490 const MCOperand &ImmOp = Inst.getOperand(1);
491 assert(ImmOp.isImm() && "expected immediate operand kind");
492 const MCOperand &RegOp = Inst.getOperand(0);
493 assert(RegOp.isReg() && "expected register operand kind");
495 int ImmValue = ImmOp.getImm();
496 tmpInst.setLoc(IDLoc);
497 if (0 <= ImmValue && ImmValue <= 65535) {
498 // For 0 <= j <= 65535.
499 // li d,j => ori d,$zero,j
500 tmpInst.setOpcode(Mips::ORi);
501 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
502 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
503 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
504 Instructions.push_back(tmpInst);
505 } else if (ImmValue < 0 && ImmValue >= -32768) {
506 // For -32768 <= j < 0.
507 // li d,j => addiu d,$zero,j
508 tmpInst.setOpcode(Mips::ADDiu);
509 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
510 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
511 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
512 Instructions.push_back(tmpInst);
514 // For any other value of j that is representable as a 32-bit integer.
515 // li d,j => lui d,hi16(j)
517 tmpInst.setOpcode(Mips::LUi);
518 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
519 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
520 Instructions.push_back(tmpInst);
522 tmpInst.setOpcode(Mips::ORi);
523 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
524 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
525 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
526 tmpInst.setLoc(IDLoc);
527 Instructions.push_back(tmpInst);
531 void MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
532 SmallVectorImpl<MCInst> &Instructions) {
534 const MCOperand &ImmOp = Inst.getOperand(2);
535 assert(ImmOp.isImm() && "expected immediate operand kind");
536 const MCOperand &SrcRegOp = Inst.getOperand(1);
537 assert(SrcRegOp.isReg() && "expected register operand kind");
538 const MCOperand &DstRegOp = Inst.getOperand(0);
539 assert(DstRegOp.isReg() && "expected register operand kind");
540 int ImmValue = ImmOp.getImm();
541 if (-32768 <= ImmValue && ImmValue <= 65535) {
542 // For -32768 <= j <= 65535.
543 // la d,j(s) => addiu d,s,j
544 tmpInst.setOpcode(Mips::ADDiu);
545 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
546 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
547 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
548 Instructions.push_back(tmpInst);
550 // For any other value of j that is representable as a 32-bit integer.
551 // la d,j(s) => lui d,hi16(j)
554 tmpInst.setOpcode(Mips::LUi);
555 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
556 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
557 Instructions.push_back(tmpInst);
559 tmpInst.setOpcode(Mips::ORi);
560 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
561 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
562 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
563 Instructions.push_back(tmpInst);
565 tmpInst.setOpcode(Mips::ADDu);
566 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
567 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
568 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
569 Instructions.push_back(tmpInst);
573 void MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
574 SmallVectorImpl<MCInst> &Instructions) {
576 const MCOperand &ImmOp = Inst.getOperand(1);
577 assert(ImmOp.isImm() && "expected immediate operand kind");
578 const MCOperand &RegOp = Inst.getOperand(0);
579 assert(RegOp.isReg() && "expected register operand kind");
580 int ImmValue = ImmOp.getImm();
581 if (-32768 <= ImmValue && ImmValue <= 65535) {
582 // For -32768 <= j <= 65535.
583 // la d,j => addiu d,$zero,j
584 tmpInst.setOpcode(Mips::ADDiu);
585 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
586 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
587 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
588 Instructions.push_back(tmpInst);
590 // For any other value of j that is representable as a 32-bit integer.
591 // la d,j => lui d,hi16(j)
593 tmpInst.setOpcode(Mips::LUi);
594 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
595 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
596 Instructions.push_back(tmpInst);
598 tmpInst.setOpcode(Mips::ORi);
599 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
600 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
601 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
602 Instructions.push_back(tmpInst);
606 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
607 SmallVectorImpl<MCInst> &Instructions, bool isLoad, bool isImmOpnd) {
608 const MCSymbolRefExpr *SR;
610 unsigned ImmOffset, HiOffset, LoOffset;
611 const MCExpr *ExprOffset;
613 unsigned AtRegNum = getReg((isMips64()) ? Mips::CPU64RegsRegClassID
614 : Mips::CPURegsRegClassID, getATReg());
615 // 1st operand is either the source or destination register.
616 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
617 unsigned RegOpNum = Inst.getOperand(0).getReg();
618 // 2nd operand is the base register.
619 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
620 unsigned BaseRegNum = Inst.getOperand(1).getReg();
621 // 3rd operand is either an immediate or expression.
623 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
624 ImmOffset = Inst.getOperand(2).getImm();
625 LoOffset = ImmOffset & 0x0000ffff;
626 HiOffset = (ImmOffset & 0xffff0000) >> 16;
627 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
628 if (LoOffset & 0x8000)
631 ExprOffset = Inst.getOperand(2).getExpr();
632 // All instructions will have the same location.
633 TempInst.setLoc(IDLoc);
634 // 1st instruction in expansion is LUi. For load instruction we can use
635 // the dst register as a temporary if base and dst are different,
636 // but for stores we must use $at.
637 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
638 TempInst.setOpcode(Mips::LUi);
639 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
641 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
643 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
644 SR = static_cast<const MCSymbolRefExpr*>(ExprOffset);
645 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
646 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
648 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
650 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
651 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
654 // Add the instruction to the list.
655 Instructions.push_back(TempInst);
656 // Prepare TempInst for next instruction.
658 // Add temp register to base.
659 TempInst.setOpcode(Mips::ADDu);
660 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
661 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
662 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
663 Instructions.push_back(TempInst);
665 // And finaly, create original instruction with low part
666 // of offset and new base.
667 TempInst.setOpcode(Inst.getOpcode());
668 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
669 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
671 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
673 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
674 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
675 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
677 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
679 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
680 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
683 Instructions.push_back(TempInst);
688 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
689 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
690 MCStreamer &Out, unsigned &ErrorInfo,
691 bool MatchingInlineAsm) {
693 SmallVector<MCInst, 8> Instructions;
694 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
697 switch (MatchResult) {
700 case Match_Success: {
701 if (processInstruction(Inst, IDLoc, Instructions))
703 for (unsigned i = 0; i < Instructions.size(); i++)
704 Out.EmitInstruction(Instructions[i]);
707 case Match_MissingFeature:
708 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
710 case Match_InvalidOperand: {
711 SMLoc ErrorLoc = IDLoc;
712 if (ErrorInfo != ~0U) {
713 if (ErrorInfo >= Operands.size())
714 return Error(IDLoc, "too few operands for instruction");
716 ErrorLoc = ((MipsOperand*) Operands[ErrorInfo])->getStartLoc();
717 if (ErrorLoc == SMLoc())
721 return Error(ErrorLoc, "invalid operand for instruction");
723 case Match_MnemonicFail:
724 return Error(IDLoc, "invalid instruction");
729 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
735 CC = StringSwitch<unsigned>(Name)
769 // Although SGI documentation just cuts out t0-t3 for n32/n64,
770 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
771 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
772 if (isMips64() && 8 <= CC && CC <= 11)
775 if (CC == -1 && isMips64())
776 CC = StringSwitch<unsigned>(Name)
789 int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
791 if (Name.equals("fcc0"))
795 CC = matchCPURegisterName(Name);
797 return matchRegisterByNumber(CC, is64BitReg ? Mips::CPU64RegsRegClassID
798 : Mips::CPURegsRegClassID);
800 if (Name[0] == 'f') {
801 StringRef NumString = Name.substr(1);
803 if (NumString.getAsInteger(10, IntVal))
804 return -1; // This is not an integer.
808 FpFormatTy Format = getFpFormat();
810 if (Format == FP_FORMAT_S || Format == FP_FORMAT_W)
811 return getReg(Mips::FGR32RegClassID, IntVal);
812 if (Format == FP_FORMAT_D) {
814 return getReg(Mips::FGR64RegClassID, IntVal);
816 // Only even numbers available as register pairs.
817 if ((IntVal > 31) || (IntVal % 2 != 0))
819 return getReg(Mips::AFGR64RegClassID, IntVal / 2);
826 void MipsAsmParser::setDefaultFpFormat() {
828 if (isMips64() || isFP64())
829 FpFormat = FP_FORMAT_D;
831 FpFormat = FP_FORMAT_S;
834 bool MipsAsmParser::requestsDoubleOperand(StringRef Mnemonic){
836 bool IsDouble = StringSwitch<bool>(Mnemonic.lower())
846 void MipsAsmParser::setFpFormat(StringRef Format) {
848 FpFormat = StringSwitch<FpFormatTy>(Format.lower())
849 .Case(".s", FP_FORMAT_S)
850 .Case(".d", FP_FORMAT_D)
851 .Case(".l", FP_FORMAT_L)
852 .Case(".w", FP_FORMAT_W)
853 .Default(FP_FORMAT_NONE);
856 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
864 int MipsAsmParser::getATReg() {
865 return Options.getATRegNum();
868 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
869 return *(getContext().getRegisterInfo().getRegClass(RC).begin() + RegNo);
872 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
877 return getReg(RegClass, RegNum);
880 int MipsAsmParser::tryParseRegister(bool is64BitReg) {
881 const AsmToken &Tok = Parser.getTok();
884 if (Tok.is(AsmToken::Identifier)) {
885 std::string lowerCase = Tok.getString().lower();
886 RegNum = matchRegisterName(lowerCase, is64BitReg);
887 } else if (Tok.is(AsmToken::Integer))
888 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
889 is64BitReg ? Mips::CPU64RegsRegClassID : Mips::CPURegsRegClassID);
893 bool MipsAsmParser::tryParseRegisterOperand(
894 SmallVectorImpl<MCParsedAsmOperand*> &Operands, bool is64BitReg) {
896 SMLoc S = Parser.getTok().getLoc();
899 RegNo = tryParseRegister(is64BitReg);
903 Operands.push_back(MipsOperand::CreateReg(RegNo, S,
904 Parser.getTok().getLoc()));
905 Parser.Lex(); // Eat register token.
909 bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
910 StringRef Mnemonic) {
911 // Check if the current operand has a custom associated parser, if so, try to
912 // custom parse the operand, or fallback to the general approach.
913 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
914 if (ResTy == MatchOperand_Success)
916 // If there wasn't a custom match, try the generic matcher below. Otherwise,
917 // there was a match, but an error occurred, in which case, just return that
918 // the operand parsing failed.
919 if (ResTy == MatchOperand_ParseFail)
922 switch (getLexer().getKind()) {
924 Error(Parser.getTok().getLoc(), "unexpected token in operand");
926 case AsmToken::Dollar: {
927 // Parse the register.
928 SMLoc S = Parser.getTok().getLoc();
929 Parser.Lex(); // Eat dollar token.
930 // Parse the register operand.
931 if (!tryParseRegisterOperand(Operands, isMips64())) {
932 if (getLexer().is(AsmToken::LParen)) {
933 // Check if it is indexed addressing operand.
934 Operands.push_back(MipsOperand::CreateToken("(", S));
935 Parser.Lex(); // Eat the parenthesis.
936 if (getLexer().isNot(AsmToken::Dollar))
939 Parser.Lex(); // Eat the dollar
940 if (tryParseRegisterOperand(Operands, isMips64()))
943 if (!getLexer().is(AsmToken::RParen))
946 S = Parser.getTok().getLoc();
947 Operands.push_back(MipsOperand::CreateToken(")", S));
952 // Maybe it is a symbol reference.
953 StringRef Identifier;
954 if (Parser.parseIdentifier(Identifier))
957 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
959 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
961 // Otherwise create a symbol reference.
962 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
965 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
968 case AsmToken::Identifier:
969 // Look for the existing symbol, we should check if
970 // we need to assigne the propper RegisterKind.
971 if (searchSymbolAlias(Operands, MipsOperand::Kind_None))
973 // Else drop to expression parsing.
974 case AsmToken::LParen:
975 case AsmToken::Minus:
977 case AsmToken::Integer:
978 case AsmToken::String: {
979 // Quoted label names.
981 SMLoc S = Parser.getTok().getLoc();
982 if (getParser().parseExpression(IdVal))
984 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
985 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
988 case AsmToken::Percent: {
989 // It is a symbol reference or constant expression.
991 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
992 if (parseRelocOperand(IdVal))
995 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
997 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
999 } // case AsmToken::Percent
1000 } // switch(getLexer().getKind())
1004 const MCExpr* MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1005 StringRef RelocStr) {
1007 // Check the type of the expression.
1008 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1009 // It's a constant, evaluate lo or hi value.
1010 if (RelocStr == "lo") {
1011 short Val = MCE->getValue();
1012 Res = MCConstantExpr::Create(Val, getContext());
1013 } else if (RelocStr == "hi") {
1014 int Val = MCE->getValue();
1015 int LoSign = Val & 0x8000;
1016 Val = (Val & 0xffff0000) >> 16;
1017 // Lower part is treated as a signed int, so if it is negative
1018 // we must add 1 to the hi part to compensate.
1021 Res = MCConstantExpr::Create(Val, getContext());
1023 llvm_unreachable("Invalid RelocStr value");
1028 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1029 // It's a symbol, create a symbolic expression from the symbol.
1030 StringRef Symbol = MSRE->getSymbol().getName();
1031 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1032 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1036 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1037 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1038 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1039 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1043 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1044 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1045 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1048 // Just return the original expression.
1052 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1054 switch (Expr->getKind()) {
1055 case MCExpr::Constant:
1057 case MCExpr::SymbolRef:
1058 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1059 case MCExpr::Binary:
1060 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1061 if (!isEvaluated(BE->getLHS()))
1063 return isEvaluated(BE->getRHS());
1066 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1073 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1074 Parser.Lex(); // Eat the % token.
1075 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1076 if (Tok.isNot(AsmToken::Identifier))
1079 std::string Str = Tok.getIdentifier().str();
1081 Parser.Lex(); // Eat the identifier.
1082 // Now make an expression from the rest of the operand.
1083 const MCExpr *IdVal;
1086 if (getLexer().getKind() == AsmToken::LParen) {
1088 Parser.Lex(); // Eat the '(' token.
1089 if (getLexer().getKind() == AsmToken::Percent) {
1090 Parser.Lex(); // Eat the % token.
1091 const AsmToken &nextTok = Parser.getTok();
1092 if (nextTok.isNot(AsmToken::Identifier))
1095 Str += nextTok.getIdentifier();
1096 Parser.Lex(); // Eat the identifier.
1097 if (getLexer().getKind() != AsmToken::LParen)
1102 if (getParser().parseParenExpression(IdVal, EndLoc))
1105 while (getLexer().getKind() == AsmToken::RParen)
1106 Parser.Lex(); // Eat the ')' token.
1109 return true; // Parenthesis must follow the relocation operand.
1111 Res = evaluateRelocExpr(IdVal, Str);
1115 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1117 StartLoc = Parser.getTok().getLoc();
1118 RegNo = tryParseRegister(isMips64());
1119 EndLoc = Parser.getTok().getLoc();
1120 return (RegNo == (unsigned) -1);
1123 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1127 while (getLexer().getKind() == AsmToken::LParen)
1130 switch (getLexer().getKind()) {
1133 case AsmToken::Identifier:
1134 case AsmToken::LParen:
1135 case AsmToken::Integer:
1136 case AsmToken::Minus:
1137 case AsmToken::Plus:
1139 Result = getParser().parseParenExpression(Res, S);
1141 Result = (getParser().parseExpression(Res));
1142 while (getLexer().getKind() == AsmToken::RParen)
1145 case AsmToken::Percent:
1146 Result = parseRelocOperand(Res);
1151 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1152 SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
1154 const MCExpr *IdVal = 0;
1156 bool isParenExpr = false;
1157 // First operand is the offset.
1158 S = Parser.getTok().getLoc();
1160 if (getLexer().getKind() == AsmToken::LParen) {
1165 if (getLexer().getKind() != AsmToken::Dollar) {
1166 if (parseMemOffset(IdVal, isParenExpr))
1167 return MatchOperand_ParseFail;
1169 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1170 if (Tok.isNot(AsmToken::LParen)) {
1171 MipsOperand *Mnemonic = static_cast<MipsOperand*>(Operands[0]);
1172 if (Mnemonic->getToken() == "la") {
1173 SMLoc E = SMLoc::getFromPointer(
1174 Parser.getTok().getLoc().getPointer() - 1);
1175 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1176 return MatchOperand_Success;
1178 if (Tok.is(AsmToken::EndOfStatement)) {
1179 SMLoc E = SMLoc::getFromPointer(
1180 Parser.getTok().getLoc().getPointer() - 1);
1182 // Zero register assumed, add a memory operand with ZERO as its base.
1183 Operands.push_back(MipsOperand::CreateMem(isMips64() ? Mips::ZERO_64
1186 return MatchOperand_Success;
1188 Error(Parser.getTok().getLoc(), "'(' expected");
1189 return MatchOperand_ParseFail;
1192 Parser.Lex(); // Eat the '(' token.
1195 const AsmToken &Tok1 = Parser.getTok(); // Get next token
1196 if (Tok1.is(AsmToken::Dollar)) {
1197 Parser.Lex(); // Eat the '$' token.
1198 if (tryParseRegisterOperand(Operands, isMips64())) {
1199 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1200 return MatchOperand_ParseFail;
1204 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1205 return MatchOperand_ParseFail;
1208 const AsmToken &Tok2 = Parser.getTok(); // Get next token.
1209 if (Tok2.isNot(AsmToken::RParen)) {
1210 Error(Parser.getTok().getLoc(), "')' expected");
1211 return MatchOperand_ParseFail;
1214 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1216 Parser.Lex(); // Eat the ')' token.
1219 IdVal = MCConstantExpr::Create(0, getContext());
1221 // Replace the register operand with the memory operand.
1222 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1223 int RegNo = op->getReg();
1224 // Remove the register from the operands.
1225 Operands.pop_back();
1226 // Add the memory operand.
1227 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1229 if (IdVal->EvaluateAsAbsolute(Imm))
1230 IdVal = MCConstantExpr::Create(Imm, getContext());
1231 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1232 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1236 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
1238 return MatchOperand_Success;
1241 MipsAsmParser::OperandMatchResultTy
1242 MipsAsmParser::parseCPU64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1245 return MatchOperand_NoMatch;
1246 if (getLexer().getKind() == AsmToken::Identifier) {
1247 if (searchSymbolAlias(Operands, MipsOperand::Kind_CPU64Regs))
1248 return MatchOperand_Success;
1249 return MatchOperand_NoMatch;
1251 // If the first token is not '$', we have an error.
1252 if (Parser.getTok().isNot(AsmToken::Dollar))
1253 return MatchOperand_NoMatch;
1255 Parser.Lex(); // Eat $
1256 if (!tryParseRegisterOperand(Operands, true)) {
1257 // Set the proper register kind.
1258 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1259 op->setRegKind(MipsOperand::Kind_CPU64Regs);
1260 return MatchOperand_Success;
1262 return MatchOperand_NoMatch;
1265 bool MipsAsmParser::searchSymbolAlias(
1266 SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegisterKind) {
1268 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1270 SMLoc S = Parser.getTok().getLoc();
1272 if (Sym->isVariable())
1273 Expr = Sym->getVariableValue();
1276 if (Expr->getKind() == MCExpr::SymbolRef) {
1277 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
1278 const StringRef DefSymbol = Ref->getSymbol().getName();
1279 if (DefSymbol.startswith("$")) {
1280 // Lookup for the register with the corresponding name.
1281 int RegNum = matchRegisterName(DefSymbol.substr(1), isMips64());
1284 MipsOperand *op = MipsOperand::CreateReg(RegNum, S,
1285 Parser.getTok().getLoc());
1286 op->setRegKind((MipsOperand::RegisterKind) RegisterKind);
1287 Operands.push_back(op);
1291 } else if (Expr->getKind() == MCExpr::Constant) {
1293 const MCConstantExpr *Const = static_cast<const MCConstantExpr*>(Expr);
1294 MipsOperand *op = MipsOperand::CreateImm(Const, S,
1295 Parser.getTok().getLoc());
1296 Operands.push_back(op);
1303 MipsAsmParser::OperandMatchResultTy
1304 MipsAsmParser::parseCPURegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1306 if (getLexer().getKind() == AsmToken::Identifier) {
1307 if (searchSymbolAlias(Operands, MipsOperand::Kind_CPURegs))
1308 return MatchOperand_Success;
1309 return MatchOperand_NoMatch;
1311 // If the first token is not '$' we have an error.
1312 if (Parser.getTok().isNot(AsmToken::Dollar))
1313 return MatchOperand_NoMatch;
1315 Parser.Lex(); // Eat $
1316 if (!tryParseRegisterOperand(Operands, false)) {
1317 // Set the proper register kind.
1318 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1319 op->setRegKind(MipsOperand::Kind_CPURegs);
1320 return MatchOperand_Success;
1322 return MatchOperand_NoMatch;
1325 MipsAsmParser::OperandMatchResultTy
1326 MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1329 return MatchOperand_NoMatch;
1331 // If the first token is not '$' we have error.
1332 if (Parser.getTok().isNot(AsmToken::Dollar))
1333 return MatchOperand_NoMatch;
1334 SMLoc S = Parser.getTok().getLoc();
1335 Parser.Lex(); // Eat the '$'.
1337 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1338 if (Tok.isNot(AsmToken::Integer))
1339 return MatchOperand_NoMatch;
1341 unsigned RegNum = Tok.getIntVal();
1342 // At the moment only hwreg29 is supported.
1344 return MatchOperand_ParseFail;
1346 MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29, S,
1347 Parser.getTok().getLoc());
1348 op->setRegKind(MipsOperand::Kind_HWRegs);
1349 Operands.push_back(op);
1351 Parser.Lex(); // Eat the register number.
1352 return MatchOperand_Success;
1355 MipsAsmParser::OperandMatchResultTy
1356 MipsAsmParser::parseHW64Regs(
1357 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1360 return MatchOperand_NoMatch;
1361 // If the first token is not '$' we have an error.
1362 if (Parser.getTok().isNot(AsmToken::Dollar))
1363 return MatchOperand_NoMatch;
1364 SMLoc S = Parser.getTok().getLoc();
1365 Parser.Lex(); // Eat $
1367 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1368 if (Tok.isNot(AsmToken::Integer))
1369 return MatchOperand_NoMatch;
1371 unsigned RegNum = Tok.getIntVal();
1372 // At the moment only hwreg29 is supported.
1374 return MatchOperand_ParseFail;
1376 MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S,
1377 Parser.getTok().getLoc());
1378 op->setRegKind(MipsOperand::Kind_HW64Regs);
1379 Operands.push_back(op);
1381 Parser.Lex(); // Eat the register number.
1382 return MatchOperand_Success;
1385 MipsAsmParser::OperandMatchResultTy
1386 MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1388 // If the first token is not '$' we have an error.
1389 if (Parser.getTok().isNot(AsmToken::Dollar))
1390 return MatchOperand_NoMatch;
1391 SMLoc S = Parser.getTok().getLoc();
1392 Parser.Lex(); // Eat the '$'
1394 const AsmToken &Tok = Parser.getTok(); // Get next token.
1395 if (Tok.is(AsmToken::Integer)) {
1396 RegNum = Tok.getIntVal();
1397 // At the moment only fcc0 is supported.
1399 return MatchOperand_ParseFail;
1400 } else if (Tok.is(AsmToken::Identifier)) {
1401 // At the moment only fcc0 is supported.
1402 if (Tok.getIdentifier() != "fcc0")
1403 return MatchOperand_ParseFail;
1405 return MatchOperand_NoMatch;
1407 MipsOperand *op = MipsOperand::CreateReg(Mips::FCC0, S,
1408 Parser.getTok().getLoc());
1409 op->setRegKind(MipsOperand::Kind_CCRRegs);
1410 Operands.push_back(op);
1412 Parser.Lex(); // Eat the register number.
1413 return MatchOperand_Success;
1416 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
1418 MCSymbolRefExpr::VariantKind VK
1419 = StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
1420 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
1421 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
1422 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
1423 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
1424 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
1425 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
1426 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
1427 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
1428 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
1429 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
1430 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
1431 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
1432 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
1433 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
1434 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
1435 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
1436 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
1437 .Default(MCSymbolRefExpr::VK_None);
1442 static int ConvertCcString(StringRef CondString) {
1443 int CC = StringSwitch<unsigned>(CondString)
1465 bool MipsAsmParser::
1466 parseMathOperation(StringRef Name, SMLoc NameLoc,
1467 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1468 // Split the format.
1469 size_t Start = Name.find('.'), Next = Name.rfind('.');
1470 StringRef Format1 = Name.slice(Start, Next);
1471 // Add the first format to the operands.
1472 Operands.push_back(MipsOperand::CreateToken(Format1, NameLoc));
1473 // Now for the second format.
1474 StringRef Format2 = Name.slice(Next, StringRef::npos);
1475 Operands.push_back(MipsOperand::CreateToken(Format2, NameLoc));
1477 // Set the format for the first register.
1478 setFpFormat(Format1);
1480 // Read the remaining operands.
1481 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1482 // Read the first operand.
1483 if (ParseOperand(Operands, Name)) {
1484 SMLoc Loc = getLexer().getLoc();
1485 Parser.eatToEndOfStatement();
1486 return Error(Loc, "unexpected token in argument list");
1489 if (getLexer().isNot(AsmToken::Comma)) {
1490 SMLoc Loc = getLexer().getLoc();
1491 Parser.eatToEndOfStatement();
1492 return Error(Loc, "unexpected token in argument list");
1494 Parser.Lex(); // Eat the comma.
1496 // Set the format for the first register
1497 setFpFormat(Format2);
1499 // Parse and remember the operand.
1500 if (ParseOperand(Operands, Name)) {
1501 SMLoc Loc = getLexer().getLoc();
1502 Parser.eatToEndOfStatement();
1503 return Error(Loc, "unexpected token in argument list");
1507 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1508 SMLoc Loc = getLexer().getLoc();
1509 Parser.eatToEndOfStatement();
1510 return Error(Loc, "unexpected token in argument list");
1513 Parser.Lex(); // Consume the EndOfStatement.
1517 bool MipsAsmParser::
1518 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1519 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1521 // Floating point instructions: Should the register be treated as a double?
1522 if (requestsDoubleOperand(Name)) {
1523 setFpFormat(FP_FORMAT_D);
1524 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
1527 setDefaultFpFormat();
1528 // Create the leading tokens for the mnemonic, split by '.' characters.
1529 size_t Start = 0, Next = Name.find('.');
1530 Mnemonic = Name.slice(Start, Next);
1532 Operands.push_back(MipsOperand::CreateToken(Mnemonic, NameLoc));
1534 if (Next != StringRef::npos) {
1535 // There is a format token in mnemonic.
1536 size_t Dot = Name.find('.', Next + 1);
1537 StringRef Format = Name.slice(Next, Dot);
1538 if (Dot == StringRef::npos) // Only one '.' in a string, it's a format.
1539 Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
1541 if (Name.startswith("c.")) {
1542 // Floating point compare, add '.' and immediate represent for cc.
1543 Operands.push_back(MipsOperand::CreateToken(".", NameLoc));
1544 int Cc = ConvertCcString(Format);
1546 return Error(NameLoc, "Invalid conditional code");
1548 SMLoc E = SMLoc::getFromPointer(
1549 Parser.getTok().getLoc().getPointer() - 1);
1551 MipsOperand::CreateImm(MCConstantExpr::Create(Cc, getContext()),
1554 // trunc, ceil, floor ...
1555 return parseMathOperation(Name, NameLoc, Operands);
1558 // The rest is a format.
1559 Format = Name.slice(Dot, StringRef::npos);
1560 Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
1563 setFpFormat(Format);
1567 // Read the remaining operands.
1568 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1569 // Read the first operand.
1570 if (ParseOperand(Operands, Mnemonic)) {
1571 SMLoc Loc = getLexer().getLoc();
1572 Parser.eatToEndOfStatement();
1573 return Error(Loc, "unexpected token in argument list");
1576 while (getLexer().is(AsmToken::Comma)) {
1577 Parser.Lex(); // Eat the comma.
1579 // Parse and remember the operand.
1580 if (ParseOperand(Operands, Name)) {
1581 SMLoc Loc = getLexer().getLoc();
1582 Parser.eatToEndOfStatement();
1583 return Error(Loc, "unexpected token in argument list");
1588 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1589 SMLoc Loc = getLexer().getLoc();
1590 Parser.eatToEndOfStatement();
1591 return Error(Loc, "unexpected token in argument list");
1594 Parser.Lex(); // Consume the EndOfStatement.
1598 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
1599 SMLoc Loc = getLexer().getLoc();
1600 Parser.eatToEndOfStatement();
1601 return Error(Loc, ErrorMsg);
1604 bool MipsAsmParser::parseSetNoAtDirective() {
1605 // Line should look like: ".set noat".
1607 Options.setATReg(0);
1610 // If this is not the end of the statement, report an error.
1611 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1612 reportParseError("unexpected token in statement");
1615 Parser.Lex(); // Consume the EndOfStatement.
1619 bool MipsAsmParser::parseSetAtDirective() {
1620 // Line can be .set at - defaults to $1
1624 if (getLexer().is(AsmToken::EndOfStatement)) {
1625 Options.setATReg(1);
1626 Parser.Lex(); // Consume the EndOfStatement.
1628 } else if (getLexer().is(AsmToken::Equal)) {
1629 getParser().Lex(); // Eat the '='.
1630 if (getLexer().isNot(AsmToken::Dollar)) {
1631 reportParseError("unexpected token in statement");
1634 Parser.Lex(); // Eat the '$'.
1635 const AsmToken &Reg = Parser.getTok();
1636 if (Reg.is(AsmToken::Identifier)) {
1637 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
1638 } else if (Reg.is(AsmToken::Integer)) {
1639 AtRegNo = Reg.getIntVal();
1641 reportParseError("unexpected token in statement");
1645 if (AtRegNo < 1 || AtRegNo > 31) {
1646 reportParseError("unexpected token in statement");
1650 if (!Options.setATReg(AtRegNo)) {
1651 reportParseError("unexpected token in statement");
1654 getParser().Lex(); // Eat the register.
1656 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1657 reportParseError("unexpected token in statement");
1660 Parser.Lex(); // Consume the EndOfStatement.
1663 reportParseError("unexpected token in statement");
1668 bool MipsAsmParser::parseSetReorderDirective() {
1670 // If this is not the end of the statement, report an error.
1671 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1672 reportParseError("unexpected token in statement");
1675 Options.setReorder();
1676 Parser.Lex(); // Consume the EndOfStatement.
1680 bool MipsAsmParser::parseSetNoReorderDirective() {
1682 // If this is not the end of the statement, report an error.
1683 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1684 reportParseError("unexpected token in statement");
1687 Options.setNoreorder();
1688 Parser.Lex(); // Consume the EndOfStatement.
1692 bool MipsAsmParser::parseSetMacroDirective() {
1694 // If this is not the end of the statement, report an error.
1695 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1696 reportParseError("unexpected token in statement");
1700 Parser.Lex(); // Consume the EndOfStatement.
1704 bool MipsAsmParser::parseSetNoMacroDirective() {
1706 // If this is not the end of the statement, report an error.
1707 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1708 reportParseError("`noreorder' must be set before `nomacro'");
1711 if (Options.isReorder()) {
1712 reportParseError("`noreorder' must be set before `nomacro'");
1715 Options.setNomacro();
1716 Parser.Lex(); // Consume the EndOfStatement.
1720 bool MipsAsmParser::parseSetAssignment() {
1722 const MCExpr *Value;
1724 if (Parser.parseIdentifier(Name))
1725 reportParseError("expected identifier after .set");
1727 if (getLexer().isNot(AsmToken::Comma))
1728 return reportParseError("unexpected token in .set directive");
1731 if (Parser.parseExpression(Value))
1732 reportParseError("expected valid expression after comma");
1734 // Check if the Name already exists as a symbol.
1735 MCSymbol *Sym = getContext().LookupSymbol(Name);
1737 return reportParseError("symbol already defined");
1738 Sym = getContext().GetOrCreateSymbol(Name);
1739 Sym->setVariableValue(Value);
1744 bool MipsAsmParser::parseDirectiveSet() {
1746 // Get the next token.
1747 const AsmToken &Tok = Parser.getTok();
1749 if (Tok.getString() == "noat") {
1750 return parseSetNoAtDirective();
1751 } else if (Tok.getString() == "at") {
1752 return parseSetAtDirective();
1753 } else if (Tok.getString() == "reorder") {
1754 return parseSetReorderDirective();
1755 } else if (Tok.getString() == "noreorder") {
1756 return parseSetNoReorderDirective();
1757 } else if (Tok.getString() == "macro") {
1758 return parseSetMacroDirective();
1759 } else if (Tok.getString() == "nomacro") {
1760 return parseSetNoMacroDirective();
1761 } else if (Tok.getString() == "nomips16") {
1762 // Ignore this directive for now.
1763 Parser.eatToEndOfStatement();
1765 } else if (Tok.getString() == "nomicromips") {
1766 // Ignore this directive for now.
1767 Parser.eatToEndOfStatement();
1770 // It is just an identifier, look for an assignment.
1771 parseSetAssignment();
1778 /// parseDirectiveWord
1779 /// ::= .word [ expression (, expression)* ]
1780 bool MipsAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
1781 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1783 const MCExpr *Value;
1784 if (getParser().parseExpression(Value))
1787 getParser().getStreamer().EmitValue(Value, Size);
1789 if (getLexer().is(AsmToken::EndOfStatement))
1792 // FIXME: Improve diagnostic.
1793 if (getLexer().isNot(AsmToken::Comma))
1794 return Error(L, "unexpected token in directive");
1803 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
1805 StringRef IDVal = DirectiveID.getString();
1807 if (IDVal == ".ent") {
1808 // Ignore this directive for now.
1813 if (IDVal == ".end") {
1814 // Ignore this directive for now.
1819 if (IDVal == ".frame") {
1820 // Ignore this directive for now.
1821 Parser.eatToEndOfStatement();
1825 if (IDVal == ".set") {
1826 return parseDirectiveSet();
1829 if (IDVal == ".fmask") {
1830 // Ignore this directive for now.
1831 Parser.eatToEndOfStatement();
1835 if (IDVal == ".mask") {
1836 // Ignore this directive for now.
1837 Parser.eatToEndOfStatement();
1841 if (IDVal == ".gpword") {
1842 // Ignore this directive for now.
1843 Parser.eatToEndOfStatement();
1847 if (IDVal == ".word") {
1848 parseDirectiveWord(4, DirectiveID.getLoc());
1855 extern "C" void LLVMInitializeMipsAsmParser() {
1856 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
1857 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
1858 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
1859 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
1862 #define GET_REGISTER_MATCHER
1863 #define GET_MATCHER_IMPLEMENTATION
1864 #include "MipsGenAsmMatcher.inc"