1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCTargetDesc.h"
11 #include "MipsRegisterInfo.h"
12 #include "llvm/ADT/StringSwitch.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCParser/MCAsmLexer.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/MC/MCSymbol.h"
21 #include "llvm/MC/MCTargetAsmParser.h"
22 #include "llvm/Support/TargetRegistry.h"
27 class MipsAssemblerOptions {
29 MipsAssemblerOptions():
30 aTReg(1), reorder(true), macro(true) {
33 unsigned getATRegNum() {return aTReg;}
34 bool setATReg(unsigned Reg);
36 bool isReorder() {return reorder;}
37 void setReorder() {reorder = true;}
38 void setNoreorder() {reorder = false;}
40 bool isMacro() {return macro;}
41 void setMacro() {macro = true;}
42 void setNomacro() {macro = false;}
52 class MipsAsmParser : public MCTargetAsmParser {
64 MipsAssemblerOptions Options;
67 #define GET_ASSEMBLER_HEADER
68 #include "MipsGenAsmMatcher.inc"
70 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
71 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
72 MCStreamer &Out, unsigned &ErrorInfo,
73 bool MatchingInlineAsm);
75 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
77 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
79 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
81 bool parseMathOperation(StringRef Name, SMLoc NameLoc,
82 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
84 bool ParseDirective(AsmToken DirectiveID);
86 MipsAsmParser::OperandMatchResultTy
87 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
89 MipsAsmParser::OperandMatchResultTy
90 parseCPURegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
92 MipsAsmParser::OperandMatchResultTy
93 parseCPU64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
95 MipsAsmParser::OperandMatchResultTy
96 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
98 MipsAsmParser::OperandMatchResultTy
99 parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
101 MipsAsmParser::OperandMatchResultTy
102 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
104 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &,
107 int tryParseRegister(bool is64BitReg);
109 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
112 bool needsExpansion(MCInst &Inst);
114 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
115 SmallVectorImpl<MCInst> &Instructions);
116 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
117 SmallVectorImpl<MCInst> &Instructions);
118 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
119 SmallVectorImpl<MCInst> &Instructions);
120 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
121 SmallVectorImpl<MCInst> &Instructions);
122 bool reportParseError(StringRef ErrorMsg);
124 bool parseMemOffset(const MCExpr *&Res);
125 bool parseRelocOperand(const MCExpr *&Res);
127 bool parseDirectiveSet();
129 bool parseSetAtDirective();
130 bool parseSetNoAtDirective();
131 bool parseSetMacroDirective();
132 bool parseSetNoMacroDirective();
133 bool parseSetReorderDirective();
134 bool parseSetNoReorderDirective();
136 bool parseDirectiveWord(unsigned Size, SMLoc L);
138 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
140 bool isMips64() const {
141 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
144 bool isFP64() const {
145 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
148 int matchRegisterName(StringRef Symbol, bool is64BitReg);
150 int matchCPURegisterName(StringRef Symbol);
152 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
154 void setFpFormat(FpFormatTy Format) {
158 void setDefaultFpFormat();
160 void setFpFormat(StringRef Format);
162 FpFormatTy getFpFormat() {return FpFormat;}
164 bool requestsDoubleOperand(StringRef Mnemonic);
166 unsigned getReg(int RC,int RegNo);
170 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
171 : MCTargetAsmParser(), STI(sti), Parser(parser) {
172 // Initialize the set of available features.
173 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
176 MCAsmParser &getParser() const { return Parser; }
177 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
184 /// MipsOperand - Instances of this class represent a parsed Mips machine
186 class MipsOperand : public MCParsedAsmOperand {
212 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
235 SMLoc StartLoc, EndLoc;
238 void addRegOperands(MCInst &Inst, unsigned N) const {
239 assert(N == 1 && "Invalid number of operands!");
240 Inst.addOperand(MCOperand::CreateReg(getReg()));
243 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
244 // Add as immediate when possible. Null MCExpr = 0.
246 Inst.addOperand(MCOperand::CreateImm(0));
247 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
248 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
250 Inst.addOperand(MCOperand::CreateExpr(Expr));
253 void addImmOperands(MCInst &Inst, unsigned N) const {
254 assert(N == 1 && "Invalid number of operands!");
255 const MCExpr *Expr = getImm();
259 void addMemOperands(MCInst &Inst, unsigned N) const {
260 assert(N == 2 && "Invalid number of operands!");
262 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
264 const MCExpr *Expr = getMemOff();
268 bool isReg() const { return Kind == k_Register; }
269 bool isImm() const { return Kind == k_Immediate; }
270 bool isToken() const { return Kind == k_Token; }
271 bool isMem() const { return Kind == k_Memory; }
273 StringRef getToken() const {
274 assert(Kind == k_Token && "Invalid access!");
275 return StringRef(Tok.Data, Tok.Length);
278 unsigned getReg() const {
279 assert((Kind == k_Register) && "Invalid access!");
283 void setRegKind(RegisterKind RegKind) {
284 assert((Kind == k_Register) && "Invalid access!");
288 const MCExpr *getImm() const {
289 assert((Kind == k_Immediate) && "Invalid access!");
293 unsigned getMemBase() const {
294 assert((Kind == k_Memory) && "Invalid access!");
298 const MCExpr *getMemOff() const {
299 assert((Kind == k_Memory) && "Invalid access!");
303 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
304 MipsOperand *Op = new MipsOperand(k_Token);
305 Op->Tok.Data = Str.data();
306 Op->Tok.Length = Str.size();
312 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
313 MipsOperand *Op = new MipsOperand(k_Register);
314 Op->Reg.RegNum = RegNum;
320 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
321 MipsOperand *Op = new MipsOperand(k_Immediate);
328 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off,
330 MipsOperand *Op = new MipsOperand(k_Memory);
338 bool isCPURegsAsm() const {
339 return Kind == k_Register && Reg.Kind == Kind_CPURegs;
341 void addCPURegsAsmOperands(MCInst &Inst, unsigned N) const {
342 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
345 bool isCPU64RegsAsm() const {
346 return Kind == k_Register && Reg.Kind == Kind_CPU64Regs;
348 void addCPU64RegsAsmOperands(MCInst &Inst, unsigned N) const {
349 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
352 bool isHWRegsAsm() const {
353 assert((Kind == k_Register) && "Invalid access!");
354 return Reg.Kind == Kind_HWRegs;
356 void addHWRegsAsmOperands(MCInst &Inst, unsigned N) const {
357 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
360 bool isHW64RegsAsm() const {
361 assert((Kind == k_Register) && "Invalid access!");
362 return Reg.Kind == Kind_HW64Regs;
364 void addHW64RegsAsmOperands(MCInst &Inst, unsigned N) const {
365 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
368 void addCCRAsmOperands(MCInst &Inst, unsigned N) const {
369 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
372 bool isCCRAsm() const {
373 assert((Kind == k_Register) && "Invalid access!");
374 return Reg.Kind == Kind_CCRRegs;
377 /// getStartLoc - Get the location of the first token of this operand.
378 SMLoc getStartLoc() const { return StartLoc; }
379 /// getEndLoc - Get the location of the last token of this operand.
380 SMLoc getEndLoc() const { return EndLoc; }
382 virtual void print(raw_ostream &OS) const {
383 llvm_unreachable("unimplemented!");
388 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
390 switch(Inst.getOpcode()) {
391 case Mips::LoadImm32Reg:
392 case Mips::LoadAddr32Imm:
393 case Mips::LoadAddr32Reg:
400 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
401 SmallVectorImpl<MCInst> &Instructions){
402 switch(Inst.getOpcode()) {
403 case Mips::LoadImm32Reg:
404 return expandLoadImm(Inst, IDLoc, Instructions);
405 case Mips::LoadAddr32Imm:
406 return expandLoadAddressImm(Inst,IDLoc,Instructions);
407 case Mips::LoadAddr32Reg:
408 return expandLoadAddressReg(Inst,IDLoc,Instructions);
412 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
413 SmallVectorImpl<MCInst> &Instructions){
415 const MCOperand &ImmOp = Inst.getOperand(1);
416 assert(ImmOp.isImm() && "expected immediate operand kind");
417 const MCOperand &RegOp = Inst.getOperand(0);
418 assert(RegOp.isReg() && "expected register operand kind");
420 int ImmValue = ImmOp.getImm();
421 tmpInst.setLoc(IDLoc);
422 if ( 0 <= ImmValue && ImmValue <= 65535) {
423 // for 0 <= j <= 65535.
424 // li d,j => ori d,$zero,j
425 tmpInst.setOpcode(Mips::ORi);
426 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
428 MCOperand::CreateReg(Mips::ZERO));
429 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
430 Instructions.push_back(tmpInst);
431 } else if ( ImmValue < 0 && ImmValue >= -32768) {
432 // for -32768 <= j < 0.
433 // li d,j => addiu d,$zero,j
434 tmpInst.setOpcode(Mips::ADDiu);
435 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
437 MCOperand::CreateReg(Mips::ZERO));
438 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
439 Instructions.push_back(tmpInst);
441 // for any other value of j that is representable as a 32-bit integer.
442 // li d,j => lui d,hi16(j)
444 tmpInst.setOpcode(Mips::LUi);
445 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
446 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
447 Instructions.push_back(tmpInst);
449 tmpInst.setOpcode(Mips::ORi);
450 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
451 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
452 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
453 tmpInst.setLoc(IDLoc);
454 Instructions.push_back(tmpInst);
458 void MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
459 SmallVectorImpl<MCInst> &Instructions){
461 const MCOperand &ImmOp = Inst.getOperand(2);
462 assert(ImmOp.isImm() && "expected immediate operand kind");
463 const MCOperand &SrcRegOp = Inst.getOperand(1);
464 assert(SrcRegOp.isReg() && "expected register operand kind");
465 const MCOperand &DstRegOp = Inst.getOperand(0);
466 assert(DstRegOp.isReg() && "expected register operand kind");
467 int ImmValue = ImmOp.getImm();
468 if ( -32768 <= ImmValue && ImmValue <= 65535) {
469 //for -32768 <= j <= 65535.
470 //la d,j(s) => addiu d,s,j
471 tmpInst.setOpcode(Mips::ADDiu);
472 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
473 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
474 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
475 Instructions.push_back(tmpInst);
477 //for any other value of j that is representable as a 32-bit integer.
478 //la d,j(s) => lui d,hi16(j)
481 tmpInst.setOpcode(Mips::LUi);
482 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
483 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
484 Instructions.push_back(tmpInst);
486 tmpInst.setOpcode(Mips::ORi);
487 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
488 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
489 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
490 Instructions.push_back(tmpInst);
492 tmpInst.setOpcode(Mips::ADDu);
493 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
494 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
495 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
496 Instructions.push_back(tmpInst);
500 void MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
501 SmallVectorImpl<MCInst> &Instructions){
503 const MCOperand &ImmOp = Inst.getOperand(1);
504 assert(ImmOp.isImm() && "expected immediate operand kind");
505 const MCOperand &RegOp = Inst.getOperand(0);
506 assert(RegOp.isReg() && "expected register operand kind");
507 int ImmValue = ImmOp.getImm();
508 if ( -32768 <= ImmValue && ImmValue <= 65535) {
509 //for -32768 <= j <= 65535.
510 //la d,j => addiu d,$zero,j
511 tmpInst.setOpcode(Mips::ADDiu);
512 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
514 MCOperand::CreateReg(Mips::ZERO));
515 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
516 Instructions.push_back(tmpInst);
518 //for any other value of j that is representable as a 32-bit integer.
519 //la d,j => lui d,hi16(j)
521 tmpInst.setOpcode(Mips::LUi);
522 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
523 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
524 Instructions.push_back(tmpInst);
526 tmpInst.setOpcode(Mips::ORi);
527 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
528 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
529 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
530 Instructions.push_back(tmpInst);
535 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
536 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
537 MCStreamer &Out, unsigned &ErrorInfo,
538 bool MatchingInlineAsm) {
540 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
543 switch (MatchResult) {
545 case Match_Success: {
546 if (needsExpansion(Inst)) {
547 SmallVector<MCInst, 4> Instructions;
548 expandInstruction(Inst, IDLoc, Instructions);
549 for(unsigned i =0; i < Instructions.size(); i++){
550 Out.EmitInstruction(Instructions[i]);
554 Out.EmitInstruction(Inst);
558 case Match_MissingFeature:
559 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
561 case Match_InvalidOperand: {
562 SMLoc ErrorLoc = IDLoc;
563 if (ErrorInfo != ~0U) {
564 if (ErrorInfo >= Operands.size())
565 return Error(IDLoc, "too few operands for instruction");
567 ErrorLoc = ((MipsOperand*)Operands[ErrorInfo])->getStartLoc();
568 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
571 return Error(ErrorLoc, "invalid operand for instruction");
573 case Match_MnemonicFail:
574 return Error(IDLoc, "invalid instruction");
579 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
585 CC = StringSwitch<unsigned>(Name)
619 // Although SGI documentation just cut out t0-t3 for n32/n64,
620 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
621 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
622 if (isMips64() && 8 <= CC && CC <= 11)
625 if (CC == -1 && isMips64())
626 CC = StringSwitch<unsigned>(Name)
638 int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
641 CC = matchCPURegisterName(Name);
643 return matchRegisterByNumber(CC,is64BitReg?Mips::CPU64RegsRegClassID:
644 Mips::CPURegsRegClassID);
646 if (Name[0] == 'f') {
647 StringRef NumString = Name.substr(1);
649 if( NumString.getAsInteger(10, IntVal))
650 return -1; // not integer
654 FpFormatTy Format = getFpFormat();
656 if (Format == FP_FORMAT_S || Format == FP_FORMAT_W)
657 return getReg(Mips::FGR32RegClassID, IntVal);
658 if (Format == FP_FORMAT_D) {
660 return getReg(Mips::FGR64RegClassID, IntVal);
662 // only even numbers available as register pairs
663 if (( IntVal > 31) || (IntVal%2 != 0))
665 return getReg(Mips::AFGR64RegClassID, IntVal/2);
671 void MipsAsmParser::setDefaultFpFormat() {
673 if (isMips64() || isFP64())
674 FpFormat = FP_FORMAT_D;
676 FpFormat = FP_FORMAT_S;
679 bool MipsAsmParser::requestsDoubleOperand(StringRef Mnemonic){
681 bool IsDouble = StringSwitch<bool>(Mnemonic.lower())
690 void MipsAsmParser::setFpFormat(StringRef Format) {
692 FpFormat = StringSwitch<FpFormatTy>(Format.lower())
693 .Case(".s", FP_FORMAT_S)
694 .Case(".d", FP_FORMAT_D)
695 .Case(".l", FP_FORMAT_L)
696 .Case(".w", FP_FORMAT_W)
697 .Default(FP_FORMAT_NONE);
700 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
708 int MipsAsmParser::getATReg() {
709 return Options.getATRegNum();
712 unsigned MipsAsmParser::getReg(int RC,int RegNo) {
713 return *(getContext().getRegisterInfo().getRegClass(RC).begin() + RegNo);
716 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
721 return getReg(RegClass, RegNum);
724 int MipsAsmParser::tryParseRegister(bool is64BitReg) {
725 const AsmToken &Tok = Parser.getTok();
728 if (Tok.is(AsmToken::Identifier)) {
729 std::string lowerCase = Tok.getString().lower();
730 RegNum = matchRegisterName(lowerCase, is64BitReg);
731 } else if (Tok.is(AsmToken::Integer))
732 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
733 is64BitReg ? Mips::CPU64RegsRegClassID
734 : Mips::CPURegsRegClassID);
739 tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
742 SMLoc S = Parser.getTok().getLoc();
745 RegNo = tryParseRegister(is64BitReg);
749 Operands.push_back(MipsOperand::CreateReg(RegNo, S,
750 Parser.getTok().getLoc()));
751 Parser.Lex(); // Eat register token.
755 bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
756 StringRef Mnemonic) {
757 // Check if the current operand has a custom associated parser, if so, try to
758 // custom parse the operand, or fallback to the general approach.
759 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
760 if (ResTy == MatchOperand_Success)
762 // If there wasn't a custom match, try the generic matcher below. Otherwise,
763 // there was a match, but an error occurred, in which case, just return that
764 // the operand parsing failed.
765 if (ResTy == MatchOperand_ParseFail)
768 switch (getLexer().getKind()) {
770 Error(Parser.getTok().getLoc(), "unexpected token in operand");
772 case AsmToken::Dollar: {
774 SMLoc S = Parser.getTok().getLoc();
775 Parser.Lex(); // Eat dollar token.
776 // parse register operand
777 if (!tryParseRegisterOperand(Operands, isMips64())) {
778 if (getLexer().is(AsmToken::LParen)) {
779 // check if it is indexed addressing operand
780 Operands.push_back(MipsOperand::CreateToken("(", S));
781 Parser.Lex(); // eat parenthesis
782 if (getLexer().isNot(AsmToken::Dollar))
785 Parser.Lex(); // eat dollar
786 if (tryParseRegisterOperand(Operands, isMips64()))
789 if (!getLexer().is(AsmToken::RParen))
792 S = Parser.getTok().getLoc();
793 Operands.push_back(MipsOperand::CreateToken(")", S));
798 // maybe it is a symbol reference
799 StringRef Identifier;
800 if (Parser.parseIdentifier(Identifier))
803 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
805 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
807 // Otherwise create a symbol ref.
808 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
811 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
814 case AsmToken::Identifier:
815 case AsmToken::LParen:
816 case AsmToken::Minus:
818 case AsmToken::Integer:
819 case AsmToken::String: {
820 // quoted label names
822 SMLoc S = Parser.getTok().getLoc();
823 if (getParser().parseExpression(IdVal))
825 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
826 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
829 case AsmToken::Percent: {
830 // it is a symbol reference or constant expression
832 SMLoc S = Parser.getTok().getLoc(); // start location of the operand
833 if (parseRelocOperand(IdVal))
836 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
838 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
840 } // case AsmToken::Percent
841 } // switch(getLexer().getKind())
845 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
847 Parser.Lex(); // eat % token
848 const AsmToken &Tok = Parser.getTok(); // get next token, operation
849 if (Tok.isNot(AsmToken::Identifier))
852 std::string Str = Tok.getIdentifier().str();
854 Parser.Lex(); // eat identifier
855 // now make expression from the rest of the operand
859 if (getLexer().getKind() == AsmToken::LParen) {
861 Parser.Lex(); // eat '(' token
862 if (getLexer().getKind() == AsmToken::Percent) {
863 Parser.Lex(); // eat % token
864 const AsmToken &nextTok = Parser.getTok();
865 if (nextTok.isNot(AsmToken::Identifier))
868 Str += nextTok.getIdentifier();
869 Parser.Lex(); // eat identifier
870 if (getLexer().getKind() != AsmToken::LParen)
875 if (getParser().parseParenExpression(IdVal,EndLoc))
878 while (getLexer().getKind() == AsmToken::RParen)
879 Parser.Lex(); // eat ')' token
882 return true; // parenthesis must follow reloc operand
884 // Check the type of the expression
885 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal)) {
886 // it's a constant, evaluate lo or hi value
887 int Val = MCE->getValue();
890 } else if (Str == "hi") {
891 Val = (Val & 0xffff0000) >> 16;
893 Res = MCConstantExpr::Create(Val, getContext());
897 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(IdVal)) {
898 // it's a symbol, create symbolic expression from symbol
899 StringRef Symbol = MSRE->getSymbol().getName();
900 MCSymbolRefExpr::VariantKind VK = getVariantKind(Str);
901 Res = MCSymbolRefExpr::Create(Symbol,VK,getContext());
907 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
910 StartLoc = Parser.getTok().getLoc();
911 RegNo = tryParseRegister(isMips64());
912 EndLoc = Parser.getTok().getLoc();
913 return (RegNo == (unsigned)-1);
916 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res) {
920 switch(getLexer().getKind()) {
923 case AsmToken::Integer:
924 case AsmToken::Minus:
926 return (getParser().parseExpression(Res));
927 case AsmToken::Percent:
928 return parseRelocOperand(Res);
929 case AsmToken::LParen:
930 return false; // it's probably assuming 0
935 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
936 SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
938 const MCExpr *IdVal = 0;
940 // first operand is the offset
941 S = Parser.getTok().getLoc();
943 if (parseMemOffset(IdVal))
944 return MatchOperand_ParseFail;
946 const AsmToken &Tok = Parser.getTok(); // get next token
947 if (Tok.isNot(AsmToken::LParen)) {
948 MipsOperand *Mnemonic = static_cast<MipsOperand*>(Operands[0]);
949 if (Mnemonic->getToken() == "la") {
950 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() -1);
951 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
952 return MatchOperand_Success;
954 Error(Parser.getTok().getLoc(), "'(' expected");
955 return MatchOperand_ParseFail;
958 Parser.Lex(); // Eat '(' token.
960 const AsmToken &Tok1 = Parser.getTok(); // get next token
961 if (Tok1.is(AsmToken::Dollar)) {
962 Parser.Lex(); // Eat '$' token.
963 if (tryParseRegisterOperand(Operands, isMips64())) {
964 Error(Parser.getTok().getLoc(), "unexpected token in operand");
965 return MatchOperand_ParseFail;
969 Error(Parser.getTok().getLoc(), "unexpected token in operand");
970 return MatchOperand_ParseFail;
973 const AsmToken &Tok2 = Parser.getTok(); // get next token
974 if (Tok2.isNot(AsmToken::RParen)) {
975 Error(Parser.getTok().getLoc(), "')' expected");
976 return MatchOperand_ParseFail;
979 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
981 Parser.Lex(); // Eat ')' token.
984 IdVal = MCConstantExpr::Create(0, getContext());
986 // now replace register operand with the mem operand
987 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
988 int RegNo = op->getReg();
989 // remove register from operands
991 // and add memory operand
992 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
994 return MatchOperand_Success;
997 MipsAsmParser::OperandMatchResultTy
998 MipsAsmParser::parseCPU64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1001 return MatchOperand_NoMatch;
1002 // if the first token is not '$' we have an error
1003 if (Parser.getTok().isNot(AsmToken::Dollar))
1004 return MatchOperand_NoMatch;
1006 Parser.Lex(); // Eat $
1007 if(!tryParseRegisterOperand(Operands, true)) {
1008 // set the proper register kind
1009 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1010 op->setRegKind(MipsOperand::Kind_CPU64Regs);
1011 return MatchOperand_Success;
1013 return MatchOperand_NoMatch;
1016 MipsAsmParser::OperandMatchResultTy
1017 MipsAsmParser::parseCPURegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1019 // if the first token is not '$' we have an error
1020 if (Parser.getTok().isNot(AsmToken::Dollar))
1021 return MatchOperand_NoMatch;
1023 Parser.Lex(); // Eat $
1024 if(!tryParseRegisterOperand(Operands, false)) {
1025 // set the propper register kind
1026 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1027 op->setRegKind(MipsOperand::Kind_CPURegs);
1028 return MatchOperand_Success;
1030 return MatchOperand_NoMatch;
1033 MipsAsmParser::OperandMatchResultTy
1034 MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1037 return MatchOperand_NoMatch;
1039 // if the first token is not '$' we have error
1040 if (Parser.getTok().isNot(AsmToken::Dollar))
1041 return MatchOperand_NoMatch;
1042 SMLoc S = Parser.getTok().getLoc();
1043 Parser.Lex(); // Eat $
1045 const AsmToken &Tok = Parser.getTok(); // get next token
1046 if (Tok.isNot(AsmToken::Integer))
1047 return MatchOperand_NoMatch;
1049 unsigned RegNum = Tok.getIntVal();
1050 // at the moment only hwreg29 is supported
1052 return MatchOperand_ParseFail;
1054 MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29, S,
1055 Parser.getTok().getLoc());
1056 op->setRegKind(MipsOperand::Kind_HWRegs);
1057 Operands.push_back(op);
1059 Parser.Lex(); // Eat reg number
1060 return MatchOperand_Success;
1063 MipsAsmParser::OperandMatchResultTy
1064 MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1067 return MatchOperand_NoMatch;
1068 //if the first token is not '$' we have error
1069 if (Parser.getTok().isNot(AsmToken::Dollar))
1070 return MatchOperand_NoMatch;
1071 SMLoc S = Parser.getTok().getLoc();
1072 Parser.Lex(); // Eat $
1074 const AsmToken &Tok = Parser.getTok(); // get next token
1075 if (Tok.isNot(AsmToken::Integer))
1076 return MatchOperand_NoMatch;
1078 unsigned RegNum = Tok.getIntVal();
1079 // at the moment only hwreg29 is supported
1081 return MatchOperand_ParseFail;
1083 MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S,
1084 Parser.getTok().getLoc());
1085 op->setRegKind(MipsOperand::Kind_HW64Regs);
1086 Operands.push_back(op);
1088 Parser.Lex(); // Eat reg number
1089 return MatchOperand_Success;
1092 MipsAsmParser::OperandMatchResultTy
1093 MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1095 //if the first token is not '$' we have error
1096 if (Parser.getTok().isNot(AsmToken::Dollar))
1097 return MatchOperand_NoMatch;
1098 SMLoc S = Parser.getTok().getLoc();
1099 Parser.Lex(); // Eat $
1101 const AsmToken &Tok = Parser.getTok(); // get next token
1102 if (Tok.is(AsmToken::Integer)) {
1103 RegNum = Tok.getIntVal();
1104 // at the moment only fcc0 is supported
1106 return MatchOperand_ParseFail;
1107 } else if (Tok.is(AsmToken::Identifier)) {
1108 // at the moment only fcc0 is supported
1109 if (Tok.getIdentifier() != "fcc0")
1110 return MatchOperand_ParseFail;
1112 return MatchOperand_NoMatch;
1114 MipsOperand *op = MipsOperand::CreateReg(Mips::FCC0, S,
1115 Parser.getTok().getLoc());
1116 op->setRegKind(MipsOperand::Kind_CCRRegs);
1117 Operands.push_back(op);
1119 Parser.Lex(); // Eat reg number
1120 return MatchOperand_Success;
1123 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
1125 MCSymbolRefExpr::VariantKind VK
1126 = StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
1127 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
1128 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
1129 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
1130 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
1131 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
1132 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
1133 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
1134 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
1135 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
1136 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
1137 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
1138 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
1139 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
1140 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
1141 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
1142 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
1143 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
1144 .Default(MCSymbolRefExpr::VK_None);
1149 static int ConvertCcString(StringRef CondString) {
1150 int CC = StringSwitch<unsigned>(CondString)
1172 bool MipsAsmParser::
1173 parseMathOperation(StringRef Name, SMLoc NameLoc,
1174 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1176 size_t Start = Name.find('.'), Next = Name.rfind('.');
1177 StringRef Format1 = Name.slice(Start, Next);
1178 // and add the first format to the operands
1179 Operands.push_back(MipsOperand::CreateToken(Format1, NameLoc));
1180 // now for the second format
1181 StringRef Format2 = Name.slice(Next, StringRef::npos);
1182 Operands.push_back(MipsOperand::CreateToken(Format2, NameLoc));
1184 // set the format for the first register
1185 setFpFormat(Format1);
1187 // Read the remaining operands.
1188 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1189 // Read the first operand.
1190 if (ParseOperand(Operands, Name)) {
1191 SMLoc Loc = getLexer().getLoc();
1192 Parser.eatToEndOfStatement();
1193 return Error(Loc, "unexpected token in argument list");
1196 if (getLexer().isNot(AsmToken::Comma)) {
1197 SMLoc Loc = getLexer().getLoc();
1198 Parser.eatToEndOfStatement();
1199 return Error(Loc, "unexpected token in argument list");
1202 Parser.Lex(); // Eat the comma.
1204 //set the format for the first register
1205 setFpFormat(Format2);
1207 // Parse and remember the operand.
1208 if (ParseOperand(Operands, Name)) {
1209 SMLoc Loc = getLexer().getLoc();
1210 Parser.eatToEndOfStatement();
1211 return Error(Loc, "unexpected token in argument list");
1215 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1216 SMLoc Loc = getLexer().getLoc();
1217 Parser.eatToEndOfStatement();
1218 return Error(Loc, "unexpected token in argument list");
1221 Parser.Lex(); // Consume the EndOfStatement
1225 bool MipsAsmParser::
1226 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1227 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1229 // floating point instructions: should register be treated as double?
1230 if (requestsDoubleOperand(Name)) {
1231 setFpFormat(FP_FORMAT_D);
1232 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
1236 setDefaultFpFormat();
1237 // Create the leading tokens for the mnemonic, split by '.' characters.
1238 size_t Start = 0, Next = Name.find('.');
1239 Mnemonic = Name.slice(Start, Next);
1241 Operands.push_back(MipsOperand::CreateToken(Mnemonic, NameLoc));
1243 if (Next != StringRef::npos) {
1244 // there is a format token in mnemonic
1245 // StringRef Rest = Name.slice(Next, StringRef::npos);
1246 size_t Dot = Name.find('.', Next+1);
1247 StringRef Format = Name.slice(Next, Dot);
1248 if (Dot == StringRef::npos) //only one '.' in a string, it's a format
1249 Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
1251 if (Name.startswith("c.")){
1252 // floating point compare, add '.' and immediate represent for cc
1253 Operands.push_back(MipsOperand::CreateToken(".", NameLoc));
1254 int Cc = ConvertCcString(Format);
1256 return Error(NameLoc, "Invalid conditional code");
1258 SMLoc E = SMLoc::getFromPointer(
1259 Parser.getTok().getLoc().getPointer() -1 );
1260 Operands.push_back(MipsOperand::CreateImm(
1261 MCConstantExpr::Create(Cc, getContext()), NameLoc, E));
1263 // trunc, ceil, floor ...
1264 return parseMathOperation(Name, NameLoc, Operands);
1267 // the rest is a format
1268 Format = Name.slice(Dot, StringRef::npos);
1269 Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
1272 setFpFormat(Format);
1276 // Read the remaining operands.
1277 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1278 // Read the first operand.
1279 if (ParseOperand(Operands, Mnemonic)) {
1280 SMLoc Loc = getLexer().getLoc();
1281 Parser.eatToEndOfStatement();
1282 return Error(Loc, "unexpected token in argument list");
1285 while (getLexer().is(AsmToken::Comma) ) {
1286 Parser.Lex(); // Eat the comma.
1288 // Parse and remember the operand.
1289 if (ParseOperand(Operands, Name)) {
1290 SMLoc Loc = getLexer().getLoc();
1291 Parser.eatToEndOfStatement();
1292 return Error(Loc, "unexpected token in argument list");
1297 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1298 SMLoc Loc = getLexer().getLoc();
1299 Parser.eatToEndOfStatement();
1300 return Error(Loc, "unexpected token in argument list");
1303 Parser.Lex(); // Consume the EndOfStatement
1307 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
1308 SMLoc Loc = getLexer().getLoc();
1309 Parser.eatToEndOfStatement();
1310 return Error(Loc, ErrorMsg);
1313 bool MipsAsmParser::parseSetNoAtDirective() {
1314 // line should look like:
1317 Options.setATReg(0);
1320 // if this is not the end of the statement, report error
1321 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1322 reportParseError("unexpected token in statement");
1325 Parser.Lex(); // Consume the EndOfStatement
1328 bool MipsAsmParser::parseSetAtDirective() {
1330 // .set at - defaults to $1
1334 if (getLexer().is(AsmToken::EndOfStatement)) {
1335 Options.setATReg(1);
1336 Parser.Lex(); // Consume the EndOfStatement
1338 } else if (getLexer().is(AsmToken::Equal)) {
1339 getParser().Lex(); //eat '='
1340 if (getLexer().isNot(AsmToken::Dollar)) {
1341 reportParseError("unexpected token in statement");
1344 Parser.Lex(); // eat '$'
1345 const AsmToken &Reg = Parser.getTok();
1346 if (Reg.is(AsmToken::Identifier)) {
1347 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
1348 } else if (Reg.is(AsmToken::Integer)) {
1349 AtRegNo = Reg.getIntVal();
1351 reportParseError("unexpected token in statement");
1355 if ( AtRegNo < 1 || AtRegNo > 31) {
1356 reportParseError("unexpected token in statement");
1360 if (!Options.setATReg(AtRegNo)) {
1361 reportParseError("unexpected token in statement");
1364 getParser().Lex(); //eat reg
1366 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1367 reportParseError("unexpected token in statement");
1370 Parser.Lex(); // Consume the EndOfStatement
1373 reportParseError("unexpected token in statement");
1378 bool MipsAsmParser::parseSetReorderDirective() {
1380 // if this is not the end of the statement, report error
1381 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1382 reportParseError("unexpected token in statement");
1385 Options.setReorder();
1386 Parser.Lex(); // Consume the EndOfStatement
1390 bool MipsAsmParser::parseSetNoReorderDirective() {
1392 // if this is not the end of the statement, report error
1393 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1394 reportParseError("unexpected token in statement");
1397 Options.setNoreorder();
1398 Parser.Lex(); // Consume the EndOfStatement
1402 bool MipsAsmParser::parseSetMacroDirective() {
1404 // if this is not the end of the statement, report error
1405 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1406 reportParseError("unexpected token in statement");
1410 Parser.Lex(); // Consume the EndOfStatement
1414 bool MipsAsmParser::parseSetNoMacroDirective() {
1416 // if this is not the end of the statement, report error
1417 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1418 reportParseError("`noreorder' must be set before `nomacro'");
1421 if (Options.isReorder()) {
1422 reportParseError("`noreorder' must be set before `nomacro'");
1425 Options.setNomacro();
1426 Parser.Lex(); // Consume the EndOfStatement
1429 bool MipsAsmParser::parseDirectiveSet() {
1432 const AsmToken &Tok = Parser.getTok();
1434 if (Tok.getString() == "noat") {
1435 return parseSetNoAtDirective();
1436 } else if (Tok.getString() == "at") {
1437 return parseSetAtDirective();
1438 } else if (Tok.getString() == "reorder") {
1439 return parseSetReorderDirective();
1440 } else if (Tok.getString() == "noreorder") {
1441 return parseSetNoReorderDirective();
1442 } else if (Tok.getString() == "macro") {
1443 return parseSetMacroDirective();
1444 } else if (Tok.getString() == "nomacro") {
1445 return parseSetNoMacroDirective();
1446 } else if (Tok.getString() == "nomips16") {
1447 // ignore this directive for now
1448 Parser.eatToEndOfStatement();
1450 } else if (Tok.getString() == "nomicromips") {
1451 // ignore this directive for now
1452 Parser.eatToEndOfStatement();
1459 /// parseDirectiveWord
1460 /// ::= .word [ expression (, expression)* ]
1461 bool MipsAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
1462 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1464 const MCExpr *Value;
1465 if (getParser().parseExpression(Value))
1468 getParser().getStreamer().EmitValue(Value, Size);
1470 if (getLexer().is(AsmToken::EndOfStatement))
1473 // FIXME: Improve diagnostic.
1474 if (getLexer().isNot(AsmToken::Comma))
1475 return Error(L, "unexpected token in directive");
1484 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
1486 StringRef IDVal = DirectiveID.getString();
1488 if ( IDVal == ".ent") {
1489 // ignore this directive for now
1494 if (IDVal == ".end") {
1495 // ignore this directive for now
1500 if (IDVal == ".frame") {
1501 // ignore this directive for now
1502 Parser.eatToEndOfStatement();
1506 if (IDVal == ".set") {
1507 return parseDirectiveSet();
1510 if (IDVal == ".fmask") {
1511 // ignore this directive for now
1512 Parser.eatToEndOfStatement();
1516 if (IDVal == ".mask") {
1517 // ignore this directive for now
1518 Parser.eatToEndOfStatement();
1522 if (IDVal == ".gpword") {
1523 // ignore this directive for now
1524 Parser.eatToEndOfStatement();
1528 if (IDVal == ".word") {
1529 parseDirectiveWord(4, DirectiveID.getLoc());
1536 extern "C" void LLVMInitializeMipsAsmParser() {
1537 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
1538 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
1539 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
1540 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
1543 #define GET_REGISTER_MATCHER
1544 #define GET_MATCHER_IMPLEMENTATION
1545 #include "MipsGenAsmMatcher.inc"