lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 class MipsDisassembler : public MCDisassembler {
  34   bool IsMicroMips;
  35   bool IsBigEndian;
  36 public:
  37   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
  43   bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
  44   bool hasMips32r6() const {
  45     return STI.getFeatureBits()[Mips::FeatureMips32r6];
  46   }
  47
  48   bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
  49
  50   bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
  51
  52   bool hasCOP3() const {
  53     // Only present in MIPS-I and MIPS-II
  54     return !hasMips32() && !hasMips3();
  55   }
  56
  57   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  58                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  59                               raw_ostream &VStream,
  60                               raw_ostream &CStream) const override;
  61 };
  62
  63 } // end anonymous namespace
  64
  65 // Forward declare these because the autogenerated code will reference them.
  66 // Definitions are further down.
  67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  68                                              unsigned RegNo,
  69                                              uint64_t Address,
  70                                              const void *Decoder);
  71
  72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
  73                                                  unsigned RegNo,
  74                                                  uint64_t Address,
  75                                                  const void *Decoder);
  76
  77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
  78                                                unsigned RegNo,
  79                                                uint64_t Address,
  80                                                const void *Decoder);
  81
  82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
  83                                                    unsigned RegNo,
  84                                                    uint64_t Address,
  85                                                    const void *Decoder);
  86
  87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
  88                                                     unsigned RegNo,
  89                                                     uint64_t Address,
  90                                                     const void *Decoder);
  91
  92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
  93                                              unsigned RegNo,
  94                                              uint64_t Address,
  95                                              const void *Decoder);
  96
  97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
  98                                            unsigned Insn,
  99                                            uint64_t Address,
 100                                            const void *Decoder);
 101
 102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 103                                             unsigned RegNo,
 104                                             uint64_t Address,
 105                                             const void *Decoder);
 106
 107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 108                                              unsigned RegNo,
 109                                              uint64_t Address,
 110                                              const void *Decoder);
 111
 112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 113                                              unsigned RegNo,
 114                                              uint64_t Address,
 115                                              const void *Decoder);
 116
 117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 118                                            unsigned RegNo,
 119                                            uint64_t Address,
 120                                            const void *Decoder);
 121
 122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 123                                            unsigned RegNo,
 124                                            uint64_t Address,
 125                                            const void *Decoder);
 126
 127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 128                                              uint64_t Address,
 129                                              const void *Decoder);
 130
 131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 132                                               unsigned Insn,
 133                                               uint64_t Address,
 134                                               const void *Decoder);
 135
 136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 137                                               unsigned RegNo,
 138                                               uint64_t Address,
 139                                               const void *Decoder);
 140
 141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 142                                                 unsigned RegNo,
 143                                                 uint64_t Address,
 144                                                 const void *Decoder);
 145
 146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 147                                                unsigned RegNo,
 148                                                uint64_t Address,
 149                                                const void *Decoder);
 150
 151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 152                                                unsigned RegNo,
 153                                                uint64_t Address,
 154                                                const void *Decoder);
 155
 156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 157                                                unsigned RegNo,
 158                                                uint64_t Address,
 159                                                const void *Decoder);
 160
 161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 162                                                unsigned RegNo,
 163                                                uint64_t Address,
 164                                                const void *Decoder);
 165
 166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 167                                                unsigned RegNo,
 168                                                uint64_t Address,
 169                                                const void *Decoder);
 170
 171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
 182                                             unsigned RegNo,
 183                                             uint64_t Address,
 184                                             const void *Decoder);
 185
 186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 187                                             unsigned RegNo,
 188                                             uint64_t Address,
 189                                             const void *Decoder);
 190
 191 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 192                                        unsigned Offset,
 193                                        uint64_t Address,
 194                                        const void *Decoder);
 195
 196 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 197                                      unsigned Insn,
 198                                      uint64_t Address,
 199                                      const void *Decoder);
 200
 201 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 202                                          unsigned Offset,
 203                                          uint64_t Address,
 204                                          const void *Decoder);
 205
 206 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 207                                          unsigned Offset,
 208                                          uint64_t Address,
 209                                          const void *Decoder);
 210
 211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 212 // shifted left by 1 bit.
 213 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
 214                                           unsigned Offset,
 215                                           uint64_t Address,
 216                                           const void *Decoder);
 217
 218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
 219 // shifted left by 1 bit.
 220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
 221                                            unsigned Offset,
 222                                            uint64_t Address,
 223                                            const void *Decoder);
 224
 225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 226 // shifted left by 1 bit.
 227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 228                                          unsigned Offset,
 229                                          uint64_t Address,
 230                                          const void *Decoder);
 231
 232 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 233 // shifted left by 1 bit.
 234 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 235                                        unsigned Insn,
 236                                        uint64_t Address,
 237                                        const void *Decoder);
 238
 239 static DecodeStatus DecodeMem(MCInst &Inst,
 240                               unsigned Insn,
 241                               uint64_t Address,
 242                               const void *Decoder);
 243
 244 static DecodeStatus DecodeMemEVA(MCInst &Inst,
 245                                  unsigned Insn,
 246                                  uint64_t Address,
 247                                  const void *Decoder);
 248
 249 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 250                               unsigned Insn,
 251                               uint64_t Address,
 252                               const void *Decoder);
 253
 254 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
 255                                              unsigned Insn,
 256                                              uint64_t Address,
 257                                              const void *Decoder);
 258
 259 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
 260                                     unsigned Insn,
 261                                     uint64_t Address,
 262                                     const void *Decoder);
 263
 264 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
 265                                        unsigned Insn,
 266                                        uint64_t Address,
 267                                        const void *Decoder);
 268
 269 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
 270                                     unsigned Insn,
 271                                     uint64_t Address,
 272                                     const void *Decoder);
 273
 274 static DecodeStatus DecodeSyncI(MCInst &Inst,
 275                                 unsigned Insn,
 276                                 uint64_t Address,
 277                                 const void *Decoder);
 278
 279 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 280                                     uint64_t Address, const void *Decoder);
 281
 282 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 283                                     unsigned Insn,
 284                                     uint64_t Address,
 285                                     const void *Decoder);
 286
 287 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
 288                                           unsigned Insn,
 289                                           uint64_t Address,
 290                                           const void *Decoder);
 291
 292 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
 293                                           unsigned Insn,
 294                                           uint64_t Address,
 295                                           const void *Decoder);
 296
 297 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
 298                                                unsigned Insn,
 299                                                uint64_t Address,
 300                                                const void *Decoder);
 301
 302 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
 303                                     unsigned Insn,
 304                                     uint64_t Address,
 305                                     const void *Decoder);
 306
 307 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 308                                      unsigned Insn,
 309                                      uint64_t Address,
 310                                      const void *Decoder);
 311
 312 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 313                                      unsigned Insn,
 314                                      uint64_t Address,
 315                                      const void *Decoder);
 316
 317 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 318                                uint64_t Address,
 319                                const void *Decoder);
 320
 321 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 322                                uint64_t Address,
 323                                const void *Decoder);
 324
 325 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 326                                uint64_t Address,
 327                                const void *Decoder);
 328
 329 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
 330                                uint64_t Address,
 331                                const void *Decoder);
 332
 333 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 334                                        unsigned Insn,
 335                                        uint64_t Address,
 336                                        const void *Decoder);
 337
 338 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 339                                        unsigned Value,
 340                                        uint64_t Address,
 341                                        const void *Decoder);
 342
 343 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
 344                                     unsigned Value,
 345                                     uint64_t Address,
 346                                     const void *Decoder);
 347
 348 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
 349                                   unsigned Value,
 350                                   uint64_t Address,
 351                                   const void *Decoder);
 352
 353 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
 354                                               unsigned Value,
 355                                               uint64_t Address,
 356                                               const void *Decoder);
 357
 358 static DecodeStatus DecodeSimm4(MCInst &Inst,
 359                                 unsigned Value,
 360                                 uint64_t Address,
 361                                 const void *Decoder);
 362
 363 static DecodeStatus DecodeSimm16(MCInst &Inst,
 364                                  unsigned Insn,
 365                                  uint64_t Address,
 366                                  const void *Decoder);
 367
 368 // Decode the immediate field of an LSA instruction which
 369 // is off by one.
 370 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 371                                  unsigned Insn,
 372                                  uint64_t Address,
 373                                  const void *Decoder);
 374
 375 static DecodeStatus DecodeInsSize(MCInst &Inst,
 376                                   unsigned Insn,
 377                                   uint64_t Address,
 378                                   const void *Decoder);
 379
 380 static DecodeStatus DecodeExtSize(MCInst &Inst,
 381                                   unsigned Insn,
 382                                   uint64_t Address,
 383                                   const void *Decoder);
 384
 385 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 386                                      uint64_t Address, const void *Decoder);
 387
 388 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 389                                      uint64_t Address, const void *Decoder);
 390
 391 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
 392                                   uint64_t Address, const void *Decoder);
 393
 394 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
 395                                     uint64_t Address, const void *Decoder);
 396
 397 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
 398                                    uint64_t Address, const void *Decoder);
 399
 400 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
 401                                      uint64_t Address, const void *Decoder);
 402
 403 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 404 /// handle.
 405 template <typename InsnType>
 406 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 407                                    const void *Decoder);
 408
 409 template <typename InsnType>
 410 static DecodeStatus
 411 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 412                       const void *Decoder);
 413
 414 template <typename InsnType>
 415 static DecodeStatus
 416 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 417                        const void *Decoder);
 418
 419 template <typename InsnType>
 420 static DecodeStatus
 421 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 422                        const void *Decoder);
 423
 424 template <typename InsnType>
 425 static DecodeStatus
 426 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 427                        const void *Decoder);
 428
 429 template <typename InsnType>
 430 static DecodeStatus
 431 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 432                       const void *Decoder);
 433
 434 template <typename InsnType>
 435 static DecodeStatus
 436 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 437                        const void *Decoder);
 438
 439 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 440                                          uint64_t Address,
 441                                          const void *Decoder);
 442
 443 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 444                                            uint64_t Address,
 445                                            const void *Decoder);
 446
 447 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
 448                                        uint64_t Address,
 449                                        const void *Decoder);
 450
 451 namespace llvm {
 452 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 453               TheMips64elTarget;
 454 }
 455
 456 static MCDisassembler *createMipsDisassembler(
 457                        const Target &T,
 458                        const MCSubtargetInfo &STI,
 459                        MCContext &Ctx) {
 460   return new MipsDisassembler(STI, Ctx, true);
 461 }
 462
 463 static MCDisassembler *createMipselDisassembler(
 464                        const Target &T,
 465                        const MCSubtargetInfo &STI,
 466                        MCContext &Ctx) {
 467   return new MipsDisassembler(STI, Ctx, false);
 468 }
 469
 470 extern "C" void LLVMInitializeMipsDisassembler() {
 471   // Register the disassembler.
 472   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 473                                          createMipsDisassembler);
 474   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 475                                          createMipselDisassembler);
 476   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 477                                          createMipsDisassembler);
 478   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 479                                          createMipselDisassembler);
 480 }
 481
 482 #include "MipsGenDisassemblerTables.inc"
 483
 484 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 485   const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
 486   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 487   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 488 }
 489
 490 template <typename InsnType>
 491 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 492                                    const void *Decoder) {
 493   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 494   // The size of the n field depends on the element size
 495   // The register class also depends on this.
 496   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 497   unsigned NSize = 0;
 498   DecodeFN RegDecoder = nullptr;
 499   if ((tmp & 0x18) == 0x00) { // INSVE_B
 500     NSize = 4;
 501     RegDecoder = DecodeMSA128BRegisterClass;
 502   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 503     NSize = 3;
 504     RegDecoder = DecodeMSA128HRegisterClass;
 505   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 506     NSize = 2;
 507     RegDecoder = DecodeMSA128WRegisterClass;
 508   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 509     NSize = 1;
 510     RegDecoder = DecodeMSA128DRegisterClass;
 511   } else
 512     llvm_unreachable("Invalid encoding");
 513
 514   assert(NSize != 0 && RegDecoder != nullptr);
 515
 516   // $wd
 517   tmp = fieldFromInstruction(insn, 6, 5);
 518   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 519     return MCDisassembler::Fail;
 520   // $wd_in
 521   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 522     return MCDisassembler::Fail;
 523   // $n
 524   tmp = fieldFromInstruction(insn, 16, NSize);
 525   MI.addOperand(MCOperand::createImm(tmp));
 526   // $ws
 527   tmp = fieldFromInstruction(insn, 11, 5);
 528   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 529     return MCDisassembler::Fail;
 530   // $n2
 531   MI.addOperand(MCOperand::createImm(0));
 532
 533   return MCDisassembler::Success;
 534 }
 535
 536 template <typename InsnType>
 537 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 538                                           uint64_t Address,
 539                                           const void *Decoder) {
 540   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 541   // (otherwise we would have matched the ADDI instruction from the earlier
 542   // ISA's instead).
 543   //
 544   // We have:
 545   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 546   //      BOVC if rs >= rt
 547   //      BEQZALC if rs == 0 && rt != 0
 548   //      BEQC if rs < rt && rs != 0
 549
 550   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 551   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 552   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 553   bool HasRs = false;
 554
 555   if (Rs >= Rt) {
 556     MI.setOpcode(Mips::BOVC);
 557     HasRs = true;
 558   } else if (Rs != 0 && Rs < Rt) {
 559     MI.setOpcode(Mips::BEQC);
 560     HasRs = true;
 561   } else
 562     MI.setOpcode(Mips::BEQZALC);
 563
 564   if (HasRs)
 565     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 566                                        Rs)));
 567
 568   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 569                                      Rt)));
 570   MI.addOperand(MCOperand::createImm(Imm));
 571
 572   return MCDisassembler::Success;
 573 }
 574
 575 template <typename InsnType>
 576 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 577                                            uint64_t Address,
 578                                            const void *Decoder) {
 579   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 580   // (otherwise we would have matched the ADDI instruction from the earlier
 581   // ISA's instead).
 582   //
 583   // We have:
 584   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 585   //      BNVC if rs >= rt
 586   //      BNEZALC if rs == 0 && rt != 0
 587   //      BNEC if rs < rt && rs != 0
 588
 589   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 590   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 591   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 592   bool HasRs = false;
 593
 594   if (Rs >= Rt) {
 595     MI.setOpcode(Mips::BNVC);
 596     HasRs = true;
 597   } else if (Rs != 0 && Rs < Rt) {
 598     MI.setOpcode(Mips::BNEC);
 599     HasRs = true;
 600   } else
 601     MI.setOpcode(Mips::BNEZALC);
 602
 603   if (HasRs)
 604     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 605                                        Rs)));
 606
 607   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 608                                      Rt)));
 609   MI.addOperand(MCOperand::createImm(Imm));
 610
 611   return MCDisassembler::Success;
 612 }
 613
 614 template <typename InsnType>
 615 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 616                                            uint64_t Address,
 617                                            const void *Decoder) {
 618   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 619   // (otherwise we would have matched the BLEZL instruction from the earlier
 620   // ISA's instead).
 621   //
 622   // We have:
 623   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 624   //      Invalid if rs == 0
 625   //      BLEZC   if rs == 0  && rt != 0
 626   //      BGEZC   if rs == rt && rt != 0
 627   //      BGEC    if rs != rt && rs != 0  && rt != 0
 628
 629   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 630   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 631   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 632   bool HasRs = false;
 633
 634   if (Rt == 0)
 635     return MCDisassembler::Fail;
 636   else if (Rs == 0)
 637     MI.setOpcode(Mips::BLEZC);
 638   else if (Rs == Rt)
 639     MI.setOpcode(Mips::BGEZC);
 640   else {
 641     HasRs = true;
 642     MI.setOpcode(Mips::BGEC);
 643   }
 644
 645   if (HasRs)
 646     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 647                                        Rs)));
 648
 649   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 650                                      Rt)));
 651
 652   MI.addOperand(MCOperand::createImm(Imm));
 653
 654   return MCDisassembler::Success;
 655 }
 656
 657 template <typename InsnType>
 658 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 659                                            uint64_t Address,
 660                                            const void *Decoder) {
 661   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 662   // (otherwise we would have matched the BGTZL instruction from the earlier
 663   // ISA's instead).
 664   //
 665   // We have:
 666   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 667   //      Invalid if rs == 0
 668   //      BGTZC   if rs == 0  && rt != 0
 669   //      BLTZC   if rs == rt && rt != 0
 670   //      BLTC    if rs != rt && rs != 0  && rt != 0
 671
 672   bool HasRs = false;
 673
 674   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 675   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 676   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 677
 678   if (Rt == 0)
 679     return MCDisassembler::Fail;
 680   else if (Rs == 0)
 681     MI.setOpcode(Mips::BGTZC);
 682   else if (Rs == Rt)
 683     MI.setOpcode(Mips::BLTZC);
 684   else {
 685     MI.setOpcode(Mips::BLTC);
 686     HasRs = true;
 687   }
 688
 689   if (HasRs)
 690     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 691                                               Rs)));
 692
 693   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 694                                      Rt)));
 695
 696   MI.addOperand(MCOperand::createImm(Imm));
 697
 698   return MCDisassembler::Success;
 699 }
 700
 701 template <typename InsnType>
 702 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 703                                           uint64_t Address,
 704                                           const void *Decoder) {
 705   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 706   // (otherwise we would have matched the BGTZ instruction from the earlier
 707   // ISA's instead).
 708   //
 709   // We have:
 710   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 711   //      BGTZ    if rt == 0
 712   //      BGTZALC if rs == 0 && rt != 0
 713   //      BLTZALC if rs != 0 && rs == rt
 714   //      BLTUC   if rs != 0 && rs != rt
 715
 716   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 717   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 718   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 719   bool HasRs = false;
 720   bool HasRt = false;
 721
 722   if (Rt == 0) {
 723     MI.setOpcode(Mips::BGTZ);
 724     HasRs = true;
 725   } else if (Rs == 0) {
 726     MI.setOpcode(Mips::BGTZALC);
 727     HasRt = true;
 728   } else if (Rs == Rt) {
 729     MI.setOpcode(Mips::BLTZALC);
 730     HasRs = true;
 731   } else {
 732     MI.setOpcode(Mips::BLTUC);
 733     HasRs = true;
 734     HasRt = true;
 735   }
 736
 737   if (HasRs)
 738     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 739                                        Rs)));
 740
 741   if (HasRt)
 742     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 743                                        Rt)));
 744
 745   MI.addOperand(MCOperand::createImm(Imm));
 746
 747   return MCDisassembler::Success;
 748 }
 749
 750 template <typename InsnType>
 751 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 752                                            uint64_t Address,
 753                                            const void *Decoder) {
 754   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 755   // (otherwise we would have matched the BLEZL instruction from the earlier
 756   // ISA's instead).
 757   //
 758   // We have:
 759   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 760   //      Invalid   if rs == 0
 761   //      BLEZALC   if rs == 0  && rt != 0
 762   //      BGEZALC   if rs == rt && rt != 0
 763   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 764
 765   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 766   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 767   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 768   bool HasRs = false;
 769
 770   if (Rt == 0)
 771     return MCDisassembler::Fail;
 772   else if (Rs == 0)
 773     MI.setOpcode(Mips::BLEZALC);
 774   else if (Rs == Rt)
 775     MI.setOpcode(Mips::BGEZALC);
 776   else {
 777     HasRs = true;
 778     MI.setOpcode(Mips::BGEUC);
 779   }
 780
 781   if (HasRs)
 782     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 783                                        Rs)));
 784   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 785                                      Rt)));
 786
 787   MI.addOperand(MCOperand::createImm(Imm));
 788
 789   return MCDisassembler::Success;
 790 }
 791
 792 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 793 /// according to the given endianess.
 794 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 795                                       uint64_t &Size, uint32_t &Insn,
 796                                       bool IsBigEndian) {
 797   // We want to read exactly 2 Bytes of data.
 798   if (Bytes.size() < 2) {
 799     Size = 0;
 800     return MCDisassembler::Fail;
 801   }
 802
 803   if (IsBigEndian) {
 804     Insn = (Bytes[0] << 8) | Bytes[1];
 805   } else {
 806     Insn = (Bytes[1] << 8) | Bytes[0];
 807   }
 808
 809   return MCDisassembler::Success;
 810 }
 811
 812 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 813 /// according to the given endianess
 814 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 815                                       uint64_t &Size, uint32_t &Insn,
 816                                       bool IsBigEndian, bool IsMicroMips) {
 817   // We want to read exactly 4 Bytes of data.
 818   if (Bytes.size() < 4) {
 819     Size = 0;
 820     return MCDisassembler::Fail;
 821   }
 822
 823   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 824   // always precede the low 16 bits in the instruction stream (that is, they
 825   // are placed at lower addresses in the instruction stream).
 826   //
 827   // microMIPS byte ordering:
 828   //   Big-endian:    0 | 1 | 2 | 3
 829   //   Little-endian: 1 | 0 | 3 | 2
 830
 831   if (IsBigEndian) {
 832     // Encoded as a big-endian 32-bit word in the stream.
 833     Insn =
 834         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 835   } else {
 836     if (IsMicroMips) {
 837       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 838              (Bytes[1] << 24);
 839     } else {
 840       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 841              (Bytes[3] << 24);
 842     }
 843   }
 844
 845   return MCDisassembler::Success;
 846 }
 847
 848 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 849                                               ArrayRef<uint8_t> Bytes,
 850                                               uint64_t Address,
 851                                               raw_ostream &VStream,
 852                                               raw_ostream &CStream) const {
 853   uint32_t Insn;
 854   DecodeStatus Result;
 855
 856   if (IsMicroMips) {
 857     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 858
 859     if (hasMips32r6()) {
 860       DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
 861       // Calling the auto-generated decoder function for microMIPS32R6
 862       // (and microMIPS64R6) 16-bit instructions.
 863       Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
 864                                  Address, this, STI);
 865       if (Result != MCDisassembler::Fail) {
 866         Size = 2;
 867         return Result;
 868       }
 869     }
 870
 871     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 872     // Calling the auto-generated decoder function for microMIPS 16-bit
 873     // instructions.
 874     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 875                                this, STI);
 876     if (Result != MCDisassembler::Fail) {
 877       Size = 2;
 878       return Result;
 879     }
 880
 881     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 882     if (Result == MCDisassembler::Fail)
 883       return MCDisassembler::Fail;
 884
 885     if (hasMips32r6()) {
 886       DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
 887       // Calling the auto-generated decoder function.
 888       Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
 889                                  this, STI);
 890       if (Result != MCDisassembler::Fail) {
 891         Size = 4;
 892         return Result;
 893       }
 894     }
 895
 896     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 897     // Calling the auto-generated decoder function.
 898     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 899                                this, STI);
 900     if (Result != MCDisassembler::Fail) {
 901       Size = 4;
 902       return Result;
 903     }
 904     return MCDisassembler::Fail;
 905   }
 906
 907   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 908   if (Result == MCDisassembler::Fail)
 909     return MCDisassembler::Fail;
 910
 911   if (hasCOP3()) {
 912     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 913     Result =
 914         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 915     if (Result != MCDisassembler::Fail) {
 916       Size = 4;
 917       return Result;
 918     }
 919   }
 920
 921   if (hasMips32r6() && isGP64()) {
 922     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 923     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 924                                Address, this, STI);
 925     if (Result != MCDisassembler::Fail) {
 926       Size = 4;
 927       return Result;
 928     }
 929   }
 930
 931   if (hasMips32r6()) {
 932     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 933     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 934                                Address, this, STI);
 935     if (Result != MCDisassembler::Fail) {
 936       Size = 4;
 937       return Result;
 938     }
 939   }
 940
 941   if (hasCnMips()) {
 942     DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
 943     Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
 944                                Address, this, STI);
 945     if (Result != MCDisassembler::Fail) {
 946       Size = 4;
 947       return Result;
 948     }
 949   }
 950
 951   if (isGP64()) {
 952     DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
 953     Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
 954                                Address, this, STI);
 955     if (Result != MCDisassembler::Fail) {
 956       Size = 4;
 957       return Result;
 958     }
 959   }
 960
 961   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 962   // Calling the auto-generated decoder function.
 963   Result =
 964       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 965   if (Result != MCDisassembler::Fail) {
 966     Size = 4;
 967     return Result;
 968   }
 969
 970   return MCDisassembler::Fail;
 971 }
 972
 973 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 974                                                  unsigned RegNo,
 975                                                  uint64_t Address,
 976                                                  const void *Decoder) {
 977
 978   return MCDisassembler::Fail;
 979
 980 }
 981
 982 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 983                                              unsigned RegNo,
 984                                              uint64_t Address,
 985                                              const void *Decoder) {
 986
 987   if (RegNo > 31)
 988     return MCDisassembler::Fail;
 989
 990   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 991   Inst.addOperand(MCOperand::createReg(Reg));
 992   return MCDisassembler::Success;
 993 }
 994
 995 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 996                                                unsigned RegNo,
 997                                                uint64_t Address,
 998                                                const void *Decoder) {
 999   if (RegNo > 7)
1000     return MCDisassembler::Fail;
1001   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1002   Inst.addOperand(MCOperand::createReg(Reg));
1003   return MCDisassembler::Success;
1004 }
1005
1006 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
1007                                                    unsigned RegNo,
1008                                                    uint64_t Address,
1009                                                    const void *Decoder) {
1010   if (RegNo > 7)
1011     return MCDisassembler::Fail;
1012   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1013   Inst.addOperand(MCOperand::createReg(Reg));
1014   return MCDisassembler::Success;
1015 }
1016
1017 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
1018                                                     unsigned RegNo,
1019                                                     uint64_t Address,
1020                                                     const void *Decoder) {
1021   if (RegNo > 7)
1022     return MCDisassembler::Fail;
1023   unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1024   Inst.addOperand(MCOperand::createReg(Reg));
1025   return MCDisassembler::Success;
1026 }
1027
1028 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1029                                              unsigned RegNo,
1030                                              uint64_t Address,
1031                                              const void *Decoder) {
1032   if (RegNo > 31)
1033     return MCDisassembler::Fail;
1034   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1035   Inst.addOperand(MCOperand::createReg(Reg));
1036   return MCDisassembler::Success;
1037 }
1038
1039 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1040                                            unsigned RegNo,
1041                                            uint64_t Address,
1042                                            const void *Decoder) {
1043   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1044     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1045
1046   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1047 }
1048
1049 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1050                                             unsigned RegNo,
1051                                             uint64_t Address,
1052                                             const void *Decoder) {
1053   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1054 }
1055
1056 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1057                                              unsigned RegNo,
1058                                              uint64_t Address,
1059                                              const void *Decoder) {
1060   if (RegNo > 31)
1061     return MCDisassembler::Fail;
1062
1063   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1064   Inst.addOperand(MCOperand::createReg(Reg));
1065   return MCDisassembler::Success;
1066 }
1067
1068 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1069                                              unsigned RegNo,
1070                                              uint64_t Address,
1071                                              const void *Decoder) {
1072   if (RegNo > 31)
1073     return MCDisassembler::Fail;
1074
1075   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1076   Inst.addOperand(MCOperand::createReg(Reg));
1077   return MCDisassembler::Success;
1078 }
1079
1080 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1081                                            unsigned RegNo,
1082                                            uint64_t Address,
1083                                            const void *Decoder) {
1084   if (RegNo > 31)
1085     return MCDisassembler::Fail;
1086   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1087   Inst.addOperand(MCOperand::createReg(Reg));
1088   return MCDisassembler::Success;
1089 }
1090
1091 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1092                                            unsigned RegNo,
1093                                            uint64_t Address,
1094                                            const void *Decoder) {
1095   if (RegNo > 7)
1096     return MCDisassembler::Fail;
1097   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1098   Inst.addOperand(MCOperand::createReg(Reg));
1099   return MCDisassembler::Success;
1100 }
1101
1102 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1103                                              uint64_t Address,
1104                                              const void *Decoder) {
1105   if (RegNo > 31)
1106     return MCDisassembler::Fail;
1107
1108   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1109   Inst.addOperand(MCOperand::createReg(Reg));
1110   return MCDisassembler::Success;
1111 }
1112
1113 static DecodeStatus DecodeMem(MCInst &Inst,
1114                               unsigned Insn,
1115                               uint64_t Address,
1116                               const void *Decoder) {
1117   int Offset = SignExtend32<16>(Insn & 0xffff);
1118   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1119   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1120
1121   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1122   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1123
1124   if (Inst.getOpcode() == Mips::SC ||
1125       Inst.getOpcode() == Mips::SCD)
1126     Inst.addOperand(MCOperand::createReg(Reg));
1127
1128   Inst.addOperand(MCOperand::createReg(Reg));
1129   Inst.addOperand(MCOperand::createReg(Base));
1130   Inst.addOperand(MCOperand::createImm(Offset));
1131
1132   return MCDisassembler::Success;
1133 }
1134
1135 static DecodeStatus DecodeMemEVA(MCInst &Inst,
1136                                  unsigned Insn,
1137                                  uint64_t Address,
1138                                  const void *Decoder) {
1139   int Offset = SignExtend32<9>(Insn >> 7);
1140   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1141   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1142
1143   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1144   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1145
1146    if (Inst.getOpcode() == Mips::SCE)
1147      Inst.addOperand(MCOperand::createReg(Reg));
1148
1149   Inst.addOperand(MCOperand::createReg(Reg));
1150   Inst.addOperand(MCOperand::createReg(Base));
1151   Inst.addOperand(MCOperand::createImm(Offset));
1152
1153   return MCDisassembler::Success;
1154 }
1155
1156 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1157                               unsigned Insn,
1158                               uint64_t Address,
1159                               const void *Decoder) {
1160   int Offset = SignExtend32<16>(Insn & 0xffff);
1161   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1162   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1163
1164   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1165
1166   Inst.addOperand(MCOperand::createReg(Base));
1167   Inst.addOperand(MCOperand::createImm(Offset));
1168   Inst.addOperand(MCOperand::createImm(Hint));
1169
1170   return MCDisassembler::Success;
1171 }
1172
1173 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1174                                     unsigned Insn,
1175                                     uint64_t Address,
1176                                     const void *Decoder) {
1177   int Offset = SignExtend32<12>(Insn & 0xfff);
1178   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1179   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1180
1181   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1182
1183   Inst.addOperand(MCOperand::createReg(Base));
1184   Inst.addOperand(MCOperand::createImm(Offset));
1185   Inst.addOperand(MCOperand::createImm(Hint));
1186
1187   return MCDisassembler::Success;
1188 }
1189
1190 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
1191                                     unsigned Insn,
1192                                     uint64_t Address,
1193                                     const void *Decoder) {
1194   int Offset = SignExtend32<9>(Insn & 0x1ff);
1195   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1196   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1197
1198   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1199
1200   Inst.addOperand(MCOperand::createReg(Base));
1201   Inst.addOperand(MCOperand::createImm(Offset));
1202   Inst.addOperand(MCOperand::createImm(Hint));
1203
1204   return MCDisassembler::Success;
1205 }
1206
1207 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
1208                                              unsigned Insn,
1209                                              uint64_t Address,
1210                                              const void *Decoder) {
1211   int Offset = SignExtend32<9>(Insn >> 7);
1212   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1213   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1214
1215   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1216
1217   Inst.addOperand(MCOperand::createReg(Base));
1218   Inst.addOperand(MCOperand::createImm(Offset));
1219   Inst.addOperand(MCOperand::createImm(Hint));
1220
1221   return MCDisassembler::Success;
1222 }
1223
1224 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
1225                                        unsigned Insn,
1226                                        uint64_t Address,
1227                                        const void *Decoder) {
1228   int Offset = SignExtend32<9>(Insn & 0x1ff);
1229   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1230   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1231
1232   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1233   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1234
1235   Inst.addOperand(MCOperand::createReg(Reg));
1236   Inst.addOperand(MCOperand::createReg(Base));
1237   Inst.addOperand(MCOperand::createImm(Offset));
1238
1239   return MCDisassembler::Success;
1240 }
1241
1242 static DecodeStatus DecodeSyncI(MCInst &Inst,
1243                               unsigned Insn,
1244                               uint64_t Address,
1245                               const void *Decoder) {
1246   int Offset = SignExtend32<16>(Insn & 0xffff);
1247   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1248
1249   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1250
1251   Inst.addOperand(MCOperand::createReg(Base));
1252   Inst.addOperand(MCOperand::createImm(Offset));
1253
1254   return MCDisassembler::Success;
1255 }
1256
1257 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1258                                     uint64_t Address, const void *Decoder) {
1259   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1260   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1261   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1262
1263   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1264   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1265
1266   Inst.addOperand(MCOperand::createReg(Reg));
1267   Inst.addOperand(MCOperand::createReg(Base));
1268
1269   // The immediate field of an LD/ST instruction is scaled which means it must
1270   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1271   // data format.
1272   // .b - 1 byte
1273   // .h - 2 bytes
1274   // .w - 4 bytes
1275   // .d - 8 bytes
1276   switch(Inst.getOpcode())
1277   {
1278   default:
1279     assert (0 && "Unexpected instruction");
1280     return MCDisassembler::Fail;
1281     break;
1282   case Mips::LD_B:
1283   case Mips::ST_B:
1284     Inst.addOperand(MCOperand::createImm(Offset));
1285     break;
1286   case Mips::LD_H:
1287   case Mips::ST_H:
1288     Inst.addOperand(MCOperand::createImm(Offset * 2));
1289     break;
1290   case Mips::LD_W:
1291   case Mips::ST_W:
1292     Inst.addOperand(MCOperand::createImm(Offset * 4));
1293     break;
1294   case Mips::LD_D:
1295   case Mips::ST_D:
1296     Inst.addOperand(MCOperand::createImm(Offset * 8));
1297     break;
1298   }
1299
1300   return MCDisassembler::Success;
1301 }
1302
1303 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1304                                     unsigned Insn,
1305                                     uint64_t Address,
1306                                     const void *Decoder) {
1307   unsigned Offset = Insn & 0xf;
1308   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1309   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1310
1311   switch (Inst.getOpcode()) {
1312     case Mips::LBU16_MM:
1313     case Mips::LHU16_MM:
1314     case Mips::LW16_MM:
1315       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1316             == MCDisassembler::Fail)
1317         return MCDisassembler::Fail;
1318       break;
1319     case Mips::SB16_MM:
1320     case Mips::SH16_MM:
1321     case Mips::SW16_MM:
1322       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1323             == MCDisassembler::Fail)
1324         return MCDisassembler::Fail;
1325       break;
1326   }
1327
1328   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1329         == MCDisassembler::Fail)
1330     return MCDisassembler::Fail;
1331
1332   switch (Inst.getOpcode()) {
1333     case Mips::LBU16_MM:
1334       if (Offset == 0xf)
1335         Inst.addOperand(MCOperand::createImm(-1));
1336       else
1337         Inst.addOperand(MCOperand::createImm(Offset));
1338       break;
1339     case Mips::SB16_MM:
1340       Inst.addOperand(MCOperand::createImm(Offset));
1341       break;
1342     case Mips::LHU16_MM:
1343     case Mips::SH16_MM:
1344       Inst.addOperand(MCOperand::createImm(Offset << 1));
1345       break;
1346     case Mips::LW16_MM:
1347     case Mips::SW16_MM:
1348       Inst.addOperand(MCOperand::createImm(Offset << 2));
1349       break;
1350   }
1351
1352   return MCDisassembler::Success;
1353 }
1354
1355 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1356                                           unsigned Insn,
1357                                           uint64_t Address,
1358                                           const void *Decoder) {
1359   unsigned Offset = Insn & 0x1F;
1360   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1361
1362   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1363
1364   Inst.addOperand(MCOperand::createReg(Reg));
1365   Inst.addOperand(MCOperand::createReg(Mips::SP));
1366   Inst.addOperand(MCOperand::createImm(Offset << 2));
1367
1368   return MCDisassembler::Success;
1369 }
1370
1371 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1372                                           unsigned Insn,
1373                                           uint64_t Address,
1374                                           const void *Decoder) {
1375   unsigned Offset = Insn & 0x7F;
1376   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1377
1378   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1379
1380   Inst.addOperand(MCOperand::createReg(Reg));
1381   Inst.addOperand(MCOperand::createReg(Mips::GP));
1382   Inst.addOperand(MCOperand::createImm(Offset << 2));
1383
1384   return MCDisassembler::Success;
1385 }
1386
1387 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1388                                                unsigned Insn,
1389                                                uint64_t Address,
1390                                                const void *Decoder) {
1391   int Offset = SignExtend32<4>(Insn & 0xf);
1392
1393   if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1394       == MCDisassembler::Fail)
1395     return MCDisassembler::Fail;
1396
1397   Inst.addOperand(MCOperand::createReg(Mips::SP));
1398   Inst.addOperand(MCOperand::createImm(Offset << 2));
1399
1400   return MCDisassembler::Success;
1401 }
1402
1403 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
1404                                     unsigned Insn,
1405                                     uint64_t Address,
1406                                     const void *Decoder) {
1407   int Offset = SignExtend32<9>(Insn & 0x1ff);
1408   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1409   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1410
1411   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1412   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1413
1414   Inst.addOperand(MCOperand::createReg(Reg));
1415   Inst.addOperand(MCOperand::createReg(Base));
1416   Inst.addOperand(MCOperand::createImm(Offset));
1417
1418   return MCDisassembler::Success;
1419 }
1420
1421 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1422                                      unsigned Insn,
1423                                      uint64_t Address,
1424                                      const void *Decoder) {
1425   int Offset = SignExtend32<12>(Insn & 0x0fff);
1426   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1427   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1428
1429   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1430   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1431
1432   switch (Inst.getOpcode()) {
1433   case Mips::SWM32_MM:
1434   case Mips::LWM32_MM:
1435     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1436         == MCDisassembler::Fail)
1437       return MCDisassembler::Fail;
1438     Inst.addOperand(MCOperand::createReg(Base));
1439     Inst.addOperand(MCOperand::createImm(Offset));
1440     break;
1441   case Mips::SC_MM:
1442     Inst.addOperand(MCOperand::createReg(Reg));
1443     // fallthrough
1444   default:
1445     Inst.addOperand(MCOperand::createReg(Reg));
1446     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1447       Inst.addOperand(MCOperand::createReg(Reg+1));
1448
1449     Inst.addOperand(MCOperand::createReg(Base));
1450     Inst.addOperand(MCOperand::createImm(Offset));
1451   }
1452
1453   return MCDisassembler::Success;
1454 }
1455
1456 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1457                                      unsigned Insn,
1458                                      uint64_t Address,
1459                                      const void *Decoder) {
1460   int Offset = SignExtend32<16>(Insn & 0xffff);
1461   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1462   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1463
1464   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1465   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1466
1467   Inst.addOperand(MCOperand::createReg(Reg));
1468   Inst.addOperand(MCOperand::createReg(Base));
1469   Inst.addOperand(MCOperand::createImm(Offset));
1470
1471   return MCDisassembler::Success;
1472 }
1473
1474 static DecodeStatus DecodeFMem(MCInst &Inst,
1475                                unsigned Insn,
1476                                uint64_t Address,
1477                                const void *Decoder) {
1478   int Offset = SignExtend32<16>(Insn & 0xffff);
1479   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1480   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1481
1482   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1483   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1484
1485   Inst.addOperand(MCOperand::createReg(Reg));
1486   Inst.addOperand(MCOperand::createReg(Base));
1487   Inst.addOperand(MCOperand::createImm(Offset));
1488
1489   return MCDisassembler::Success;
1490 }
1491
1492 static DecodeStatus DecodeFMem2(MCInst &Inst,
1493                                unsigned Insn,
1494                                uint64_t Address,
1495                                const void *Decoder) {
1496   int Offset = SignExtend32<16>(Insn & 0xffff);
1497   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1498   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1499
1500   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1501   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1502
1503   Inst.addOperand(MCOperand::createReg(Reg));
1504   Inst.addOperand(MCOperand::createReg(Base));
1505   Inst.addOperand(MCOperand::createImm(Offset));
1506
1507   return MCDisassembler::Success;
1508 }
1509
1510 static DecodeStatus DecodeFMem3(MCInst &Inst,
1511                                unsigned Insn,
1512                                uint64_t Address,
1513                                const void *Decoder) {
1514   int Offset = SignExtend32<16>(Insn & 0xffff);
1515   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1516   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1517
1518   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1519   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1520
1521   Inst.addOperand(MCOperand::createReg(Reg));
1522   Inst.addOperand(MCOperand::createReg(Base));
1523   Inst.addOperand(MCOperand::createImm(Offset));
1524
1525   return MCDisassembler::Success;
1526 }
1527
1528 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1529                                     unsigned Insn,
1530                                     uint64_t Address,
1531                                     const void *Decoder) {
1532   int Offset = SignExtend32<11>(Insn & 0x07ff);
1533   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1534   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1535
1536   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1537   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1538
1539   Inst.addOperand(MCOperand::createReg(Reg));
1540   Inst.addOperand(MCOperand::createReg(Base));
1541   Inst.addOperand(MCOperand::createImm(Offset));
1542
1543   return MCDisassembler::Success;
1544 }
1545 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1546                                        unsigned Insn,
1547                                        uint64_t Address,
1548                                        const void *Decoder) {
1549   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1550   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1551   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1552
1553   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1554   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1555
1556   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1557     Inst.addOperand(MCOperand::createReg(Rt));
1558   }
1559
1560   Inst.addOperand(MCOperand::createReg(Rt));
1561   Inst.addOperand(MCOperand::createReg(Base));
1562   Inst.addOperand(MCOperand::createImm(Offset));
1563
1564   return MCDisassembler::Success;
1565 }
1566
1567 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1568                                               unsigned RegNo,
1569                                               uint64_t Address,
1570                                               const void *Decoder) {
1571   // Currently only hardware register 29 is supported.
1572   if (RegNo != 29)
1573     return  MCDisassembler::Fail;
1574   Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1575   return MCDisassembler::Success;
1576 }
1577
1578 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1579                                               unsigned RegNo,
1580                                               uint64_t Address,
1581                                               const void *Decoder) {
1582   if (RegNo > 30 || RegNo %2)
1583     return MCDisassembler::Fail;
1584
1585   ;
1586   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1587   Inst.addOperand(MCOperand::createReg(Reg));
1588   return MCDisassembler::Success;
1589 }
1590
1591 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1592                                                 unsigned RegNo,
1593                                                 uint64_t Address,
1594                                                 const void *Decoder) {
1595   if (RegNo >= 4)
1596     return MCDisassembler::Fail;
1597
1598   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1599   Inst.addOperand(MCOperand::createReg(Reg));
1600   return MCDisassembler::Success;
1601 }
1602
1603 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1604                                                unsigned RegNo,
1605                                                uint64_t Address,
1606                                                const void *Decoder) {
1607   if (RegNo >= 4)
1608     return MCDisassembler::Fail;
1609
1610   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1611   Inst.addOperand(MCOperand::createReg(Reg));
1612   return MCDisassembler::Success;
1613 }
1614
1615 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1616                                                unsigned RegNo,
1617                                                uint64_t Address,
1618                                                const void *Decoder) {
1619   if (RegNo >= 4)
1620     return MCDisassembler::Fail;
1621
1622   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1623   Inst.addOperand(MCOperand::createReg(Reg));
1624   return MCDisassembler::Success;
1625 }
1626
1627 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1628                                                unsigned RegNo,
1629                                                uint64_t Address,
1630                                                const void *Decoder) {
1631   if (RegNo > 31)
1632     return MCDisassembler::Fail;
1633
1634   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1635   Inst.addOperand(MCOperand::createReg(Reg));
1636   return MCDisassembler::Success;
1637 }
1638
1639 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1640                                                unsigned RegNo,
1641                                                uint64_t Address,
1642                                                const void *Decoder) {
1643   if (RegNo > 31)
1644     return MCDisassembler::Fail;
1645
1646   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1647   Inst.addOperand(MCOperand::createReg(Reg));
1648   return MCDisassembler::Success;
1649 }
1650
1651 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1652                                                unsigned RegNo,
1653                                                uint64_t Address,
1654                                                const void *Decoder) {
1655   if (RegNo > 31)
1656     return MCDisassembler::Fail;
1657
1658   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1659   Inst.addOperand(MCOperand::createReg(Reg));
1660   return MCDisassembler::Success;
1661 }
1662
1663 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1664                                                unsigned RegNo,
1665                                                uint64_t Address,
1666                                                const void *Decoder) {
1667   if (RegNo > 31)
1668     return MCDisassembler::Fail;
1669
1670   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1671   Inst.addOperand(MCOperand::createReg(Reg));
1672   return MCDisassembler::Success;
1673 }
1674
1675 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1676                                                unsigned RegNo,
1677                                                uint64_t Address,
1678                                                const void *Decoder) {
1679   if (RegNo > 7)
1680     return MCDisassembler::Fail;
1681
1682   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1683   Inst.addOperand(MCOperand::createReg(Reg));
1684   return MCDisassembler::Success;
1685 }
1686
1687 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
1688                                             unsigned RegNo,
1689                                             uint64_t Address,
1690                                             const void *Decoder) {
1691   if (RegNo > 31)
1692     return MCDisassembler::Fail;
1693
1694   unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
1695   Inst.addOperand(MCOperand::createReg(Reg));
1696   return MCDisassembler::Success;
1697 }
1698
1699 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1700                                             unsigned RegNo,
1701                                             uint64_t Address,
1702                                             const void *Decoder) {
1703   if (RegNo > 31)
1704     return MCDisassembler::Fail;
1705
1706   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1707   Inst.addOperand(MCOperand::createReg(Reg));
1708   return MCDisassembler::Success;
1709 }
1710
1711 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1712                                        unsigned Offset,
1713                                        uint64_t Address,
1714                                        const void *Decoder) {
1715   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1716   Inst.addOperand(MCOperand::createImm(BranchOffset));
1717   return MCDisassembler::Success;
1718 }
1719
1720 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1721                                      unsigned Insn,
1722                                      uint64_t Address,
1723                                      const void *Decoder) {
1724
1725   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1726   Inst.addOperand(MCOperand::createImm(JumpOffset));
1727   return MCDisassembler::Success;
1728 }
1729
1730 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1731                                          unsigned Offset,
1732                                          uint64_t Address,
1733                                          const void *Decoder) {
1734   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1735
1736   Inst.addOperand(MCOperand::createImm(BranchOffset));
1737   return MCDisassembler::Success;
1738 }
1739
1740 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1741                                          unsigned Offset,
1742                                          uint64_t Address,
1743                                          const void *Decoder) {
1744   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1745
1746   Inst.addOperand(MCOperand::createImm(BranchOffset));
1747   return MCDisassembler::Success;
1748 }
1749
1750 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1751                                           unsigned Offset,
1752                                           uint64_t Address,
1753                                           const void *Decoder) {
1754   int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1755   Inst.addOperand(MCOperand::createImm(BranchOffset));
1756   return MCDisassembler::Success;
1757 }
1758
1759 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1760                                            unsigned Offset,
1761                                            uint64_t Address,
1762                                            const void *Decoder) {
1763   int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1764   Inst.addOperand(MCOperand::createImm(BranchOffset));
1765   return MCDisassembler::Success;
1766 }
1767
1768 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1769                                          unsigned Offset,
1770                                          uint64_t Address,
1771                                          const void *Decoder) {
1772   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1773   Inst.addOperand(MCOperand::createImm(BranchOffset));
1774   return MCDisassembler::Success;
1775 }
1776
1777 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1778                                        unsigned Insn,
1779                                        uint64_t Address,
1780                                        const void *Decoder) {
1781   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1782   Inst.addOperand(MCOperand::createImm(JumpOffset));
1783   return MCDisassembler::Success;
1784 }
1785
1786 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1787                                        unsigned Value,
1788                                        uint64_t Address,
1789                                        const void *Decoder) {
1790   if (Value == 0)
1791     Inst.addOperand(MCOperand::createImm(1));
1792   else if (Value == 0x7)
1793     Inst.addOperand(MCOperand::createImm(-1));
1794   else
1795     Inst.addOperand(MCOperand::createImm(Value << 2));
1796   return MCDisassembler::Success;
1797 }
1798
1799 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1800                                     unsigned Value,
1801                                     uint64_t Address,
1802                                     const void *Decoder) {
1803   Inst.addOperand(MCOperand::createImm(Value << 2));
1804   return MCDisassembler::Success;
1805 }
1806
1807 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1808                                   unsigned Value,
1809                                   uint64_t Address,
1810                                   const void *Decoder) {
1811   if (Value == 0x7F)
1812     Inst.addOperand(MCOperand::createImm(-1));
1813   else
1814     Inst.addOperand(MCOperand::createImm(Value));
1815   return MCDisassembler::Success;
1816 }
1817
1818 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
1819                                               unsigned Value,
1820                                               uint64_t Address,
1821                                               const void *Decoder) {
1822   Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
1823   return MCDisassembler::Success;
1824 }
1825
1826 static DecodeStatus DecodeSimm4(MCInst &Inst,
1827                                 unsigned Value,
1828                                 uint64_t Address,
1829                                 const void *Decoder) {
1830   Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
1831   return MCDisassembler::Success;
1832 }
1833
1834 static DecodeStatus DecodeSimm16(MCInst &Inst,
1835                                  unsigned Insn,
1836                                  uint64_t Address,
1837                                  const void *Decoder) {
1838   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
1839   return MCDisassembler::Success;
1840 }
1841
1842 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1843                                  unsigned Insn,
1844                                  uint64_t Address,
1845                                  const void *Decoder) {
1846   // We add one to the immediate field as it was encoded as 'imm - 1'.
1847   Inst.addOperand(MCOperand::createImm(Insn + 1));
1848   return MCDisassembler::Success;
1849 }
1850
1851 static DecodeStatus DecodeInsSize(MCInst &Inst,
1852                                   unsigned Insn,
1853                                   uint64_t Address,
1854                                   const void *Decoder) {
1855   // First we need to grab the pos(lsb) from MCInst.
1856   int Pos = Inst.getOperand(2).getImm();
1857   int Size = (int) Insn - Pos + 1;
1858   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1859   return MCDisassembler::Success;
1860 }
1861
1862 static DecodeStatus DecodeExtSize(MCInst &Inst,
1863                                   unsigned Insn,
1864                                   uint64_t Address,
1865                                   const void *Decoder) {
1866   int Size = (int) Insn  + 1;
1867   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1868   return MCDisassembler::Success;
1869 }
1870
1871 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1872                                      uint64_t Address, const void *Decoder) {
1873   Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1874   return MCDisassembler::Success;
1875 }
1876
1877 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1878                                      uint64_t Address, const void *Decoder) {
1879   Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1880   return MCDisassembler::Success;
1881 }
1882
1883 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1884                                   uint64_t Address, const void *Decoder) {
1885   int32_t DecodedValue;
1886   switch (Insn) {
1887   case 0: DecodedValue = 256; break;
1888   case 1: DecodedValue = 257; break;
1889   case 510: DecodedValue = -258; break;
1890   case 511: DecodedValue = -257; break;
1891   default: DecodedValue = SignExtend32<9>(Insn); break;
1892   }
1893   Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1894   return MCDisassembler::Success;
1895 }
1896
1897 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1898                                     uint64_t Address, const void *Decoder) {
1899   // Insn must be >= 0, since it is unsigned that condition is always true.
1900   assert(Insn < 16);
1901   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1902                              255, 32768, 65535};
1903   Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1904   return MCDisassembler::Success;
1905 }
1906
1907 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1908                                     uint64_t Address, const void *Decoder) {
1909   Inst.addOperand(MCOperand::createImm(Insn << 2));
1910   return MCDisassembler::Success;
1911 }
1912
1913 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1914                                          unsigned Insn,
1915                                          uint64_t Address,
1916                                          const void *Decoder) {
1917   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1918                      Mips::S6, Mips::FP};
1919   unsigned RegNum;
1920
1921   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1922   // Empty register lists are not allowed.
1923   if (RegLst == 0)
1924     return MCDisassembler::Fail;
1925
1926   RegNum = RegLst & 0xf;
1927   for (unsigned i = 0; i < RegNum; i++)
1928     Inst.addOperand(MCOperand::createReg(Regs[i]));
1929
1930   if (RegLst & 0x10)
1931     Inst.addOperand(MCOperand::createReg(Mips::RA));
1932
1933   return MCDisassembler::Success;
1934 }
1935
1936 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1937                                            uint64_t Address,
1938                                            const void *Decoder) {
1939   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1940   unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1941   unsigned RegNum = RegLst & 0x3;
1942
1943   for (unsigned i = 0; i <= RegNum; i++)
1944     Inst.addOperand(MCOperand::createReg(Regs[i]));
1945
1946   Inst.addOperand(MCOperand::createReg(Mips::RA));
1947
1948   return MCDisassembler::Success;
1949 }
1950
1951 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
1952                                        uint64_t Address, const void *Decoder) {
1953
1954   unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1955
1956   switch (RegPair) {
1957   default:
1958     return MCDisassembler::Fail;
1959   case 0:
1960     Inst.addOperand(MCOperand::createReg(Mips::A1));
1961     Inst.addOperand(MCOperand::createReg(Mips::A2));
1962     break;
1963   case 1:
1964     Inst.addOperand(MCOperand::createReg(Mips::A1));
1965     Inst.addOperand(MCOperand::createReg(Mips::A3));
1966     break;
1967   case 2:
1968     Inst.addOperand(MCOperand::createReg(Mips::A2));
1969     Inst.addOperand(MCOperand::createReg(Mips::A3));
1970     break;
1971   case 3:
1972     Inst.addOperand(MCOperand::createReg(Mips::A0));
1973     Inst.addOperand(MCOperand::createReg(Mips::S5));
1974     break;
1975   case 4:
1976     Inst.addOperand(MCOperand::createReg(Mips::A0));
1977     Inst.addOperand(MCOperand::createReg(Mips::S6));
1978     break;
1979   case 5:
1980     Inst.addOperand(MCOperand::createReg(Mips::A0));
1981     Inst.addOperand(MCOperand::createReg(Mips::A1));
1982     break;
1983   case 6:
1984     Inst.addOperand(MCOperand::createReg(Mips::A0));
1985     Inst.addOperand(MCOperand::createReg(Mips::A2));
1986     break;
1987   case 7:
1988     Inst.addOperand(MCOperand::createReg(Mips::A0));
1989     Inst.addOperand(MCOperand::createReg(Mips::A3));
1990     break;
1991   }
1992
1993   return MCDisassembler::Success;
1994 }
1995
1996 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1997                                      uint64_t Address, const void *Decoder) {
1998   Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
1999   return MCDisassembler::Success;
2000 }