1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/TargetRegistry.h"
28 #define DEBUG_TYPE "mips-disassembler"
30 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 /// MipsDisassemblerBase - a disasembler class for Mips.
35 class MipsDisassemblerBase : public MCDisassembler {
37 /// Constructor - Initializes the disassembler.
39 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
41 MCDisassembler(STI, Ctx),
42 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
44 virtual ~MipsDisassemblerBase() {}
46 bool isN64() const { return IsN64; }
54 /// MipsDisassembler - a disasembler class for Mips32.
55 class MipsDisassembler : public MipsDisassemblerBase {
58 /// Constructor - Initializes the disassembler.
60 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
62 MipsDisassemblerBase(STI, Ctx, bigEndian) {
63 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
66 /// getInstruction - See MCDisassembler.
67 virtual DecodeStatus getInstruction(MCInst &instr,
69 const MemoryObject ®ion,
72 raw_ostream &cStream) const;
76 /// Mips64Disassembler - a disasembler class for Mips64.
77 class Mips64Disassembler : public MipsDisassemblerBase {
79 /// Constructor - Initializes the disassembler.
81 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
83 MipsDisassemblerBase(STI, Ctx, bigEndian) {}
85 /// getInstruction - See MCDisassembler.
86 virtual DecodeStatus getInstruction(MCInst &instr,
88 const MemoryObject ®ion,
91 raw_ostream &cStream) const;
94 } // end anonymous namespace
96 // Forward declare these because the autogenerated code will reference them.
97 // Definitions are further down.
98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
101 const void *Decoder);
103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
106 const void *Decoder);
108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
111 const void *Decoder);
113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
116 const void *Decoder);
118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
121 const void *Decoder);
123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
126 const void *Decoder);
128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
131 const void *Decoder);
133 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
136 const void *Decoder);
138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
141 const void *Decoder);
143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
146 const void *Decoder);
148 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
151 const void *Decoder);
153 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
156 const void *Decoder);
158 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
161 const void *Decoder);
163 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
166 const void *Decoder);
168 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
171 const void *Decoder);
173 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
176 const void *Decoder);
178 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
181 const void *Decoder);
183 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
186 const void *Decoder);
188 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
191 const void *Decoder);
193 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
196 const void *Decoder);
198 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
201 const void *Decoder);
203 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
206 const void *Decoder);
208 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
209 // shifted left by 1 bit.
210 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
213 const void *Decoder);
215 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
216 // shifted left by 1 bit.
217 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
220 const void *Decoder);
222 static DecodeStatus DecodeMem(MCInst &Inst,
225 const void *Decoder);
227 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
228 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
233 const void *Decoder);
235 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
238 const void *Decoder);
240 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
242 const void *Decoder);
244 static DecodeStatus DecodeSimm16(MCInst &Inst,
247 const void *Decoder);
249 // Decode the immediate field of an LSA instruction which
251 static DecodeStatus DecodeLSAImm(MCInst &Inst,
254 const void *Decoder);
256 static DecodeStatus DecodeInsSize(MCInst &Inst,
259 const void *Decoder);
261 static DecodeStatus DecodeExtSize(MCInst &Inst,
264 const void *Decoder);
266 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
268 template <typename InsnType>
269 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
270 const void *Decoder);
272 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
276 static MCDisassembler *createMipsDisassembler(
278 const MCSubtargetInfo &STI,
280 return new MipsDisassembler(STI, Ctx, true);
283 static MCDisassembler *createMipselDisassembler(
285 const MCSubtargetInfo &STI,
287 return new MipsDisassembler(STI, Ctx, false);
290 static MCDisassembler *createMips64Disassembler(
292 const MCSubtargetInfo &STI,
294 return new Mips64Disassembler(STI, Ctx, true);
297 static MCDisassembler *createMips64elDisassembler(
299 const MCSubtargetInfo &STI,
301 return new Mips64Disassembler(STI, Ctx, false);
304 extern "C" void LLVMInitializeMipsDisassembler() {
305 // Register the disassembler.
306 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
307 createMipsDisassembler);
308 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
309 createMipselDisassembler);
310 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
311 createMips64Disassembler);
312 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
313 createMips64elDisassembler);
316 #include "MipsGenDisassemblerTables.inc"
318 template <typename InsnType>
319 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
320 const void *Decoder) {
321 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
322 // The size of the n field depends on the element size
323 // The register class also depends on this.
324 InsnType tmp = fieldFromInstruction(insn, 17, 5);
326 DecodeFN RegDecoder = nullptr;
327 if ((tmp & 0x18) == 0x00) { // INSVE_B
329 RegDecoder = DecodeMSA128BRegisterClass;
330 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
332 RegDecoder = DecodeMSA128HRegisterClass;
333 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
335 RegDecoder = DecodeMSA128WRegisterClass;
336 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
338 RegDecoder = DecodeMSA128DRegisterClass;
340 llvm_unreachable("Invalid encoding");
342 assert(NSize != 0 && RegDecoder != nullptr);
345 tmp = fieldFromInstruction(insn, 6, 5);
346 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
347 return MCDisassembler::Fail;
349 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
350 return MCDisassembler::Fail;
352 tmp = fieldFromInstruction(insn, 16, NSize);
353 MI.addOperand(MCOperand::CreateImm(tmp));
355 tmp = fieldFromInstruction(insn, 11, 5);
356 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
357 return MCDisassembler::Fail;
359 MI.addOperand(MCOperand::CreateImm(0));
361 return MCDisassembler::Success;
364 /// readInstruction - read four bytes from the MemoryObject
365 /// and return 32 bit word sorted according to the given endianess
366 static DecodeStatus readInstruction32(const MemoryObject ®ion,
374 // We want to read exactly 4 Bytes of data.
375 if (region.readBytes(address, 4, Bytes) == -1) {
377 return MCDisassembler::Fail;
381 // Encoded as a big-endian 32-bit word in the stream.
382 insn = (Bytes[3] << 0) |
388 // Encoded as a small-endian 32-bit word in the stream.
389 // Little-endian byte ordering:
390 // mips32r2: 4 | 3 | 2 | 1
391 // microMIPS: 2 | 1 | 4 | 3
393 insn = (Bytes[2] << 0) |
398 insn = (Bytes[0] << 0) |
405 return MCDisassembler::Success;
409 MipsDisassembler::getInstruction(MCInst &instr,
411 const MemoryObject &Region,
413 raw_ostream &vStream,
414 raw_ostream &cStream) const {
417 DecodeStatus Result = readInstruction32(Region, Address, Size,
418 Insn, isBigEndian, IsMicroMips);
419 if (Result == MCDisassembler::Fail)
420 return MCDisassembler::Fail;
423 // Calling the auto-generated decoder function.
424 Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
426 if (Result != MCDisassembler::Fail) {
430 return MCDisassembler::Fail;
433 // Calling the auto-generated decoder function.
434 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
436 if (Result != MCDisassembler::Fail) {
441 return MCDisassembler::Fail;
445 Mips64Disassembler::getInstruction(MCInst &instr,
447 const MemoryObject &Region,
449 raw_ostream &vStream,
450 raw_ostream &cStream) const {
453 DecodeStatus Result = readInstruction32(Region, Address, Size,
454 Insn, isBigEndian, false);
455 if (Result == MCDisassembler::Fail)
456 return MCDisassembler::Fail;
458 // Calling the auto-generated decoder function.
459 Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
461 if (Result != MCDisassembler::Fail) {
465 // If we fail to decode in Mips64 decoder space we can try in Mips32
466 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
468 if (Result != MCDisassembler::Fail) {
473 return MCDisassembler::Fail;
476 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
477 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
478 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
479 return *(RegInfo->getRegClass(RC).begin() + RegNo);
482 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
485 const void *Decoder) {
487 return MCDisassembler::Fail;
491 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
494 const void *Decoder) {
497 return MCDisassembler::Fail;
499 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
500 Inst.addOperand(MCOperand::CreateReg(Reg));
501 return MCDisassembler::Success;
504 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
507 const void *Decoder) {
509 return MCDisassembler::Fail;
510 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
511 Inst.addOperand(MCOperand::CreateReg(Reg));
512 return MCDisassembler::Success;
515 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
518 const void *Decoder) {
519 if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
520 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
522 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
525 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
528 const void *Decoder) {
529 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
532 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
535 const void *Decoder) {
537 return MCDisassembler::Fail;
539 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
540 Inst.addOperand(MCOperand::CreateReg(Reg));
541 return MCDisassembler::Success;
544 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
547 const void *Decoder) {
549 return MCDisassembler::Fail;
551 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
552 Inst.addOperand(MCOperand::CreateReg(Reg));
553 return MCDisassembler::Success;
556 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
559 const void *Decoder) {
561 return MCDisassembler::Fail;
563 unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
564 Inst.addOperand(MCOperand::CreateReg(Reg));
565 return MCDisassembler::Success;
568 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
571 const void *Decoder) {
573 return MCDisassembler::Fail;
574 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
575 Inst.addOperand(MCOperand::CreateReg(Reg));
576 return MCDisassembler::Success;
579 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
582 const void *Decoder) {
584 return MCDisassembler::Fail;
585 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
586 Inst.addOperand(MCOperand::CreateReg(Reg));
587 return MCDisassembler::Success;
590 static DecodeStatus DecodeMem(MCInst &Inst,
593 const void *Decoder) {
594 int Offset = SignExtend32<16>(Insn & 0xffff);
595 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
596 unsigned Base = fieldFromInstruction(Insn, 21, 5);
598 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
599 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
601 if(Inst.getOpcode() == Mips::SC){
602 Inst.addOperand(MCOperand::CreateReg(Reg));
605 Inst.addOperand(MCOperand::CreateReg(Reg));
606 Inst.addOperand(MCOperand::CreateReg(Base));
607 Inst.addOperand(MCOperand::CreateImm(Offset));
609 return MCDisassembler::Success;
612 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
613 uint64_t Address, const void *Decoder) {
614 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
615 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
616 unsigned Base = fieldFromInstruction(Insn, 11, 5);
618 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
619 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
621 Inst.addOperand(MCOperand::CreateReg(Reg));
622 Inst.addOperand(MCOperand::CreateReg(Base));
624 // The immediate field of an LD/ST instruction is scaled which means it must
625 // be multiplied (when decoding) by the size (in bytes) of the instructions'
631 switch(Inst.getOpcode())
634 assert (0 && "Unexpected instruction");
635 return MCDisassembler::Fail;
639 Inst.addOperand(MCOperand::CreateImm(Offset));
643 Inst.addOperand(MCOperand::CreateImm(Offset << 1));
647 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
651 Inst.addOperand(MCOperand::CreateImm(Offset << 3));
655 return MCDisassembler::Success;
658 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
661 const void *Decoder) {
662 int Offset = SignExtend32<12>(Insn & 0x0fff);
663 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
664 unsigned Base = fieldFromInstruction(Insn, 16, 5);
666 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
667 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
669 if (Inst.getOpcode() == Mips::SC_MM)
670 Inst.addOperand(MCOperand::CreateReg(Reg));
672 Inst.addOperand(MCOperand::CreateReg(Reg));
673 Inst.addOperand(MCOperand::CreateReg(Base));
674 Inst.addOperand(MCOperand::CreateImm(Offset));
676 return MCDisassembler::Success;
679 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
682 const void *Decoder) {
683 int Offset = SignExtend32<16>(Insn & 0xffff);
684 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
685 unsigned Base = fieldFromInstruction(Insn, 16, 5);
687 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
688 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
690 Inst.addOperand(MCOperand::CreateReg(Reg));
691 Inst.addOperand(MCOperand::CreateReg(Base));
692 Inst.addOperand(MCOperand::CreateImm(Offset));
694 return MCDisassembler::Success;
697 static DecodeStatus DecodeFMem(MCInst &Inst,
700 const void *Decoder) {
701 int Offset = SignExtend32<16>(Insn & 0xffff);
702 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
703 unsigned Base = fieldFromInstruction(Insn, 21, 5);
705 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
706 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
708 Inst.addOperand(MCOperand::CreateReg(Reg));
709 Inst.addOperand(MCOperand::CreateReg(Base));
710 Inst.addOperand(MCOperand::CreateImm(Offset));
712 return MCDisassembler::Success;
716 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
719 const void *Decoder) {
720 // Currently only hardware register 29 is supported.
722 return MCDisassembler::Fail;
723 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
724 return MCDisassembler::Success;
727 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
730 const void *Decoder) {
731 if (RegNo > 30 || RegNo %2)
732 return MCDisassembler::Fail;
735 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
736 Inst.addOperand(MCOperand::CreateReg(Reg));
737 return MCDisassembler::Success;
740 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
743 const void *Decoder) {
745 return MCDisassembler::Fail;
747 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
748 Inst.addOperand(MCOperand::CreateReg(Reg));
749 return MCDisassembler::Success;
752 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
755 const void *Decoder) {
757 return MCDisassembler::Fail;
759 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
760 Inst.addOperand(MCOperand::CreateReg(Reg));
761 return MCDisassembler::Success;
764 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
767 const void *Decoder) {
769 return MCDisassembler::Fail;
771 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
772 Inst.addOperand(MCOperand::CreateReg(Reg));
773 return MCDisassembler::Success;
776 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
779 const void *Decoder) {
781 return MCDisassembler::Fail;
783 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
784 Inst.addOperand(MCOperand::CreateReg(Reg));
785 return MCDisassembler::Success;
788 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
791 const void *Decoder) {
793 return MCDisassembler::Fail;
795 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
796 Inst.addOperand(MCOperand::CreateReg(Reg));
797 return MCDisassembler::Success;
800 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
803 const void *Decoder) {
805 return MCDisassembler::Fail;
807 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
808 Inst.addOperand(MCOperand::CreateReg(Reg));
809 return MCDisassembler::Success;
812 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
815 const void *Decoder) {
817 return MCDisassembler::Fail;
819 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
820 Inst.addOperand(MCOperand::CreateReg(Reg));
821 return MCDisassembler::Success;
824 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
827 const void *Decoder) {
829 return MCDisassembler::Fail;
831 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
832 Inst.addOperand(MCOperand::CreateReg(Reg));
833 return MCDisassembler::Success;
836 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
839 const void *Decoder) {
840 unsigned BranchOffset = Offset & 0xffff;
841 BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
842 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
843 return MCDisassembler::Success;
846 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
849 const void *Decoder) {
851 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
852 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
853 return MCDisassembler::Success;
856 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
859 const void *Decoder) {
860 unsigned BranchOffset = Offset & 0xffff;
861 BranchOffset = SignExtend32<18>(BranchOffset << 1);
862 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
863 return MCDisassembler::Success;
866 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
869 const void *Decoder) {
870 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
871 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
872 return MCDisassembler::Success;
875 static DecodeStatus DecodeSimm16(MCInst &Inst,
878 const void *Decoder) {
879 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
880 return MCDisassembler::Success;
883 static DecodeStatus DecodeLSAImm(MCInst &Inst,
886 const void *Decoder) {
887 // We add one to the immediate field as it was encoded as 'imm - 1'.
888 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
889 return MCDisassembler::Success;
892 static DecodeStatus DecodeInsSize(MCInst &Inst,
895 const void *Decoder) {
896 // First we need to grab the pos(lsb) from MCInst.
897 int Pos = Inst.getOperand(2).getImm();
898 int Size = (int) Insn - Pos + 1;
899 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
900 return MCDisassembler::Success;
903 static DecodeStatus DecodeExtSize(MCInst &Inst,
906 const void *Decoder) {
907 int Size = (int) Insn + 1;
908 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
909 return MCDisassembler::Success;