1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/TargetRegistry.h"
28 #define DEBUG_TYPE "mips-disassembler"
30 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 /// MipsDisassemblerBase - a disasembler class for Mips.
35 class MipsDisassemblerBase : public MCDisassembler {
37 /// Constructor - Initializes the disassembler.
39 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
41 MCDisassembler(STI, Ctx),
42 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
44 virtual ~MipsDisassemblerBase() {}
46 bool isN64() const { return IsN64; }
54 /// MipsDisassembler - a disasembler class for Mips32.
55 class MipsDisassembler : public MipsDisassemblerBase {
58 /// Constructor - Initializes the disassembler.
60 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
61 : MipsDisassemblerBase(STI, Ctx, bigEndian) {
62 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
65 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
66 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
67 bool hasMips32r6() const {
68 return STI.getFeatureBits() & Mips::FeatureMips32r6;
71 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
73 bool hasCOP3() const {
74 // Only present in MIPS-I and MIPS-II
75 return !hasMips32() && !hasMips3();
78 /// getInstruction - See MCDisassembler.
79 DecodeStatus getInstruction(MCInst &instr,
81 const MemoryObject ®ion,
84 raw_ostream &cStream) const override;
88 /// Mips64Disassembler - a disasembler class for Mips64.
89 class Mips64Disassembler : public MipsDisassemblerBase {
91 /// Constructor - Initializes the disassembler.
93 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
95 MipsDisassemblerBase(STI, Ctx, bigEndian) {}
97 /// getInstruction - See MCDisassembler.
98 DecodeStatus getInstruction(MCInst &instr,
100 const MemoryObject ®ion,
102 raw_ostream &vStream,
103 raw_ostream &cStream) const override;
106 } // end anonymous namespace
108 // Forward declare these because the autogenerated code will reference them.
109 // Definitions are further down.
110 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
113 const void *Decoder);
115 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
118 const void *Decoder);
120 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
123 const void *Decoder);
125 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
128 const void *Decoder);
130 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
133 const void *Decoder);
135 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
138 const void *Decoder);
140 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
143 const void *Decoder);
145 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
148 const void *Decoder);
150 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
153 const void *Decoder);
155 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
158 const void *Decoder);
160 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
162 const void *Decoder);
164 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
167 const void *Decoder);
169 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
172 const void *Decoder);
174 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
177 const void *Decoder);
179 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
182 const void *Decoder);
184 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
187 const void *Decoder);
189 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
192 const void *Decoder);
194 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
197 const void *Decoder);
199 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
202 const void *Decoder);
204 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
207 const void *Decoder);
209 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
212 const void *Decoder);
214 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
217 const void *Decoder);
219 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
222 const void *Decoder);
224 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
227 const void *Decoder);
229 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
232 const void *Decoder);
234 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
237 const void *Decoder);
239 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
240 // shifted left by 1 bit.
241 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
244 const void *Decoder);
246 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
247 // shifted left by 1 bit.
248 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
251 const void *Decoder);
253 static DecodeStatus DecodeMem(MCInst &Inst,
256 const void *Decoder);
258 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
259 uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
264 const void *Decoder);
266 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
269 const void *Decoder);
271 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
273 const void *Decoder);
275 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
278 const void *Decoder);
280 static DecodeStatus DecodeSimm16(MCInst &Inst,
283 const void *Decoder);
285 // Decode the immediate field of an LSA instruction which
287 static DecodeStatus DecodeLSAImm(MCInst &Inst,
290 const void *Decoder);
292 static DecodeStatus DecodeInsSize(MCInst &Inst,
295 const void *Decoder);
297 static DecodeStatus DecodeExtSize(MCInst &Inst,
300 const void *Decoder);
302 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
306 uint64_t Address, const void *Decoder);
308 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
310 template <typename InsnType>
311 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
312 const void *Decoder);
314 template <typename InsnType>
316 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
317 const void *Decoder);
319 template <typename InsnType>
321 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
322 const void *Decoder);
324 template <typename InsnType>
326 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
327 const void *Decoder);
329 template <typename InsnType>
331 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
332 const void *Decoder);
334 template <typename InsnType>
336 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
337 const void *Decoder);
339 template <typename InsnType>
341 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
342 const void *Decoder);
345 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
349 static MCDisassembler *createMipsDisassembler(
351 const MCSubtargetInfo &STI,
353 return new MipsDisassembler(STI, Ctx, true);
356 static MCDisassembler *createMipselDisassembler(
358 const MCSubtargetInfo &STI,
360 return new MipsDisassembler(STI, Ctx, false);
363 static MCDisassembler *createMips64Disassembler(
365 const MCSubtargetInfo &STI,
367 return new Mips64Disassembler(STI, Ctx, true);
370 static MCDisassembler *createMips64elDisassembler(
372 const MCSubtargetInfo &STI,
374 return new Mips64Disassembler(STI, Ctx, false);
377 extern "C" void LLVMInitializeMipsDisassembler() {
378 // Register the disassembler.
379 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
380 createMipsDisassembler);
381 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
382 createMipselDisassembler);
383 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
384 createMips64Disassembler);
385 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
386 createMips64elDisassembler);
389 #include "MipsGenDisassemblerTables.inc"
391 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
392 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
393 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
394 return *(RegInfo->getRegClass(RC).begin() + RegNo);
397 template <typename InsnType>
398 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
399 const void *Decoder) {
400 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
401 // The size of the n field depends on the element size
402 // The register class also depends on this.
403 InsnType tmp = fieldFromInstruction(insn, 17, 5);
405 DecodeFN RegDecoder = nullptr;
406 if ((tmp & 0x18) == 0x00) { // INSVE_B
408 RegDecoder = DecodeMSA128BRegisterClass;
409 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
411 RegDecoder = DecodeMSA128HRegisterClass;
412 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
414 RegDecoder = DecodeMSA128WRegisterClass;
415 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
417 RegDecoder = DecodeMSA128DRegisterClass;
419 llvm_unreachable("Invalid encoding");
421 assert(NSize != 0 && RegDecoder != nullptr);
424 tmp = fieldFromInstruction(insn, 6, 5);
425 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
426 return MCDisassembler::Fail;
428 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
429 return MCDisassembler::Fail;
431 tmp = fieldFromInstruction(insn, 16, NSize);
432 MI.addOperand(MCOperand::CreateImm(tmp));
434 tmp = fieldFromInstruction(insn, 11, 5);
435 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
436 return MCDisassembler::Fail;
438 MI.addOperand(MCOperand::CreateImm(0));
440 return MCDisassembler::Success;
443 template <typename InsnType>
444 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
446 const void *Decoder) {
447 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
448 // (otherwise we would have matched the ADDI instruction from the earlier
452 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
454 // BEQZALC if rs == 0 && rt != 0
455 // BEQC if rs < rt && rs != 0
457 InsnType Rs = fieldFromInstruction(insn, 21, 5);
458 InsnType Rt = fieldFromInstruction(insn, 16, 5);
459 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
463 MI.setOpcode(Mips::BOVC);
465 } else if (Rs != 0 && Rs < Rt) {
466 MI.setOpcode(Mips::BEQC);
469 MI.setOpcode(Mips::BEQZALC);
472 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
475 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
477 MI.addOperand(MCOperand::CreateImm(Imm));
479 return MCDisassembler::Success;
482 template <typename InsnType>
483 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
485 const void *Decoder) {
486 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
487 // (otherwise we would have matched the ADDI instruction from the earlier
491 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
493 // BNEZALC if rs == 0 && rt != 0
494 // BNEC if rs < rt && rs != 0
496 InsnType Rs = fieldFromInstruction(insn, 21, 5);
497 InsnType Rt = fieldFromInstruction(insn, 16, 5);
498 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
502 MI.setOpcode(Mips::BNVC);
504 } else if (Rs != 0 && Rs < Rt) {
505 MI.setOpcode(Mips::BNEC);
508 MI.setOpcode(Mips::BNEZALC);
511 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
514 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
516 MI.addOperand(MCOperand::CreateImm(Imm));
518 return MCDisassembler::Success;
521 template <typename InsnType>
522 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
524 const void *Decoder) {
525 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
526 // (otherwise we would have matched the BLEZL instruction from the earlier
530 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
531 // Invalid if rs == 0
532 // BLEZC if rs == 0 && rt != 0
533 // BGEZC if rs == rt && rt != 0
534 // BGEC if rs != rt && rs != 0 && rt != 0
536 InsnType Rs = fieldFromInstruction(insn, 21, 5);
537 InsnType Rt = fieldFromInstruction(insn, 16, 5);
538 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
542 return MCDisassembler::Fail;
544 MI.setOpcode(Mips::BLEZC);
546 MI.setOpcode(Mips::BGEZC);
549 MI.setOpcode(Mips::BGEC);
553 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
556 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
559 MI.addOperand(MCOperand::CreateImm(Imm));
561 return MCDisassembler::Success;
564 template <typename InsnType>
565 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
567 const void *Decoder) {
568 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
569 // (otherwise we would have matched the BGTZL instruction from the earlier
573 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
574 // Invalid if rs == 0
575 // BGTZC if rs == 0 && rt != 0
576 // BLTZC if rs == rt && rt != 0
577 // BLTC if rs != rt && rs != 0 && rt != 0
579 InsnType Rs = fieldFromInstruction(insn, 21, 5);
580 InsnType Rt = fieldFromInstruction(insn, 16, 5);
581 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
584 return MCDisassembler::Fail;
586 MI.setOpcode(Mips::BGTZC);
588 MI.setOpcode(Mips::BLTZC);
590 return MCDisassembler::Fail; // FIXME: BLTC is not implemented yet.
592 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
595 MI.addOperand(MCOperand::CreateImm(Imm));
597 return MCDisassembler::Success;
600 template <typename InsnType>
601 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
603 const void *Decoder) {
604 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
605 // (otherwise we would have matched the BGTZ instruction from the earlier
609 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
611 // BGTZALC if rs == 0 && rt != 0
612 // BLTZALC if rs != 0 && rs == rt
613 // BLTUC if rs != 0 && rs != rt
615 InsnType Rs = fieldFromInstruction(insn, 21, 5);
616 InsnType Rt = fieldFromInstruction(insn, 16, 5);
617 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
622 MI.setOpcode(Mips::BGTZ);
624 } else if (Rs == 0) {
625 MI.setOpcode(Mips::BGTZALC);
627 } else if (Rs == Rt) {
628 MI.setOpcode(Mips::BLTZALC);
631 return MCDisassembler::Fail; // BLTUC not implemented yet
634 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
638 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
641 MI.addOperand(MCOperand::CreateImm(Imm));
643 return MCDisassembler::Success;
646 template <typename InsnType>
647 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
649 const void *Decoder) {
650 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
651 // (otherwise we would have matched the BLEZL instruction from the earlier
655 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
656 // Invalid if rs == 0
657 // BLEZALC if rs == 0 && rt != 0
658 // BGEZALC if rs == rt && rt != 0
659 // BGEUC if rs != rt && rs != 0 && rt != 0
661 InsnType Rs = fieldFromInstruction(insn, 21, 5);
662 InsnType Rt = fieldFromInstruction(insn, 16, 5);
663 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
667 return MCDisassembler::Fail;
669 MI.setOpcode(Mips::BLEZALC);
671 MI.setOpcode(Mips::BGEZALC);
674 MI.setOpcode(Mips::BGEUC);
678 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
680 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
683 MI.addOperand(MCOperand::CreateImm(Imm));
685 return MCDisassembler::Success;
688 /// readInstruction - read four bytes from the MemoryObject
689 /// and return 32 bit word sorted according to the given endianess
690 static DecodeStatus readInstruction32(const MemoryObject ®ion,
698 // We want to read exactly 4 Bytes of data.
699 if (region.readBytes(address, 4, Bytes) == -1) {
701 return MCDisassembler::Fail;
705 // Encoded as a big-endian 32-bit word in the stream.
706 insn = (Bytes[3] << 0) |
712 // Encoded as a small-endian 32-bit word in the stream.
713 // Little-endian byte ordering:
714 // mips32r2: 4 | 3 | 2 | 1
715 // microMIPS: 2 | 1 | 4 | 3
717 insn = (Bytes[2] << 0) |
722 insn = (Bytes[0] << 0) |
729 return MCDisassembler::Success;
733 MipsDisassembler::getInstruction(MCInst &instr,
735 const MemoryObject &Region,
737 raw_ostream &vStream,
738 raw_ostream &cStream) const {
741 DecodeStatus Result = readInstruction32(Region, Address, Size,
742 Insn, isBigEndian, IsMicroMips);
743 if (Result == MCDisassembler::Fail)
744 return MCDisassembler::Fail;
747 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n");
748 // Calling the auto-generated decoder function.
749 Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
751 if (Result != MCDisassembler::Fail) {
755 return MCDisassembler::Fail;
759 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
761 decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, this, STI);
762 if (Result != MCDisassembler::Fail) {
768 if (hasMips32r6() && isGP64()) {
769 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
770 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
772 if (Result != MCDisassembler::Fail) {
779 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
780 Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
782 if (Result != MCDisassembler::Fail) {
788 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
789 // Calling the auto-generated decoder function.
790 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
792 if (Result != MCDisassembler::Fail) {
797 return MCDisassembler::Fail;
801 Mips64Disassembler::getInstruction(MCInst &instr,
803 const MemoryObject &Region,
805 raw_ostream &vStream,
806 raw_ostream &cStream) const {
809 DecodeStatus Result = readInstruction32(Region, Address, Size,
810 Insn, isBigEndian, false);
811 if (Result == MCDisassembler::Fail)
812 return MCDisassembler::Fail;
814 // Calling the auto-generated decoder function.
815 Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
817 if (Result != MCDisassembler::Fail) {
821 // If we fail to decode in Mips64 decoder space we can try in Mips32
822 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
824 if (Result != MCDisassembler::Fail) {
829 return MCDisassembler::Fail;
832 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
835 const void *Decoder) {
837 return MCDisassembler::Fail;
841 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
844 const void *Decoder) {
847 return MCDisassembler::Fail;
849 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
850 Inst.addOperand(MCOperand::CreateReg(Reg));
851 return MCDisassembler::Success;
854 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
857 const void *Decoder) {
859 return MCDisassembler::Fail;
860 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
861 Inst.addOperand(MCOperand::CreateReg(Reg));
862 return MCDisassembler::Success;
865 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
868 const void *Decoder) {
869 if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
870 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
872 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
875 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
878 const void *Decoder) {
879 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
882 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
885 const void *Decoder) {
887 return MCDisassembler::Fail;
889 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
890 Inst.addOperand(MCOperand::CreateReg(Reg));
891 return MCDisassembler::Success;
894 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
897 const void *Decoder) {
899 return MCDisassembler::Fail;
901 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
902 Inst.addOperand(MCOperand::CreateReg(Reg));
903 return MCDisassembler::Success;
906 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
909 const void *Decoder) {
911 return MCDisassembler::Fail;
913 unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
914 Inst.addOperand(MCOperand::CreateReg(Reg));
915 return MCDisassembler::Success;
918 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
921 const void *Decoder) {
923 return MCDisassembler::Fail;
924 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
925 Inst.addOperand(MCOperand::CreateReg(Reg));
926 return MCDisassembler::Success;
929 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
932 const void *Decoder) {
934 return MCDisassembler::Fail;
935 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
936 Inst.addOperand(MCOperand::CreateReg(Reg));
937 return MCDisassembler::Success;
940 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
942 const void *Decoder) {
944 return MCDisassembler::Fail;
946 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
947 Inst.addOperand(MCOperand::CreateReg(Reg));
948 return MCDisassembler::Success;
951 static DecodeStatus DecodeMem(MCInst &Inst,
954 const void *Decoder) {
955 int Offset = SignExtend32<16>(Insn & 0xffff);
956 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
957 unsigned Base = fieldFromInstruction(Insn, 21, 5);
959 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
960 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
962 if(Inst.getOpcode() == Mips::SC){
963 Inst.addOperand(MCOperand::CreateReg(Reg));
966 Inst.addOperand(MCOperand::CreateReg(Reg));
967 Inst.addOperand(MCOperand::CreateReg(Base));
968 Inst.addOperand(MCOperand::CreateImm(Offset));
970 return MCDisassembler::Success;
973 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
974 uint64_t Address, const void *Decoder) {
975 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
976 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
977 unsigned Base = fieldFromInstruction(Insn, 11, 5);
979 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
980 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
982 Inst.addOperand(MCOperand::CreateReg(Reg));
983 Inst.addOperand(MCOperand::CreateReg(Base));
985 // The immediate field of an LD/ST instruction is scaled which means it must
986 // be multiplied (when decoding) by the size (in bytes) of the instructions'
992 switch(Inst.getOpcode())
995 assert (0 && "Unexpected instruction");
996 return MCDisassembler::Fail;
1000 Inst.addOperand(MCOperand::CreateImm(Offset));
1004 Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1008 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1012 Inst.addOperand(MCOperand::CreateImm(Offset << 3));
1016 return MCDisassembler::Success;
1019 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1022 const void *Decoder) {
1023 int Offset = SignExtend32<12>(Insn & 0x0fff);
1024 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1025 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1027 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1028 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1030 if (Inst.getOpcode() == Mips::SC_MM)
1031 Inst.addOperand(MCOperand::CreateReg(Reg));
1033 Inst.addOperand(MCOperand::CreateReg(Reg));
1034 Inst.addOperand(MCOperand::CreateReg(Base));
1035 Inst.addOperand(MCOperand::CreateImm(Offset));
1037 return MCDisassembler::Success;
1040 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1043 const void *Decoder) {
1044 int Offset = SignExtend32<16>(Insn & 0xffff);
1045 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1046 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1048 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1049 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1051 Inst.addOperand(MCOperand::CreateReg(Reg));
1052 Inst.addOperand(MCOperand::CreateReg(Base));
1053 Inst.addOperand(MCOperand::CreateImm(Offset));
1055 return MCDisassembler::Success;
1058 static DecodeStatus DecodeFMem(MCInst &Inst,
1061 const void *Decoder) {
1062 int Offset = SignExtend32<16>(Insn & 0xffff);
1063 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1064 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1066 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1067 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1069 Inst.addOperand(MCOperand::CreateReg(Reg));
1070 Inst.addOperand(MCOperand::CreateReg(Base));
1071 Inst.addOperand(MCOperand::CreateImm(Offset));
1073 return MCDisassembler::Success;
1076 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1079 const void *Decoder) {
1080 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1081 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1082 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1084 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1085 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1087 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1088 Inst.addOperand(MCOperand::CreateReg(Rt));
1091 Inst.addOperand(MCOperand::CreateReg(Rt));
1092 Inst.addOperand(MCOperand::CreateReg(Base));
1093 Inst.addOperand(MCOperand::CreateImm(Offset));
1095 return MCDisassembler::Success;
1098 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1101 const void *Decoder) {
1102 // Currently only hardware register 29 is supported.
1104 return MCDisassembler::Fail;
1105 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1106 return MCDisassembler::Success;
1109 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1112 const void *Decoder) {
1113 if (RegNo > 30 || RegNo %2)
1114 return MCDisassembler::Fail;
1117 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1118 Inst.addOperand(MCOperand::CreateReg(Reg));
1119 return MCDisassembler::Success;
1122 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1125 const void *Decoder) {
1127 return MCDisassembler::Fail;
1129 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1130 Inst.addOperand(MCOperand::CreateReg(Reg));
1131 return MCDisassembler::Success;
1134 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1137 const void *Decoder) {
1139 return MCDisassembler::Fail;
1141 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1142 Inst.addOperand(MCOperand::CreateReg(Reg));
1143 return MCDisassembler::Success;
1146 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1149 const void *Decoder) {
1151 return MCDisassembler::Fail;
1153 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1154 Inst.addOperand(MCOperand::CreateReg(Reg));
1155 return MCDisassembler::Success;
1158 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1161 const void *Decoder) {
1163 return MCDisassembler::Fail;
1165 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1166 Inst.addOperand(MCOperand::CreateReg(Reg));
1167 return MCDisassembler::Success;
1170 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1173 const void *Decoder) {
1175 return MCDisassembler::Fail;
1177 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1178 Inst.addOperand(MCOperand::CreateReg(Reg));
1179 return MCDisassembler::Success;
1182 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1185 const void *Decoder) {
1187 return MCDisassembler::Fail;
1189 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1190 Inst.addOperand(MCOperand::CreateReg(Reg));
1191 return MCDisassembler::Success;
1194 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1197 const void *Decoder) {
1199 return MCDisassembler::Fail;
1201 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1202 Inst.addOperand(MCOperand::CreateReg(Reg));
1203 return MCDisassembler::Success;
1206 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1209 const void *Decoder) {
1211 return MCDisassembler::Fail;
1213 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1214 Inst.addOperand(MCOperand::CreateReg(Reg));
1215 return MCDisassembler::Success;
1218 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1221 const void *Decoder) {
1223 return MCDisassembler::Fail;
1225 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1226 Inst.addOperand(MCOperand::CreateReg(Reg));
1227 return MCDisassembler::Success;
1230 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1233 const void *Decoder) {
1234 int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4;
1235 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1236 return MCDisassembler::Success;
1239 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1242 const void *Decoder) {
1244 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1245 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1246 return MCDisassembler::Success;
1249 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1252 const void *Decoder) {
1253 int32_t BranchOffset = SignExtend32<21>(Offset) << 2;
1255 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1256 return MCDisassembler::Success;
1259 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1262 const void *Decoder) {
1263 int32_t BranchOffset = SignExtend32<26>(Offset) << 2;
1265 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1266 return MCDisassembler::Success;
1269 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1272 const void *Decoder) {
1273 int32_t BranchOffset = SignExtend32<16>(Offset) << 1;
1274 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1275 return MCDisassembler::Success;
1278 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1281 const void *Decoder) {
1282 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1283 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1284 return MCDisassembler::Success;
1287 static DecodeStatus DecodeSimm16(MCInst &Inst,
1290 const void *Decoder) {
1291 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1292 return MCDisassembler::Success;
1295 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1298 const void *Decoder) {
1299 // We add one to the immediate field as it was encoded as 'imm - 1'.
1300 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1301 return MCDisassembler::Success;
1304 static DecodeStatus DecodeInsSize(MCInst &Inst,
1307 const void *Decoder) {
1308 // First we need to grab the pos(lsb) from MCInst.
1309 int Pos = Inst.getOperand(2).getImm();
1310 int Size = (int) Insn - Pos + 1;
1311 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1312 return MCDisassembler::Success;
1315 static DecodeStatus DecodeExtSize(MCInst &Inst,
1318 const void *Decoder) {
1319 int Size = (int) Insn + 1;
1320 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1321 return MCDisassembler::Success;
1324 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1325 uint64_t Address, const void *Decoder) {
1326 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));
1327 return MCDisassembler::Success;
1330 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1331 uint64_t Address, const void *Decoder) {
1332 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) << 3));
1333 return MCDisassembler::Success;