1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
27 #define DEBUG_TYPE "mips-disassembler"
29 typedef MCDisassembler::DecodeStatus DecodeStatus;
33 class MipsDisassembler : public MCDisassembler {
37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
38 : MCDisassembler(STI, Ctx),
39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
40 IsBigEndian(IsBigEndian) {}
42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
44 bool hasMips32r6() const {
45 return STI.getFeatureBits()[Mips::FeatureMips32r6];
48 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
50 bool hasCOP3() const {
51 // Only present in MIPS-I and MIPS-II
52 return !hasMips32() && !hasMips3();
55 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
56 ArrayRef<uint8_t> Bytes, uint64_t Address,
58 raw_ostream &CStream) const override;
61 } // end anonymous namespace
63 // Forward declare these because the autogenerated code will reference them.
64 // Definitions are further down.
65 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
70 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
75 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
80 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
85 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
90 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
95 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
100 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
103 const void *Decoder);
105 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
108 const void *Decoder);
110 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
113 const void *Decoder);
115 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
118 const void *Decoder);
120 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
123 const void *Decoder);
125 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
127 const void *Decoder);
129 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
132 const void *Decoder);
134 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
137 const void *Decoder);
139 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
142 const void *Decoder);
144 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
147 const void *Decoder);
149 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
152 const void *Decoder);
154 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
157 const void *Decoder);
159 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
162 const void *Decoder);
164 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
167 const void *Decoder);
169 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
172 const void *Decoder);
174 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
177 const void *Decoder);
179 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
182 const void *Decoder);
184 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
187 const void *Decoder);
189 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
192 const void *Decoder);
194 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
197 const void *Decoder);
199 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
202 const void *Decoder);
204 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
205 // shifted left by 1 bit.
206 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
209 const void *Decoder);
211 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
212 // shifted left by 1 bit.
213 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
216 const void *Decoder);
218 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
219 // shifted left by 1 bit.
220 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
223 const void *Decoder);
225 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
226 // shifted left by 1 bit.
227 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
230 const void *Decoder);
232 static DecodeStatus DecodeMem(MCInst &Inst,
235 const void *Decoder);
237 static DecodeStatus DecodeCacheOp(MCInst &Inst,
240 const void *Decoder);
242 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
245 const void *Decoder);
247 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
250 const void *Decoder);
252 static DecodeStatus DecodeSyncI(MCInst &Inst,
255 const void *Decoder);
257 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
258 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
263 const void *Decoder);
265 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
268 const void *Decoder);
270 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
273 const void *Decoder);
275 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
278 const void *Decoder);
280 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
283 const void *Decoder);
285 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
288 const void *Decoder);
290 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
292 const void *Decoder);
294 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
296 const void *Decoder);
298 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
300 const void *Decoder);
302 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
304 const void *Decoder);
306 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
309 const void *Decoder);
311 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
314 const void *Decoder);
316 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
319 const void *Decoder);
321 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
324 const void *Decoder);
326 static DecodeStatus DecodeSimm4(MCInst &Inst,
329 const void *Decoder);
331 static DecodeStatus DecodeSimm16(MCInst &Inst,
334 const void *Decoder);
336 // Decode the immediate field of an LSA instruction which
338 static DecodeStatus DecodeLSAImm(MCInst &Inst,
341 const void *Decoder);
343 static DecodeStatus DecodeInsSize(MCInst &Inst,
346 const void *Decoder);
348 static DecodeStatus DecodeExtSize(MCInst &Inst,
351 const void *Decoder);
353 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
354 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
357 uint64_t Address, const void *Decoder);
359 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
360 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
363 uint64_t Address, const void *Decoder);
365 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
366 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
369 uint64_t Address, const void *Decoder);
371 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
373 template <typename InsnType>
374 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
375 const void *Decoder);
377 template <typename InsnType>
379 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
380 const void *Decoder);
382 template <typename InsnType>
384 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
385 const void *Decoder);
387 template <typename InsnType>
389 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
390 const void *Decoder);
392 template <typename InsnType>
394 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
395 const void *Decoder);
397 template <typename InsnType>
399 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
400 const void *Decoder);
402 template <typename InsnType>
404 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
405 const void *Decoder);
407 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
409 const void *Decoder);
411 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
413 const void *Decoder);
415 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
417 const void *Decoder);
420 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
424 static MCDisassembler *createMipsDisassembler(
426 const MCSubtargetInfo &STI,
428 return new MipsDisassembler(STI, Ctx, true);
431 static MCDisassembler *createMipselDisassembler(
433 const MCSubtargetInfo &STI,
435 return new MipsDisassembler(STI, Ctx, false);
438 extern "C" void LLVMInitializeMipsDisassembler() {
439 // Register the disassembler.
440 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
441 createMipsDisassembler);
442 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
443 createMipselDisassembler);
444 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
445 createMipsDisassembler);
446 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
447 createMipselDisassembler);
450 #include "MipsGenDisassemblerTables.inc"
452 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
453 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
454 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
455 return *(RegInfo->getRegClass(RC).begin() + RegNo);
458 template <typename InsnType>
459 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
460 const void *Decoder) {
461 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
462 // The size of the n field depends on the element size
463 // The register class also depends on this.
464 InsnType tmp = fieldFromInstruction(insn, 17, 5);
466 DecodeFN RegDecoder = nullptr;
467 if ((tmp & 0x18) == 0x00) { // INSVE_B
469 RegDecoder = DecodeMSA128BRegisterClass;
470 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
472 RegDecoder = DecodeMSA128HRegisterClass;
473 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
475 RegDecoder = DecodeMSA128WRegisterClass;
476 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
478 RegDecoder = DecodeMSA128DRegisterClass;
480 llvm_unreachable("Invalid encoding");
482 assert(NSize != 0 && RegDecoder != nullptr);
485 tmp = fieldFromInstruction(insn, 6, 5);
486 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
487 return MCDisassembler::Fail;
489 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
490 return MCDisassembler::Fail;
492 tmp = fieldFromInstruction(insn, 16, NSize);
493 MI.addOperand(MCOperand::createImm(tmp));
495 tmp = fieldFromInstruction(insn, 11, 5);
496 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
497 return MCDisassembler::Fail;
499 MI.addOperand(MCOperand::createImm(0));
501 return MCDisassembler::Success;
504 template <typename InsnType>
505 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
507 const void *Decoder) {
508 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
509 // (otherwise we would have matched the ADDI instruction from the earlier
513 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
515 // BEQZALC if rs == 0 && rt != 0
516 // BEQC if rs < rt && rs != 0
518 InsnType Rs = fieldFromInstruction(insn, 21, 5);
519 InsnType Rt = fieldFromInstruction(insn, 16, 5);
520 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
524 MI.setOpcode(Mips::BOVC);
526 } else if (Rs != 0 && Rs < Rt) {
527 MI.setOpcode(Mips::BEQC);
530 MI.setOpcode(Mips::BEQZALC);
533 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
536 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
538 MI.addOperand(MCOperand::createImm(Imm));
540 return MCDisassembler::Success;
543 template <typename InsnType>
544 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
546 const void *Decoder) {
547 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
548 // (otherwise we would have matched the ADDI instruction from the earlier
552 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
554 // BNEZALC if rs == 0 && rt != 0
555 // BNEC if rs < rt && rs != 0
557 InsnType Rs = fieldFromInstruction(insn, 21, 5);
558 InsnType Rt = fieldFromInstruction(insn, 16, 5);
559 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
563 MI.setOpcode(Mips::BNVC);
565 } else if (Rs != 0 && Rs < Rt) {
566 MI.setOpcode(Mips::BNEC);
569 MI.setOpcode(Mips::BNEZALC);
572 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
575 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
577 MI.addOperand(MCOperand::createImm(Imm));
579 return MCDisassembler::Success;
582 template <typename InsnType>
583 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
585 const void *Decoder) {
586 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
587 // (otherwise we would have matched the BLEZL instruction from the earlier
591 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
592 // Invalid if rs == 0
593 // BLEZC if rs == 0 && rt != 0
594 // BGEZC if rs == rt && rt != 0
595 // BGEC if rs != rt && rs != 0 && rt != 0
597 InsnType Rs = fieldFromInstruction(insn, 21, 5);
598 InsnType Rt = fieldFromInstruction(insn, 16, 5);
599 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
603 return MCDisassembler::Fail;
605 MI.setOpcode(Mips::BLEZC);
607 MI.setOpcode(Mips::BGEZC);
610 MI.setOpcode(Mips::BGEC);
614 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
620 MI.addOperand(MCOperand::createImm(Imm));
622 return MCDisassembler::Success;
625 template <typename InsnType>
626 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
628 const void *Decoder) {
629 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
630 // (otherwise we would have matched the BGTZL instruction from the earlier
634 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
635 // Invalid if rs == 0
636 // BGTZC if rs == 0 && rt != 0
637 // BLTZC if rs == rt && rt != 0
638 // BLTC if rs != rt && rs != 0 && rt != 0
642 InsnType Rs = fieldFromInstruction(insn, 21, 5);
643 InsnType Rt = fieldFromInstruction(insn, 16, 5);
644 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
647 return MCDisassembler::Fail;
649 MI.setOpcode(Mips::BGTZC);
651 MI.setOpcode(Mips::BLTZC);
653 MI.setOpcode(Mips::BLTC);
658 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
661 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
664 MI.addOperand(MCOperand::createImm(Imm));
666 return MCDisassembler::Success;
669 template <typename InsnType>
670 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
672 const void *Decoder) {
673 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
674 // (otherwise we would have matched the BGTZ instruction from the earlier
678 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
680 // BGTZALC if rs == 0 && rt != 0
681 // BLTZALC if rs != 0 && rs == rt
682 // BLTUC if rs != 0 && rs != rt
684 InsnType Rs = fieldFromInstruction(insn, 21, 5);
685 InsnType Rt = fieldFromInstruction(insn, 16, 5);
686 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
691 MI.setOpcode(Mips::BGTZ);
693 } else if (Rs == 0) {
694 MI.setOpcode(Mips::BGTZALC);
696 } else if (Rs == Rt) {
697 MI.setOpcode(Mips::BLTZALC);
700 MI.setOpcode(Mips::BLTUC);
706 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
710 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
713 MI.addOperand(MCOperand::createImm(Imm));
715 return MCDisassembler::Success;
718 template <typename InsnType>
719 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
721 const void *Decoder) {
722 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
723 // (otherwise we would have matched the BLEZL instruction from the earlier
727 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
728 // Invalid if rs == 0
729 // BLEZALC if rs == 0 && rt != 0
730 // BGEZALC if rs == rt && rt != 0
731 // BGEUC if rs != rt && rs != 0 && rt != 0
733 InsnType Rs = fieldFromInstruction(insn, 21, 5);
734 InsnType Rt = fieldFromInstruction(insn, 16, 5);
735 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
739 return MCDisassembler::Fail;
741 MI.setOpcode(Mips::BLEZALC);
743 MI.setOpcode(Mips::BGEZALC);
746 MI.setOpcode(Mips::BGEUC);
750 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
752 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
755 MI.addOperand(MCOperand::createImm(Imm));
757 return MCDisassembler::Success;
760 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
761 /// according to the given endianess.
762 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
763 uint64_t &Size, uint32_t &Insn,
765 // We want to read exactly 2 Bytes of data.
766 if (Bytes.size() < 2) {
768 return MCDisassembler::Fail;
772 Insn = (Bytes[0] << 8) | Bytes[1];
774 Insn = (Bytes[1] << 8) | Bytes[0];
777 return MCDisassembler::Success;
780 /// Read four bytes from the ArrayRef and return 32 bit word sorted
781 /// according to the given endianess
782 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
783 uint64_t &Size, uint32_t &Insn,
784 bool IsBigEndian, bool IsMicroMips) {
785 // We want to read exactly 4 Bytes of data.
786 if (Bytes.size() < 4) {
788 return MCDisassembler::Fail;
791 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
792 // always precede the low 16 bits in the instruction stream (that is, they
793 // are placed at lower addresses in the instruction stream).
795 // microMIPS byte ordering:
796 // Big-endian: 0 | 1 | 2 | 3
797 // Little-endian: 1 | 0 | 3 | 2
800 // Encoded as a big-endian 32-bit word in the stream.
802 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
805 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
808 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
813 return MCDisassembler::Success;
816 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
817 ArrayRef<uint8_t> Bytes,
819 raw_ostream &VStream,
820 raw_ostream &CStream) const {
825 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
827 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
828 // Calling the auto-generated decoder function.
829 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
831 if (Result != MCDisassembler::Fail) {
836 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
837 if (Result == MCDisassembler::Fail)
838 return MCDisassembler::Fail;
841 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
842 // Calling the auto-generated decoder function.
843 Result = decodeInstruction(DecoderTableMicroMips32r632, Instr, Insn, Address,
846 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
847 // Calling the auto-generated decoder function.
848 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
851 if (Result != MCDisassembler::Fail) {
855 return MCDisassembler::Fail;
858 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
859 if (Result == MCDisassembler::Fail)
860 return MCDisassembler::Fail;
863 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
865 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
866 if (Result != MCDisassembler::Fail) {
872 if (hasMips32r6() && isGP64()) {
873 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
874 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
876 if (Result != MCDisassembler::Fail) {
883 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
884 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
886 if (Result != MCDisassembler::Fail) {
893 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
894 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
896 if (Result != MCDisassembler::Fail) {
902 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
903 // Calling the auto-generated decoder function.
905 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
906 if (Result != MCDisassembler::Fail) {
911 return MCDisassembler::Fail;
914 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
917 const void *Decoder) {
919 return MCDisassembler::Fail;
923 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
926 const void *Decoder) {
929 return MCDisassembler::Fail;
931 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
932 Inst.addOperand(MCOperand::createReg(Reg));
933 return MCDisassembler::Success;
936 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
939 const void *Decoder) {
941 return MCDisassembler::Fail;
942 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
943 Inst.addOperand(MCOperand::createReg(Reg));
944 return MCDisassembler::Success;
947 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
950 const void *Decoder) {
952 return MCDisassembler::Fail;
953 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
954 Inst.addOperand(MCOperand::createReg(Reg));
955 return MCDisassembler::Success;
958 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
961 const void *Decoder) {
963 return MCDisassembler::Fail;
964 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
965 Inst.addOperand(MCOperand::createReg(Reg));
966 return MCDisassembler::Success;
969 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
972 const void *Decoder) {
974 return MCDisassembler::Fail;
975 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
976 Inst.addOperand(MCOperand::createReg(Reg));
977 return MCDisassembler::Success;
980 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
983 const void *Decoder) {
984 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
985 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
987 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
990 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
993 const void *Decoder) {
994 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
997 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1000 const void *Decoder) {
1002 return MCDisassembler::Fail;
1004 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1005 Inst.addOperand(MCOperand::createReg(Reg));
1006 return MCDisassembler::Success;
1009 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1012 const void *Decoder) {
1014 return MCDisassembler::Fail;
1016 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1017 Inst.addOperand(MCOperand::createReg(Reg));
1018 return MCDisassembler::Success;
1021 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1024 const void *Decoder) {
1026 return MCDisassembler::Fail;
1027 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1028 Inst.addOperand(MCOperand::createReg(Reg));
1029 return MCDisassembler::Success;
1032 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1035 const void *Decoder) {
1037 return MCDisassembler::Fail;
1038 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1039 Inst.addOperand(MCOperand::createReg(Reg));
1040 return MCDisassembler::Success;
1043 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1045 const void *Decoder) {
1047 return MCDisassembler::Fail;
1049 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1050 Inst.addOperand(MCOperand::createReg(Reg));
1051 return MCDisassembler::Success;
1054 static DecodeStatus DecodeMem(MCInst &Inst,
1057 const void *Decoder) {
1058 int Offset = SignExtend32<16>(Insn & 0xffff);
1059 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1060 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1062 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1063 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1065 if(Inst.getOpcode() == Mips::SC ||
1066 Inst.getOpcode() == Mips::SCD){
1067 Inst.addOperand(MCOperand::createReg(Reg));
1070 Inst.addOperand(MCOperand::createReg(Reg));
1071 Inst.addOperand(MCOperand::createReg(Base));
1072 Inst.addOperand(MCOperand::createImm(Offset));
1074 return MCDisassembler::Success;
1077 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1080 const void *Decoder) {
1081 int Offset = SignExtend32<16>(Insn & 0xffff);
1082 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1083 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1085 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1087 Inst.addOperand(MCOperand::createReg(Base));
1088 Inst.addOperand(MCOperand::createImm(Offset));
1089 Inst.addOperand(MCOperand::createImm(Hint));
1091 return MCDisassembler::Success;
1094 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1097 const void *Decoder) {
1098 int Offset = SignExtend32<12>(Insn & 0xfff);
1099 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1100 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1102 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1104 Inst.addOperand(MCOperand::createReg(Base));
1105 Inst.addOperand(MCOperand::createImm(Offset));
1106 Inst.addOperand(MCOperand::createImm(Hint));
1108 return MCDisassembler::Success;
1111 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
1114 const void *Decoder) {
1115 int Offset = fieldFromInstruction(Insn, 7, 9);
1116 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1117 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1119 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1121 Inst.addOperand(MCOperand::createReg(Base));
1122 Inst.addOperand(MCOperand::createImm(Offset));
1123 Inst.addOperand(MCOperand::createImm(Hint));
1125 return MCDisassembler::Success;
1128 static DecodeStatus DecodeSyncI(MCInst &Inst,
1131 const void *Decoder) {
1132 int Offset = SignExtend32<16>(Insn & 0xffff);
1133 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1135 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1137 Inst.addOperand(MCOperand::createReg(Base));
1138 Inst.addOperand(MCOperand::createImm(Offset));
1140 return MCDisassembler::Success;
1143 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1144 uint64_t Address, const void *Decoder) {
1145 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1146 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1147 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1149 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1150 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1152 Inst.addOperand(MCOperand::createReg(Reg));
1153 Inst.addOperand(MCOperand::createReg(Base));
1155 // The immediate field of an LD/ST instruction is scaled which means it must
1156 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1162 switch(Inst.getOpcode())
1165 assert (0 && "Unexpected instruction");
1166 return MCDisassembler::Fail;
1170 Inst.addOperand(MCOperand::createImm(Offset));
1174 Inst.addOperand(MCOperand::createImm(Offset * 2));
1178 Inst.addOperand(MCOperand::createImm(Offset * 4));
1182 Inst.addOperand(MCOperand::createImm(Offset * 8));
1186 return MCDisassembler::Success;
1189 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1192 const void *Decoder) {
1193 unsigned Offset = Insn & 0xf;
1194 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1195 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1197 switch (Inst.getOpcode()) {
1198 case Mips::LBU16_MM:
1199 case Mips::LHU16_MM:
1201 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1202 == MCDisassembler::Fail)
1203 return MCDisassembler::Fail;
1208 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1209 == MCDisassembler::Fail)
1210 return MCDisassembler::Fail;
1214 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1215 == MCDisassembler::Fail)
1216 return MCDisassembler::Fail;
1218 switch (Inst.getOpcode()) {
1219 case Mips::LBU16_MM:
1221 Inst.addOperand(MCOperand::createImm(-1));
1223 Inst.addOperand(MCOperand::createImm(Offset));
1226 Inst.addOperand(MCOperand::createImm(Offset));
1228 case Mips::LHU16_MM:
1230 Inst.addOperand(MCOperand::createImm(Offset << 1));
1234 Inst.addOperand(MCOperand::createImm(Offset << 2));
1238 return MCDisassembler::Success;
1241 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1244 const void *Decoder) {
1245 unsigned Offset = Insn & 0x1F;
1246 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1248 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1250 Inst.addOperand(MCOperand::createReg(Reg));
1251 Inst.addOperand(MCOperand::createReg(Mips::SP));
1252 Inst.addOperand(MCOperand::createImm(Offset << 2));
1254 return MCDisassembler::Success;
1257 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1260 const void *Decoder) {
1261 unsigned Offset = Insn & 0x7F;
1262 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1264 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1266 Inst.addOperand(MCOperand::createReg(Reg));
1267 Inst.addOperand(MCOperand::createReg(Mips::GP));
1268 Inst.addOperand(MCOperand::createImm(Offset << 2));
1270 return MCDisassembler::Success;
1273 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1276 const void *Decoder) {
1277 int Offset = SignExtend32<4>(Insn & 0xf);
1279 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1280 == MCDisassembler::Fail)
1281 return MCDisassembler::Fail;
1283 Inst.addOperand(MCOperand::createReg(Mips::SP));
1284 Inst.addOperand(MCOperand::createImm(Offset << 2));
1286 return MCDisassembler::Success;
1289 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1292 const void *Decoder) {
1293 int Offset = SignExtend32<12>(Insn & 0x0fff);
1294 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1295 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1297 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1298 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1300 switch (Inst.getOpcode()) {
1301 case Mips::SWM32_MM:
1302 case Mips::LWM32_MM:
1303 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1304 == MCDisassembler::Fail)
1305 return MCDisassembler::Fail;
1306 Inst.addOperand(MCOperand::createReg(Base));
1307 Inst.addOperand(MCOperand::createImm(Offset));
1310 Inst.addOperand(MCOperand::createReg(Reg));
1313 Inst.addOperand(MCOperand::createReg(Reg));
1314 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1315 Inst.addOperand(MCOperand::createReg(Reg+1));
1317 Inst.addOperand(MCOperand::createReg(Base));
1318 Inst.addOperand(MCOperand::createImm(Offset));
1321 return MCDisassembler::Success;
1324 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1327 const void *Decoder) {
1328 int Offset = SignExtend32<16>(Insn & 0xffff);
1329 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1330 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1332 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1333 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1335 Inst.addOperand(MCOperand::createReg(Reg));
1336 Inst.addOperand(MCOperand::createReg(Base));
1337 Inst.addOperand(MCOperand::createImm(Offset));
1339 return MCDisassembler::Success;
1342 static DecodeStatus DecodeFMem(MCInst &Inst,
1345 const void *Decoder) {
1346 int Offset = SignExtend32<16>(Insn & 0xffff);
1347 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1348 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1350 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1351 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1353 Inst.addOperand(MCOperand::createReg(Reg));
1354 Inst.addOperand(MCOperand::createReg(Base));
1355 Inst.addOperand(MCOperand::createImm(Offset));
1357 return MCDisassembler::Success;
1360 static DecodeStatus DecodeFMem2(MCInst &Inst,
1363 const void *Decoder) {
1364 int Offset = SignExtend32<16>(Insn & 0xffff);
1365 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1366 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1368 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1369 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1371 Inst.addOperand(MCOperand::createReg(Reg));
1372 Inst.addOperand(MCOperand::createReg(Base));
1373 Inst.addOperand(MCOperand::createImm(Offset));
1375 return MCDisassembler::Success;
1378 static DecodeStatus DecodeFMem3(MCInst &Inst,
1381 const void *Decoder) {
1382 int Offset = SignExtend32<16>(Insn & 0xffff);
1383 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1384 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1386 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1387 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1389 Inst.addOperand(MCOperand::createReg(Reg));
1390 Inst.addOperand(MCOperand::createReg(Base));
1391 Inst.addOperand(MCOperand::createImm(Offset));
1393 return MCDisassembler::Success;
1396 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1399 const void *Decoder) {
1400 int Offset = SignExtend32<11>(Insn & 0x07ff);
1401 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1402 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1404 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1405 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1407 Inst.addOperand(MCOperand::createReg(Reg));
1408 Inst.addOperand(MCOperand::createReg(Base));
1409 Inst.addOperand(MCOperand::createImm(Offset));
1411 return MCDisassembler::Success;
1413 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1416 const void *Decoder) {
1417 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1418 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1419 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1421 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1422 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1424 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1425 Inst.addOperand(MCOperand::createReg(Rt));
1428 Inst.addOperand(MCOperand::createReg(Rt));
1429 Inst.addOperand(MCOperand::createReg(Base));
1430 Inst.addOperand(MCOperand::createImm(Offset));
1432 return MCDisassembler::Success;
1435 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1438 const void *Decoder) {
1439 // Currently only hardware register 29 is supported.
1441 return MCDisassembler::Fail;
1442 Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1443 return MCDisassembler::Success;
1446 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1449 const void *Decoder) {
1450 if (RegNo > 30 || RegNo %2)
1451 return MCDisassembler::Fail;
1454 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1455 Inst.addOperand(MCOperand::createReg(Reg));
1456 return MCDisassembler::Success;
1459 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1462 const void *Decoder) {
1464 return MCDisassembler::Fail;
1466 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1467 Inst.addOperand(MCOperand::createReg(Reg));
1468 return MCDisassembler::Success;
1471 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1474 const void *Decoder) {
1476 return MCDisassembler::Fail;
1478 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1479 Inst.addOperand(MCOperand::createReg(Reg));
1480 return MCDisassembler::Success;
1483 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1486 const void *Decoder) {
1488 return MCDisassembler::Fail;
1490 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1491 Inst.addOperand(MCOperand::createReg(Reg));
1492 return MCDisassembler::Success;
1495 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1498 const void *Decoder) {
1500 return MCDisassembler::Fail;
1502 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1503 Inst.addOperand(MCOperand::createReg(Reg));
1504 return MCDisassembler::Success;
1507 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1510 const void *Decoder) {
1512 return MCDisassembler::Fail;
1514 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1515 Inst.addOperand(MCOperand::createReg(Reg));
1516 return MCDisassembler::Success;
1519 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1522 const void *Decoder) {
1524 return MCDisassembler::Fail;
1526 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1527 Inst.addOperand(MCOperand::createReg(Reg));
1528 return MCDisassembler::Success;
1531 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1534 const void *Decoder) {
1536 return MCDisassembler::Fail;
1538 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1539 Inst.addOperand(MCOperand::createReg(Reg));
1540 return MCDisassembler::Success;
1543 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1546 const void *Decoder) {
1548 return MCDisassembler::Fail;
1550 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1551 Inst.addOperand(MCOperand::createReg(Reg));
1552 return MCDisassembler::Success;
1555 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1558 const void *Decoder) {
1560 return MCDisassembler::Fail;
1562 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1563 Inst.addOperand(MCOperand::createReg(Reg));
1564 return MCDisassembler::Success;
1567 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1570 const void *Decoder) {
1571 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1572 Inst.addOperand(MCOperand::createImm(BranchOffset));
1573 return MCDisassembler::Success;
1576 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1579 const void *Decoder) {
1581 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1582 Inst.addOperand(MCOperand::createImm(JumpOffset));
1583 return MCDisassembler::Success;
1586 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1589 const void *Decoder) {
1590 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1592 Inst.addOperand(MCOperand::createImm(BranchOffset));
1593 return MCDisassembler::Success;
1596 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1599 const void *Decoder) {
1600 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1602 Inst.addOperand(MCOperand::createImm(BranchOffset));
1603 return MCDisassembler::Success;
1606 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1609 const void *Decoder) {
1610 int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1611 Inst.addOperand(MCOperand::createImm(BranchOffset));
1612 return MCDisassembler::Success;
1615 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1618 const void *Decoder) {
1619 int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1620 Inst.addOperand(MCOperand::createImm(BranchOffset));
1621 return MCDisassembler::Success;
1624 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1627 const void *Decoder) {
1628 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1629 Inst.addOperand(MCOperand::createImm(BranchOffset));
1630 return MCDisassembler::Success;
1633 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1636 const void *Decoder) {
1637 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1638 Inst.addOperand(MCOperand::createImm(JumpOffset));
1639 return MCDisassembler::Success;
1642 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1645 const void *Decoder) {
1647 Inst.addOperand(MCOperand::createImm(1));
1648 else if (Value == 0x7)
1649 Inst.addOperand(MCOperand::createImm(-1));
1651 Inst.addOperand(MCOperand::createImm(Value << 2));
1652 return MCDisassembler::Success;
1655 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1658 const void *Decoder) {
1659 Inst.addOperand(MCOperand::createImm(Value << 2));
1660 return MCDisassembler::Success;
1663 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1666 const void *Decoder) {
1668 Inst.addOperand(MCOperand::createImm(-1));
1670 Inst.addOperand(MCOperand::createImm(Value));
1671 return MCDisassembler::Success;
1674 static DecodeStatus DecodeSimm4(MCInst &Inst,
1677 const void *Decoder) {
1678 Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
1679 return MCDisassembler::Success;
1682 static DecodeStatus DecodeSimm16(MCInst &Inst,
1685 const void *Decoder) {
1686 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
1687 return MCDisassembler::Success;
1690 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1693 const void *Decoder) {
1694 // We add one to the immediate field as it was encoded as 'imm - 1'.
1695 Inst.addOperand(MCOperand::createImm(Insn + 1));
1696 return MCDisassembler::Success;
1699 static DecodeStatus DecodeInsSize(MCInst &Inst,
1702 const void *Decoder) {
1703 // First we need to grab the pos(lsb) from MCInst.
1704 int Pos = Inst.getOperand(2).getImm();
1705 int Size = (int) Insn - Pos + 1;
1706 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1707 return MCDisassembler::Success;
1710 static DecodeStatus DecodeExtSize(MCInst &Inst,
1713 const void *Decoder) {
1714 int Size = (int) Insn + 1;
1715 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1716 return MCDisassembler::Success;
1719 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1720 uint64_t Address, const void *Decoder) {
1721 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1722 return MCDisassembler::Success;
1725 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1726 uint64_t Address, const void *Decoder) {
1727 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1728 return MCDisassembler::Success;
1731 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1732 uint64_t Address, const void *Decoder) {
1733 int32_t DecodedValue;
1735 case 0: DecodedValue = 256; break;
1736 case 1: DecodedValue = 257; break;
1737 case 510: DecodedValue = -258; break;
1738 case 511: DecodedValue = -257; break;
1739 default: DecodedValue = SignExtend32<9>(Insn); break;
1741 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1742 return MCDisassembler::Success;
1745 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1746 uint64_t Address, const void *Decoder) {
1747 // Insn must be >= 0, since it is unsigned that condition is always true.
1749 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1751 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1752 return MCDisassembler::Success;
1755 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1756 uint64_t Address, const void *Decoder) {
1757 Inst.addOperand(MCOperand::createImm(Insn << 2));
1758 return MCDisassembler::Success;
1761 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1764 const void *Decoder) {
1765 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1766 Mips::S6, Mips::FP};
1769 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1770 // Empty register lists are not allowed.
1772 return MCDisassembler::Fail;
1774 RegNum = RegLst & 0xf;
1775 for (unsigned i = 0; i < RegNum; i++)
1776 Inst.addOperand(MCOperand::createReg(Regs[i]));
1779 Inst.addOperand(MCOperand::createReg(Mips::RA));
1781 return MCDisassembler::Success;
1784 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1786 const void *Decoder) {
1787 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1788 unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1789 unsigned RegNum = RegLst & 0x3;
1791 for (unsigned i = 0; i <= RegNum; i++)
1792 Inst.addOperand(MCOperand::createReg(Regs[i]));
1794 Inst.addOperand(MCOperand::createReg(Mips::RA));
1796 return MCDisassembler::Success;
1799 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
1800 uint64_t Address, const void *Decoder) {
1802 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1806 return MCDisassembler::Fail;
1808 Inst.addOperand(MCOperand::createReg(Mips::A1));
1809 Inst.addOperand(MCOperand::createReg(Mips::A2));
1812 Inst.addOperand(MCOperand::createReg(Mips::A1));
1813 Inst.addOperand(MCOperand::createReg(Mips::A3));
1816 Inst.addOperand(MCOperand::createReg(Mips::A2));
1817 Inst.addOperand(MCOperand::createReg(Mips::A3));
1820 Inst.addOperand(MCOperand::createReg(Mips::A0));
1821 Inst.addOperand(MCOperand::createReg(Mips::S5));
1824 Inst.addOperand(MCOperand::createReg(Mips::A0));
1825 Inst.addOperand(MCOperand::createReg(Mips::S6));
1828 Inst.addOperand(MCOperand::createReg(Mips::A0));
1829 Inst.addOperand(MCOperand::createReg(Mips::A1));
1832 Inst.addOperand(MCOperand::createReg(Mips::A0));
1833 Inst.addOperand(MCOperand::createReg(Mips::A2));
1836 Inst.addOperand(MCOperand::createReg(Mips::A0));
1837 Inst.addOperand(MCOperand::createReg(Mips::A3));
1841 return MCDisassembler::Success;
1844 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1845 uint64_t Address, const void *Decoder) {
1846 Inst.addOperand(MCOperand::createImm(SignExtend32<23>(Insn) << 2));
1847 return MCDisassembler::Success;